From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661210961; cv=none; d=zohomail.com; s=zohoarc; b=ag6XaSWC/rioFwHADz5WlIJ8tDIxZkarcvFLiwJ4I4fX1fskC4znHhjaE+KhtkYgKI/AgecWiKlf5aTf732ZSrZXvVtnQEJlsynY0upnNGD08Vuh29qVahlV5wxx/Zqr5L5R3TS6uuipWve8mCPqtIFMhYmQzarzSja1g/4TIr8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661210961; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u1rNx+z6mfX9QOf0swX80lotmkBIQnUrgYcTWCQuCO0=; b=BUV2sgPKYO5A5OuccHSo8xRFuH0Fo7O8YUYStQJL5AcD/jSj9VzI98LVQIkg7eyM0I9wqyqtQoQyUp0jtnTq9/UKW/0ygJV5VZ+ErshKOQiG0JhwTwywj7ZXvsFVca+gKUdZPOk6SB2hZrOxBZ6uXXLGIIdDV5DqNOID3Uj4Qgw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661210961728169.6002448190127; Mon, 22 Aug 2022 16:29:21 -0700 (PDT) Received: from localhost ([::1]:40310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGrA-00080u-OK for importer@patchew.org; Mon, 22 Aug 2022 19:29:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlp-0005cz-8W for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:49 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:36699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGli-0005aW-JU for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:45 -0400 Received: by mail-pf1-x433.google.com with SMTP id w29so6259598pfj.3 for ; Mon, 22 Aug 2022 16:23:42 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=u1rNx+z6mfX9QOf0swX80lotmkBIQnUrgYcTWCQuCO0=; b=sdLmjGg43PO9lTKnLfky08DInjwny15HVABQVjuB2+JbRwSPAWwdTSSCHIeDcrYLnq uy6IyNtvnPYIDKyIH/jwuROtaiRgEUBDyNnYdbQjg0ZdPGmuN6tT36MqyIuxsYnvobos WNvPW/uldIAyyYC9zJ1yT6eTmt0d5ekBOTvU2R3ttas2nKByR7ItRezMF+XPlGbLHdWj ozRm2zgMq8aOOhveYdCcY6AYHqYJV4fKWHTpobuHgpqGWGfE0KIwJnHt5EQ8dMQd43ge PyIpKMbk8gwykZRtztzhpNQ8OiQY3pXTySDr2D36sZbnzXDgIKVmbYJRVmd+iRFkpbRm DxqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=u1rNx+z6mfX9QOf0swX80lotmkBIQnUrgYcTWCQuCO0=; b=uDfClVHaKXWYe3DHXjdUF9zKNKcPJbHLKvGsRJA/54owf06XMfI/bbv3a7f0lpe7M5 HcvEwx5WjmyYlbMIumIqbrSGawhHlNecWft7vgK0zQmgoVlsK1PSLGATYCjmPHk2PgWx 10ybXM+Z7+2PkXyEiLbHZgQVT0PWilZYSyX1PewHkt0FoUzeqGy7zsy40YgdDOoOhjjU C6WkgP3Lk61ENzVPyaEait4HvgTvl4eFrGg95ddQ/JIsna8wWRuAMcACEh6WBootLXti LURqdgDmq22PPh/1omcxX5tkzjWKsVapa01Ma8j4sOSI4OgxN79I5G3dk1ExWBGjLi2k 9gdQ== X-Gm-Message-State: ACgBeo0olQWF3yR8Ty507q+nFxn82q3psX/Tnn28yOFhNZoIH1fVz2lm WzV7M8YL4WdEeajqEiMa0QplY5sN5vQI4Q== X-Google-Smtp-Source: AA6agR4Uyqxjsguvnv9p/zAt7Voj87Kp+pX7AM7BiGUYRLAM4SDQGoGFdW05tCISLShmXDQD6bkFXw== X-Received: by 2002:a63:6a46:0:b0:41a:3e67:67cd with SMTP id f67-20020a636a46000000b0041a3e6767cdmr18773197pgc.94.1661210621087; Mon, 22 Aug 2022 16:23:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 01/17] accel/tcg: Remove PageDesc code_bitmap Date: Mon, 22 Aug 2022 16:23:22 -0700 Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210962370100001 Content-Type: text/plain; charset="utf-8" This bitmap is created and discarded immediately. We gain nothing by its existence. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 78 ++------------------------------------- 1 file changed, 4 insertions(+), 74 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index e44f40b234..34bf296250 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -102,21 +102,14 @@ #define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) #endif =20 -#define SMC_BITMAP_USE_THRESHOLD 10 - typedef struct PageDesc { /* list of TBs intersecting this ram page */ uintptr_t first_tb; -#ifdef CONFIG_SOFTMMU - /* in order to optimize self modifying code, we count the number - of lookups we do to a given page to use a bitmap */ - unsigned long *code_bitmap; - unsigned int code_write_count; -#else +#ifdef CONFIG_USER_ONLY unsigned long flags; void *target_data; #endif -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_SOFTMMU QemuSpin lock; #endif } PageDesc; @@ -907,17 +900,6 @@ void tb_htable_init(void) qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode); } =20 -/* call with @p->lock held */ -static inline void invalidate_page_bitmap(PageDesc *p) -{ - assert_page_locked(p); -#ifdef CONFIG_SOFTMMU - g_free(p->code_bitmap); - p->code_bitmap =3D NULL; - p->code_write_count =3D 0; -#endif -} - /* Set to NULL all the 'first_tb' fields in all PageDescs. */ static void page_flush_tb_1(int level, void **lp) { @@ -932,7 +914,6 @@ static void page_flush_tb_1(int level, void **lp) for (i =3D 0; i < V_L2_SIZE; ++i) { page_lock(&pd[i]); pd[i].first_tb =3D (uintptr_t)NULL; - invalidate_page_bitmap(pd + i); page_unlock(&pd[i]); } } else { @@ -1197,11 +1178,9 @@ static void do_tb_phys_invalidate(TranslationBlock *= tb, bool rm_from_page_list) if (rm_from_page_list) { p =3D page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); tb_page_remove(p, tb); - invalidate_page_bitmap(p); if (tb->page_addr[1] !=3D -1) { p =3D page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); tb_page_remove(p, tb); - invalidate_page_bitmap(p); } } =20 @@ -1246,35 +1225,6 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_pag= e_addr_t page_addr) } } =20 -#ifdef CONFIG_SOFTMMU -/* call with @p->lock held */ -static void build_page_bitmap(PageDesc *p) -{ - int n, tb_start, tb_end; - TranslationBlock *tb; - - assert_page_locked(p); - p->code_bitmap =3D bitmap_new(TARGET_PAGE_SIZE); - - PAGE_FOR_EACH_TB(p, tb, n) { - /* NOTE: this is subtle as a TB may span two physical pages */ - if (n =3D=3D 0) { - /* NOTE: tb_end may be after the end of the page, but - it is not a problem */ - tb_start =3D tb->pc & ~TARGET_PAGE_MASK; - tb_end =3D tb_start + tb->size; - if (tb_end > TARGET_PAGE_SIZE) { - tb_end =3D TARGET_PAGE_SIZE; - } - } else { - tb_start =3D 0; - tb_end =3D ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); - } - bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); - } -} -#endif - /* add the tb in the target page and protect it if necessary * * Called with mmap_lock held for user-mode emulation. @@ -1295,7 +1245,6 @@ static inline void tb_page_add(PageDesc *p, Translati= onBlock *tb, page_already_protected =3D p->first_tb !=3D (uintptr_t)NULL; #endif p->first_tb =3D (uintptr_t)tb | n; - invalidate_page_bitmap(p); =20 #if defined(CONFIG_USER_ONLY) /* translator_loop() must have made all TB pages non-writable */ @@ -1357,10 +1306,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t ph= ys_pc, /* remove TB from the page(s) if we couldn't insert it */ if (unlikely(existing_tb)) { tb_page_remove(p, tb); - invalidate_page_bitmap(p); if (p2) { tb_page_remove(p2, tb); - invalidate_page_bitmap(p2); } tb =3D existing_tb; } @@ -1731,7 +1678,6 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, #if !defined(CONFIG_USER_ONLY) /* if no code remaining, no need to continue to use slow writes */ if (!p->first_tb) { - invalidate_page_bitmap(p); tlb_unprotect_code(start); } #endif @@ -1827,24 +1773,8 @@ void tb_invalidate_phys_page_fast(struct page_collec= tion *pages, } =20 assert_page_locked(p); - if (!p->code_bitmap && - ++p->code_write_count >=3D SMC_BITMAP_USE_THRESHOLD) { - build_page_bitmap(p); - } - if (p->code_bitmap) { - unsigned int nr; - unsigned long b; - - nr =3D start & ~TARGET_PAGE_MASK; - b =3D p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); - if (b & ((1 << len) - 1)) { - goto do_invalidate; - } - } else { - do_invalidate: - tb_invalidate_phys_page_range__locked(pages, p, start, start + len, - retaddr); - } + tb_invalidate_phys_page_range__locked(pages, p, start, start + len, + retaddr); } #else /* Called with mmap_lock held. If pc is not 0 then it indicates the --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661210797; cv=none; d=zohomail.com; s=zohoarc; b=kUx/SnCCqKwEgJ1KTHvuuufS3F75ebeDR0YqKoEN4BqXG14HiNxTFLfb+xy4TuFv+djGRkOVyxiKMh1gg8UijlDItDBYA63MbaDA0zRVJRONFngKIVLfFMqfW16zSP9/Qbg+AKidv2kPs3CfpdFc5FRv6keYvsxJZF0K+55pkdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661210797; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eMqYEALQlNCHryVYkn9ayeWYJiH16krDhtfDzKR3N+4=; b=Z+odwqdsDOhWKaIRO4y8Xhps115/0OMJ3HPjI+UlZfiFLjxgfXkJ1Zee8BhMkx7Ve9qA9S7Cw2rmeXUr+9+FX5UEA/1qxxtAvHo2bJlJn7iK3XSGiZTjNeiyU8NkJC2x71PEeWXq+b2ZugW/FvvyzY0rRzvHZGF+txpsBc0uAP8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661210797353802.8037273079038; Mon, 22 Aug 2022 16:26:37 -0700 (PDT) Received: from localhost ([::1]:58462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGoV-00007D-QM for importer@patchew.org; Mon, 22 Aug 2022 19:26:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlp-0005d0-91 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:50 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:54838) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGlj-0005am-L6 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:45 -0400 Received: by mail-pj1-x1030.google.com with SMTP id bf22so12439989pjb.4 for ; Mon, 22 Aug 2022 16:23:43 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=eMqYEALQlNCHryVYkn9ayeWYJiH16krDhtfDzKR3N+4=; b=TYQBcK0MW3DxORsvXbqYjWpE/UmT9qOmwhv9wkrUvhF0j5rA6d5pKvtPzWcYl+9L/T qAvV1jms+Lx3KVQ1w0oVJOTP6V9RgCED3VI7DW0Wmr41+DVB7iFnL0tB2rdVZMZZELP1 GOqwBPzN1BPfoBDd3CMGf5t88lKe44qPn0Z8dezGE4QVRb3d4BE/2NgF/UkJTI53ZcHe TFt8Ynfifin+b5h9vfNuNvUP5sYDFYJSRHX2NDV7AzMKWqmXGfnVDITBA2K6vmUbeuBS 6fkEcoSnRs3k6Nliqc6XHg9gL08+hW76uj7rXLSDwz5pl9p2DdWXpeAf1Irj3GzXGq13 PUAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=eMqYEALQlNCHryVYkn9ayeWYJiH16krDhtfDzKR3N+4=; b=ZYAw68cKxjlcwbCZonAe7FyuuG+ysbqvSlTkJFtgHNCkszo2iH2QTmnXKct0cMdHzj ubeL0OdDFpyedQ1GQXSsQwQxZmSyPjyeM9d6TrJNGnwTll60+CgottKaG8L2ghaqHlxL pf9id/eRcP1bxvFr+g6FZr1XX70EX9+yB81BR5XsAt32pUh+zKM7/D4ts3MJNj4Mi8Tp 4H/2iA4Nw+hOpNtuEVzqQxT4GmZbPZZQL76kPC14rhK65p59ubFToyLmEqYrkinTh8jL lqeHeTPz6/7VGiI+s/7HVdXQsGM/bUWcgp1voBCK8TvCUFF8znrbG7T52yCXdTcqZUK2 HCYA== X-Gm-Message-State: ACgBeo3DQjzWe3cI+th0VRyHg3G2MrAW0JdL9zs+DMIFYm7NAYncQdcF 4chZpXH1AcrD5ubJI1kNcQcRJDX11qGQyg== X-Google-Smtp-Source: AA6agR588Xaw8V5mgt910iXAqfft/VUSQ2ZYw/tRblgtwlvsQt4qvLYBzF9ThYkdb36mIor2LxGMBg== X-Received: by 2002:a17:902:7b95:b0:172:9dc3:6c12 with SMTP id w21-20020a1709027b9500b001729dc36c12mr22486423pll.94.1661210622245; Mon, 22 Aug 2022 16:23:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 02/17] accel/tcg: Use bool for page_find_alloc Date: Mon, 22 Aug 2022 16:23:23 -0700 Message-Id: <20220822232338.1727934-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210799170100001 Content-Type: text/plain; charset="utf-8" Bool is more appropriate type for the alloc parameter. Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 34bf296250..a8f1c34c4e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -465,7 +465,7 @@ void page_init(void) #endif } =20 -static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) +static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc) { PageDesc *pd; void **lp; @@ -533,11 +533,11 @@ static PageDesc *page_find_alloc(tb_page_addr_t index= , int alloc) =20 static inline PageDesc *page_find(tb_page_addr_t index) { - return page_find_alloc(index, 0); + return page_find_alloc(index, false); } =20 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int al= loc); + PageDesc **ret_p2, tb_page_addr_t phys2, bool a= lloc); =20 /* In user-mode page locks aren't used; mmap_lock is enough */ #ifdef CONFIG_USER_ONLY @@ -651,7 +651,7 @@ static inline void page_unlock(PageDesc *pd) /* lock the page(s) of a TB in the correct acquisition order */ static inline void page_lock_tb(const TranslationBlock *tb) { - page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0); + page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false); } =20 static inline void page_unlock_tb(const TranslationBlock *tb) @@ -840,7 +840,7 @@ void page_collection_unlock(struct page_collection *set) #endif /* !CONFIG_USER_ONLY */ =20 static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int al= loc) + PageDesc **ret_p2, tb_page_addr_t phys2, bool a= lloc) { PageDesc *p1, *p2; tb_page_addr_t page1; @@ -1290,7 +1290,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, * Note that inserting into the hash table first isn't an option, since * we can only insert TBs that are fully initialized. */ - page_lock_pair(&p, phys_pc, &p2, phys_page2, 1); + page_lock_pair(&p, phys_pc, &p2, phys_page2, true); tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); if (p2) { tb_page_add(p2, tb, 1, phys_page2); @@ -2219,7 +2219,7 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) for (addr =3D start, len =3D end - start; len !=3D 0; len -=3D TARGET_PAGE_SIZE, addr +=3D TARGET_PAGE_SIZE) { - PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, 1); + PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, true); =20 /* If the write protection bit is set, then we invalidate the code inside. */ --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661211285; cv=none; d=zohomail.com; s=zohoarc; b=BKxwkqk+U8fDHwx4iuPAMz/onVxDxlgA7Sb8/EdhlBFrK66/g5IuokC6hHT0npi0uU9e1xDdh0GJyhGnD2sRDQJBjP8K0NsGZaar215uChpR6E8vIqC4+MAYwAqP8AXpZ87G0on0cIfSddnQ0uKeKLXxGSBCK5hEl1+BGJDM3Lc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661211285; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Fp921J5xyOMPkA1GL+gCt3XwJG9dpPCMYFOeFVTD1t4=; b=Ac5gynICciDYOZ+Bq9uiR62fQJCz/AHfUO396ED0tJGunOBy75Jevd/ki2dqOedMEvJ175phSw/lQK0PdOzECtk1e31M3w2GDM/bS/gihi60T6CrwfduTuzBvK5dfS/M4quXhPniy+lyIfFrmwzAwoIPsEjCVSpw9rUioN5Ts4Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661211285323218.41863118774688; Mon, 22 Aug 2022 16:34:45 -0700 (PDT) Received: from localhost ([::1]:52538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGwO-0005TL-4n for importer@patchew.org; Mon, 22 Aug 2022 19:34:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlp-0005d2-MM for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:50 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:40876) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGlk-0005az-GG for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:49 -0400 Received: by mail-pg1-x52f.google.com with SMTP id w13so5668762pgq.7 for ; Mon, 22 Aug 2022 16:23:44 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Fp921J5xyOMPkA1GL+gCt3XwJG9dpPCMYFOeFVTD1t4=; b=kzbsvpwZVGZmbFjryS0qfFuc75yvYfslMVvlyNjHLq+xhKK958dBn9VJpfP+H6vBSG /UZBDeloVWoGtsPzPKMIGFnAquFbE9QMNak6DgcQfWrBjIbemCdse5suEMe4BrkCx46d WiuiOdDctTqVtgvgN+d4+ufTqRb6EHuLxhKKGIxZeTuF5swzA4v9OK5W8Xh3MXkvBDt1 TJg2TXrsT37Pvxdr0/nIq+eavo+CXHnuvUaEZj2c2vRqkEmE2gtVf0D7oYXK1PGX9yro ND8gO5juCgdh/BkuAkiD9K6SAFNO+Lhwlr3n2ASm8sS4qqql/LxfaMrNhFL38aemwKY9 Zz+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Fp921J5xyOMPkA1GL+gCt3XwJG9dpPCMYFOeFVTD1t4=; b=g9AquZvdrsurMAJeBcGT3iWjsGTstYZtt/qVc6zcM2w7Es+2pkNmi5PbAJpHJtz94S VxTjp7KtiY1cABFlep1i5UkKChFSjlPu8uuuc/a7m2N/6HQeAWBri0/4QGFXlUU9CEu4 e+kUWDXagfjX88JE4cr3vwfOcx93hdXTo2CuD85VewS2teFL7TxwPrmNysPOLFr3FFi0 cuHen6mJ3hY8XpNT8mR3ZXVz5KVDFcQld55ep2Ip0KOmEl5v37Nkh2HmqC8lj94hWfgY 6BCznfsDK4vp1XsyeEu98Sk6EB0exOq3PXNtIoHjh9cw7VW13jaIfyv2TMcbe32WA9fR lEcQ== X-Gm-Message-State: ACgBeo3v0eI6OhHQYHjg26rMjw7ksjmxitAQnOE01Ql2bdj7P1vQAfb4 6gpFXJWGoGk5QTSSZCFyzSDMS/IigBdkDw== X-Google-Smtp-Source: AA6agR5Hs58FEU96jOlQVVfDwHrLairksx4hTXLmM6BS3mvyI30cx8FDp/HBbyQntFWe4W4ZuVn2Dg== X-Received: by 2002:a63:83c1:0:b0:42a:d322:584f with SMTP id h184-20020a6383c1000000b0042ad322584fmr2800681pge.418.1661210623146; Mon, 22 Aug 2022 16:23:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 03/17] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Date: Mon, 22 Aug 2022 16:23:24 -0700 Message-Id: <20220822232338.1727934-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211286531100001 Content-Type: text/plain; charset="utf-8" Use the pc coming from db->pc_first rather than the TB. Use the cached host_addr rather than re-computing for the first page. We still need a separate lookup for the second page because it won't be computed for DisasContextBase until the translator actually performs a read from the page. Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 7 ++++--- accel/tcg/plugin-gen.c | 23 ++++++++++++----------- accel/tcg/translator.c | 2 +- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index f92f169739..5004728c61 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -19,7 +19,8 @@ struct DisasContextBase; =20 #ifdef CONFIG_PLUGIN =20 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool s= upress); +bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, + bool supress); void plugin_gen_tb_end(CPUState *cpu); void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *d= b); void plugin_gen_insn_end(void); @@ -48,8 +49,8 @@ static inline void plugin_insn_append(abi_ptr pc, const v= oid *from, size_t size) =20 #else /* !CONFIG_PLUGIN */ =20 -static inline -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool s= upress) +static inline bool +plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool= sup) { return false; } diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 8377c15383..0f080386af 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -852,7 +852,8 @@ static void plugin_gen_inject(const struct qemu_plugin_= tb *plugin_tb) pr_ops(); } =20 -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool m= em_only) +bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db, + bool mem_only) { bool ret =3D false; =20 @@ -870,9 +871,9 @@ bool plugin_gen_tb_start(CPUState *cpu, const Translati= onBlock *tb, bool mem_onl =20 ret =3D true; =20 - ptb->vaddr =3D tb->pc; + ptb->vaddr =3D db->pc_first; ptb->vaddr2 =3D -1; - get_page_addr_code_hostp(cpu->env_ptr, tb->pc, true, &ptb->haddr1); + ptb->haddr1 =3D db->host_addr[0]; ptb->haddr2 =3D NULL; ptb->mem_only =3D mem_only; =20 @@ -898,16 +899,16 @@ void plugin_gen_insn_start(CPUState *cpu, const Disas= ContextBase *db) * Note that we skip this when haddr1 =3D=3D NULL, e.g. when we're * fetching instructions from a region not backed by RAM. */ - if (likely(ptb->haddr1 !=3D NULL && ptb->vaddr2 =3D=3D -1) && - unlikely((db->pc_next & TARGET_PAGE_MASK) !=3D - (db->pc_first & TARGET_PAGE_MASK))) { - get_page_addr_code_hostp(cpu->env_ptr, db->pc_next, - true, &ptb->haddr2); - ptb->vaddr2 =3D db->pc_next; - } - if (likely(ptb->vaddr2 =3D=3D -1)) { + if (ptb->haddr1 =3D=3D NULL) { + pinsn->haddr =3D NULL; + } else if (is_same_page(db, db->pc_next)) { pinsn->haddr =3D ptb->haddr1 + pinsn->vaddr - ptb->vaddr; } else { + if (ptb->vaddr2 =3D=3D -1) { + ptb->vaddr2 =3D TARGET_PAGE_ALIGN(db->pc_first); + get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, + true, &ptb->haddr2); + } pinsn->haddr =3D ptb->haddr2 + pinsn->vaddr - ptb->vaddr2; } } diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index c8e9523e52..db924601ea 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -75,7 +75,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,= int max_insns, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - plugin_enabled =3D plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); + plugin_enabled =3D plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY); =20 while (true) { db->num_insns++; --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=nnTf8vYQrhFGbCh9F71+TS9pu/cqcKGq2pxwJ/zBizo=; b=Erp2M4pPEYOXS4FqQvkUXnl5DU+KPOQdEbYIv7v0vnBGl3vzwcB9VBkz1jTjRdbMwA ByhUYUVIOlDO8fEbVkxme574B0iH5pXbB8YWTJ3v2ik7upqhFWJjcNtPAjmaUeMBpu3s 8yT/mUrQg8yXkKRQNfxFefVSCTfkoIwyqHblY50Pn7KO1oex73Z+su9lXYHcjAb80HYo V4+uF8NUyg7VGqiVPs2zBtPdFZ4V0Wa/mF0bsX/PcCROHX3ACpnLqtT7sHpdEVNNTpdU GQM3BH52x6sjh6ci1HxbbCpELqTQedXjNjZqYlzzibIHZHCOdG8Grm/4sDjQpD2y+l/A 7mPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=nnTf8vYQrhFGbCh9F71+TS9pu/cqcKGq2pxwJ/zBizo=; b=y1l8xTWA1OCN8N6B3TEHXmpiiaBuYnN3e+G/Z/WSPJ3VK58SaNPZeD5eEHf926eJWO YPThwyiv2W3Wnn4fcJK5NxC1dtlglpfIzgLIpEnr0ZgAu0LLtSxk8M5StHJ+HrM8JTx3 mmtpKL+wmjPb8MXxVvDXJEXBG9qAdMt0st8jAlrsrWKo1uCO5x7ja2/W23/W0li4PZmc 3gLORvOF0QKTfGg3/lewU2WFZZLVzBbhNh3aeHT0D788x8FVTa8z3LMv4biAZplH7Hh8 YEyybf92g8mGcLG6CqdYCcrdFlqA7WAryBbrneLO//h7X68YufJiZwUMFjj+wwJ/xREs 6mFw== X-Gm-Message-State: ACgBeo34jm3U4FvM1K3JT0fdyDEVaCCQ+19CMnQVAHO03wC5SLMTsstN S/n5xEb2YitBwI2DKNg4ncO82NSzmRGU9A== X-Google-Smtp-Source: AA6agR75c/YfBb33RfyLX7tGZFuwEHln4WWnxlCdQBbxjr5Q1YWJv0C/hC+Of59gwxJtxhpBfyA4Pg== X-Received: by 2002:a65:6854:0:b0:41c:feab:e17c with SMTP id q20-20020a656854000000b0041cfeabe17cmr18878843pgt.256.1661210624252; Mon, 22 Aug 2022 16:23:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 04/17] accel/tcg: Do not align tb->page_addr[0] Date: Mon, 22 Aug 2022 16:23:25 -0700 Message-Id: <20220822232338.1727934-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210936278100001 Content-Type: text/plain; charset="utf-8" Let tb->page_addr[0] contain the offset within the page of the start of the translation block. We need to recover this value anyway at various points, and it is easier to discard the page offset when it's not needed, which happens naturally via the existing find_page shift. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 16 ++++++++-------- accel/tcg/cputlb.c | 3 ++- accel/tcg/translate-all.c | 9 +++++---- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7b8977a0a4..b1fd962718 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -174,7 +174,7 @@ struct tb_desc { target_ulong pc; target_ulong cs_base; CPUArchState *env; - tb_page_addr_t phys_page1; + tb_page_addr_t page_addr0; uint32_t flags; uint32_t cflags; uint32_t trace_vcpu_dstate; @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const struct tb_desc *desc =3D d; =20 if (tb->pc =3D=3D desc->pc && - tb->page_addr[0] =3D=3D desc->phys_page1 && + tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && @@ -195,12 +195,12 @@ static bool tb_lookup_cmp(const void *p, const void *= d) if (tb->page_addr[1] =3D=3D -1) { return true; } else { - tb_page_addr_t phys_page2; - target_ulong virt_page2; + tb_page_addr_t phys_page1; + target_ulong virt_page1; =20 - virt_page2 =3D (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZ= E; - phys_page2 =3D get_page_addr_code(desc->env, virt_page2); - if (tb->page_addr[1] =3D=3D phys_page2) { + virt_page1 =3D TARGET_PAGE_ALIGN(desc->pc); + phys_page1 =3D get_page_addr_code(desc->env, virt_page1); + if (tb->page_addr[1] =3D=3D phys_page1) { return true; } } @@ -226,7 +226,7 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, if (phys_pc =3D=3D -1) { return NULL; } - desc.phys_page1 =3D phys_pc & TARGET_PAGE_MASK; + desc.page_addr0 =3D phys_pc; h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ae7b40dd51..8b81b07b79 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -951,7 +951,8 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUS= tate *src_cpu, can be detected */ void tlb_protect_code(ram_addr_t ram_addr) { - cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE, + cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE, DIRTY_MEMORY_CODE); } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a8f1c34c4e..20f00f4335 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1167,7 +1167,7 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) qemu_spin_unlock(&tb->jmp_lock); =20 /* remove the TB from the hash list */ - phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + phys_pc =3D tb->page_addr[0]; h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { @@ -1291,7 +1291,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, * we can only insert TBs that are fully initialized. */ page_lock_pair(&p, phys_pc, &p2, phys_page2, true); - tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); + tb_page_add(p, tb, 0, phys_pc); if (p2) { tb_page_add(p2, tb, 1, phys_page2); } else { @@ -1644,11 +1644,12 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, if (n =3D=3D 0) { /* NOTE: tb_end may be after the end of the page, but it is not a problem */ - tb_start =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + tb_start =3D tb->page_addr[0]; tb_end =3D tb_start + tb->size; } else { tb_start =3D tb->page_addr[1]; - tb_end =3D tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK= ); + tb_end =3D tb_start + ((tb->page_addr[0] + tb->size) + & ~TARGET_PAGE_MASK); } if (!(tb_end <=3D start || tb_start >=3D end)) { #ifdef TARGET_HAS_PRECISE_SMC --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661211620; cv=none; d=zohomail.com; s=zohoarc; b=bQAuwskMemd3z5yYbFfytdTqoebEA+AyRHP0l6eP/o86xcMFfmyOmwxjfD+NgX4RN4i1d6oaO8loPTmTdEleeMP8aryRAP4W3OxjmJZk+UY7GHf/+bD1pt7EqY/5p2XXHRPSzlxaK4Xq2M50e5mM6C/L+GNxNr1K65E8PoUe+6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=XGYmwpgiZPY1AsTDknzkrjEzLYeuV4sGoEw7odttBvA=; b=adtutzQcMuVneKhA8FVpCHu1q4sKiS678TT+udXfA2GxQt/gEkLYfo/eFBmoTWvGhR 78m3hCCEBqOFVyle1P7fwfic+N+zUySTl+clA65+sRKCqx2WLKuCaxLlAHFXbQkSOaLI LnHmaE7uGtZbkJo7nPXiZEo1vqOlgJfSCyEhvXYCHHm7tzU/tX4/oGUYVJvynH8VpZMk L1AQ/NeYSzFns2J/5FZ286c/WTYZVE+ucMY+ocG56F0A0V8lzt6k4G1/uQE4t+oGBRZq kPZDJyvo1ytrTe2IAgSDPDzyVCzt89p3CV3PWAGVSNMFsfSB2mwRGZS29ECa4D2YpboP DHZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=XGYmwpgiZPY1AsTDknzkrjEzLYeuV4sGoEw7odttBvA=; b=nsf/YTiSOiwtbAe2y/37e6h5ldQEWDmLlwxmcFz1mk1t/NOV8bhkxaUDlhXo0QgKpL sgxukh49IxKtXmeVuiQt5RAzJzudhrs9iMwjMKIeAh+kgXYB1D1JPy/Qe1LqVXt3Y5So 7BnAWnJQUjU8sxaH60VS2HbMC9Z7equi1GLblwN+EErjzd4azxy/ajAUPvxeR8llttzI lq9HO4tK++TJ6W+18PBW5wbPay0E8VwKzjqtukFoikUIATUVKhTcTG4dkbKfo1BBybZy 2PGZw7EGci11rl8/mL/p4/39U/uK405r6KNC7Rw0VbJ/4yPrXdBgKyr2SyPkJaSaXFBX 8q7Q== X-Gm-Message-State: ACgBeo22R+hcBJJuZarelzA2GnlGMDg5sQU8jLBqhPZbA/HHMuRNL/1y 8TI60LZIB3+EjqZ8dPEQIcZsnnYIwqzxQw== X-Google-Smtp-Source: AA6agR7VN01CR5t9ZvTFC9Ua7BhRm80j4CWWDsk6SQ3QOZV3bhKPn7bEdjq61/mmRaFlMXy0JrokkA== X-Received: by 2002:a65:5504:0:b0:42a:352d:c79c with SMTP id f4-20020a655504000000b0042a352dc79cmr16561567pgr.58.1661210625251; Mon, 22 Aug 2022 16:23:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 05/17] include/hw/core: Create struct CPUJumpCache Date: Mon, 22 Aug 2022 16:23:26 -0700 Message-Id: <20220822232338.1727934-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211622214100001 Content-Type: text/plain; charset="utf-8" Wrap the bare TranslationBlock pointer into a structure. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 8 ++++++-- accel/tcg/cpu-exec.c | 9 ++++++--- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 4 ++-- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..8edef14199 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -233,6 +233,10 @@ struct hvf_vcpu_state; #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) =20 +typedef struct { + TranslationBlock *tb; +} CPUJumpCache; + /* work queue */ =20 /* The union type allows passing of 64 bit target pointers on 32 bit @@ -362,7 +366,7 @@ struct CPUState { IcountDecr *icount_decr_ptr; =20 /* Accessed in parallel; all accesses must be atomic */ - TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; + CPUJumpCache tb_jmp_cache[TB_JMP_CACHE_SIZE]; =20 struct GDBRegisterState *gdb_regs; int gdb_num_regs; @@ -453,7 +457,7 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) unsigned int i; =20 for (i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i], NULL); + qatomic_set(&cpu->tb_jmp_cache[i].tb, NULL); } } =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b1fd962718..3f8e4bbbc8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -243,7 +243,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); + tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); =20 if (likely(tb && tb->pc =3D=3D pc && @@ -257,7 +257,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , target_ulong pc, if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash], tb); + qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); return tb; } =20 @@ -978,6 +978,8 @@ int cpu_exec(CPUState *cpu) =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { + uint32_t h; + mmap_lock(); tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); mmap_unlock(); @@ -985,7 +987,8 @@ int cpu_exec(CPUState *cpu) * We add the TB in the virtual pc hash table * for the fast lookup */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]= , tb); + h =3D tb_jmp_cache_hash_func(pc); + qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8b81b07b79..a8afe1ab9f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -103,7 +103,7 @@ static void tb_jmp_cache_clear_page(CPUState *cpu, targ= et_ulong page_addr) unsigned int i, i0 =3D tb_jmp_cache_hash_page(page_addr); =20 for (i =3D 0; i < TB_JMP_PAGE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); + qatomic_set(&cpu->tb_jmp_cache[i0 + i].tb, NULL); } } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 20f00f4335..c2745f14a6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1187,8 +1187,8 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) /* remove the TB from the hash list */ h =3D tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h]) =3D=3D tb) { - qatomic_set(&cpu->tb_jmp_cache[h], NULL); + if (qatomic_read(&cpu->tb_jmp_cache[h].tb) =3D=3D tb) { + qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); } } =20 --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661210820; cv=none; d=zohomail.com; s=zohoarc; b=lPXBgHszf893idGApm1pOeXQVBLIA2K458/uBAoqd/dDKTzHYWEyHa5J8d78M3cJLsypV0s7qif38Jp7Mo4aZGG+GHaDhk8tY58sO4mkLnxj/DzxFGhxVh3nEKmDOERawJwCGZ/LhpialSpKKxt2RiOqnaqFKl0QLB6EK/ZNCT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661210820; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=AjCZW8xJUb6I9643NCyfNU4X/BcXHb1WVao5dY2EkTM=; b=NeYEl/BZPxitThJ/V/A04QWeB/F6JR3iWjHGZcYQAHEmIAdBI+BRI65XnR0IRVPE/W wJSH+7dkamnmy9SNJn3CiCRyhyJUNqNgy39Jul7xIokJ/tJ16iNlX215g9spCJogMMYT b769fTGVjJmZDXo/NJdvTyXmrUAbZSu/Dhvk7jjh9eVmg3yr0zywhT0AZcvzciGECKIF 026PvEtomWhweHPjkO0XWOllX0V6/NOQKUyHzt5D1mNooserebnZyL9SbCWTD8bd/WX2 RHnhKj+I54sTrDRWeGozlVQKxQdKUgHw1zd5oyE+Uo0m7y2fgqgsrT4O+GDRFzsKG6bb xwNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=AjCZW8xJUb6I9643NCyfNU4X/BcXHb1WVao5dY2EkTM=; b=3kN2MsxVWj2PFHjrs1PnvHtHk8HkfTT8bw0NSN2JnQCEuYt2FZy87p1Mqhyz+/NtWy UnveLBlPLyS3KVmQFtZoRub6lw6HK0tq/6M9WSFtBqImlN8hvjO68Az91fnLI/YNkMBq 8gOmfBKJw8wCLwP9lZFZy3Wjt0X+Cmul4n2Zd202zkb6KSenOi4/dne4a120o4MoIqgM Ql8/mzy7gM5VQDXTbEjk/FZDtMcfZrgyW882yYnRtLvu1vnPvqifpcHLSXw3pHu3dWF1 HBRH+kyYjOXkbGd5XbXTVsQxFBLONDfEvgr/kin51vn+BK0yil8uzkwFCZFyjyHCBCMN z5Rg== X-Gm-Message-State: ACgBeo33TX8T5jtgMG1/x4MatzW/8Z6z8tp9yx9RVWCuj53CAkFaMhhw QA7+DI9zdMfiaEQcGAx2SyVUDfAWoiQ6ig== X-Google-Smtp-Source: AA6agR7XIS5YJjtBuM+w4QtOflC8y6ePH7zbjykoBNv+bk/l0OjrDGP+JgI56bkbWta65mByA1Qcxg== X-Received: by 2002:a05:6a00:1706:b0:52f:6f75:991b with SMTP id h6-20020a056a00170600b0052f6f75991bmr22666237pfc.34.1661210626508; Mon, 22 Aug 2022 16:23:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 06/17] accel/tcg: Introduce tb_pc and tb_pc_log Date: Mon, 22 Aug 2022 16:23:27 -0700 Message-Id: <20220822232338.1727934-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210821279100001 Content-Type: text/plain; charset="utf-8" The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++++++++++ accel/tcg/cpu-exec.c | 20 ++++++++--------- accel/tcg/translate-all.c | 29 +++++++++++++------------ target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- tcg/tcg.c | 6 ++--- 19 files changed, 59 insertions(+), 46 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 4ad166966b..cec3ef1666 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -533,6 +533,18 @@ struct TranslationBlock { uintptr_t jmp_dest[2]; }; =20 +/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ +static inline target_ulong tb_pc(const TranslationBlock *tb) +{ + return tb->pc; +} + +/* Similarly, but for logs. */ +static inline target_ulong tb_pc_log(const TranslationBlock *tb) +{ + return tb->pc; +} + /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3f8e4bbbc8..f146960b7b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -185,7 +185,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb->pc =3D=3D desc->pc && + if (tb_pc(tb) =3D=3D desc->pc && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -413,7 +413,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) TranslationBlock *last_tb; const void *tb_ptr =3D itb->tc.ptr; =20 - log_cpu_exec(itb->pc, cpu, itb); + log_cpu_exec(tb_pc_log(itb), cpu, itb); =20 qemu_thread_jit_execute(); ret =3D tcg_qemu_tb_exec(env, tb_ptr); @@ -437,16 +437,16 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int= *tb_exit) * of the start of the TB. */ CPUClass *cc =3D CPU_GET_CLASS(cpu); - qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb_pc_log(last_tb), "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc.ptr, last_tb->pc, - lookup_symbol(last_tb->pc)); + last_tb->tc.ptr, tb_pc_log(last_tb), + lookup_symbol(tb_pc_log(last_tb))); if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); - cc->set_pc(cpu, last_tb->pc); + cc->set_pc(cpu, tb_pc(last_tb)); } } =20 @@ -588,11 +588,11 @@ static inline void tb_add_jump(TranslationBlock *tb, = int n, =20 qemu_spin_unlock(&tb_next->jmp_lock); =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb_pc_log(tb), "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc.ptr, tb->pc, n, - tb_next->tc.ptr, tb_next->pc); + tb->tc.ptr, tb_pc_log(tb), n, + tb_next->tc.ptr, tb_pc_log(tb_next)); return; =20 out_unlock_next: @@ -842,7 +842,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, { int32_t insns_left; =20 - trace_exec_tb(tb, tb->pc); + trace_exec_tb(tb, tb_pc_log(tb)); tb =3D cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit !=3D TB_EXIT_REQUESTED) { *last_tb =3D tb; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c2745f14a6..1248ee3433 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -298,7 +298,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb->pc : 0); + prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -326,7 +326,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; + target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -884,7 +884,7 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return a->pc =3D=3D b->pc && + return tb_pc(a) =3D=3D tb_pc(b) && a->cs_base =3D=3D b->cs_base && a->flags =3D=3D b->flags && (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && @@ -1012,9 +1012,10 @@ static void do_tb_invalidate_check(void *p, uint32_t= hash, void *userp) TranslationBlock *tb =3D p; target_ulong addr =3D *(target_ulong *)userp; =20 - if (!(addr + TARGET_PAGE_SIZE <=3D tb->pc || addr >=3D tb->pc + tb->si= ze)) { + if (!(addr + TARGET_PAGE_SIZE <=3D tb_pc(tb) || + addr >=3D tb_pc(tb) + tb->size)) { printf("ERROR invalidate: address=3D" TARGET_FMT_lx - " PC=3D%08lx size=3D%04x\n", addr, (long)tb->pc, tb->size); + " PC=3D%08lx size=3D%04x\n", addr, (long)tb_pc(tb), tb->siz= e); } } =20 @@ -1033,11 +1034,11 @@ static void do_tb_page_check(void *p, uint32_t hash= , void *userp) TranslationBlock *tb =3D p; int flags1, flags2; =20 - flags1 =3D page_get_flags(tb->pc); - flags2 =3D page_get_flags(tb->pc + tb->size - 1); + flags1 =3D page_get_flags(tb_pc(tb)); + flags2 =3D page_get_flags(tb_pc(tb) + tb->size - 1); if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { printf("ERROR page flags: PC=3D%08lx size=3D%04x f1=3D%x f2=3D%x\n= ", - (long)tb->pc, tb->size, flags1, flags2); + (long)tb_pc(tb), tb->size, flags1, flags2); } } =20 @@ -1168,7 +1169,7 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, + h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; @@ -1299,7 +1300,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, + h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 @@ -1399,7 +1400,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cpu =3D NULL; max_insns =3D tb->icount; =20 - trace_translate_block(tb, tb->pc, tb->tc.ptr); + trace_translate_block(tb, tb_pc_log(tb), tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1476,7 +1477,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(tb->pc)) { + qemu_log_in_addr_range(tb_pc_log(tb))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { int code_size, data_size; @@ -1916,9 +1917,9 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) */ cpu->cflags_next_tb =3D curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO |= n; =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb_pc_log(tb), "cpu_io_recompile: rewound execution of TB to " - TARGET_FMT_lx "\n", tb->pc); + TARGET_FMT_lx "\n", tb_pc_log(tb)); =20 cpu_loop_exit_noexc(cpu); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7ec3281da9..047bf3f4ab 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -72,9 +72,9 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, * never possible for an AArch64 TB to chain to an AArch32 TB. */ if (is_a64(env)) { - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } else { - env->regs[15] =3D tb->pc; + env->regs[15] =3D tb_pc(tb); } } #endif /* CONFIG_TCG */ diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 05b992ff73..6ebef62b4c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -47,7 +47,7 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs, AVRCPU *cpu =3D AVR_CPU(cs); CPUAVRState *env =3D &cpu->env; =20 - env->pc_w =3D tb->pc / 2; /* internally PC points to words */ + env->pc_w =3D tb_pc(tb) / 2; /* internally PC points to words */ } =20 static void avr_cpu_reset(DeviceState *ds) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fa9bd702d6..6289a6e64a 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -256,7 +256,7 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *c= s, { HexagonCPU *cpu =3D HEXAGON_CPU(cs); CPUHexagonState *env =3D &cpu->env; - env->gpr[HEX_REG_PC] =3D tb->pc; + env->gpr[HEX_REG_PC] =3D tb_pc(tb); } =20 static bool hexagon_cpu_has_work(CPUState *cs) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a6f52caf14..fc9d43f620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -42,7 +42,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, HPPACPU *cpu =3D HPPA_CPU(cs); =20 #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f =3D tb->pc; + cpu->env.iaoq_f =3D tb_pc(tb); cpu->env.iaoq_b =3D tb->cs_base; #else /* Recover the IAOQ values from the GVA + PRIV. */ @@ -52,7 +52,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, int32_t diff =3D cs_base; =20 cpu->env.iasq_f =3D iasq_f; - cpu->env.iaoq_f =3D (tb->pc & ~iasq_f) + priv; + cpu->env.iaoq_f =3D (tb_pc(tb) & ~iasq_f) + priv; if (diff) { cpu->env.iaoq_b =3D cpu->env.iaoq_f + diff; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6fdfdf9598..76989a5a9d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -51,7 +51,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, { X86CPU *cpu =3D X86_CPU(cs); =20 - cpu->env.eip =3D tb->pc - tb->cs_base; + cpu->env.eip =3D tb_pc(tb) - tb->cs_base; } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 941e2772bc..262ddfb51c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -309,7 +309,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState = *cs, LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); CPULoongArchState *env =3D &cpu->env; =20 - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } #endif /* CONFIG_TCG */ =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aed200dcff..5a642db285 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -89,7 +89,7 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.iflags =3D tb->flags & IFLAGS_TB_MASK; } =20 diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 2bd77a61de..96e61170e6 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -82,7 +82,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const Tra= nslationBlock *tb) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; =20 - env->active_tc.PC =3D tb->pc; + env->active_tc.PC =3D tb_pc(tb); env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/syse= mu/special_helper.c index f4f8fe8afc..3c5f35c759 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -94,7 +94,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const = TranslationBlock *tb) CPUMIPSState *env =3D &cpu->env; =20 if ((env->hflags & MIPS_HFLAG_BMASK) !=3D 0 - && env->active_tc.PC !=3D tb->pc) { + && env->active_tc.PC !=3D tb_pc(tb)) { env->active_tc.PC -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); env->hflags &=3D ~MIPS_HFLAG_BMASK; return true; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 41d1b2a24a..10ea952ff2 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -36,7 +36,7 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); } =20 =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac6f82ebd0..8cb9428a80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -397,9 +397,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); =20 if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)tb->pc; + env->pc =3D (int32_t)tb_pc(tb); } else { - env->pc =3D tb->pc; + env->pc =3D tb_pc(tb); } } =20 diff --git a/target/rx/cpu.c b/target/rx/cpu.c index fb30080ac4..f1e0008e04 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -37,7 +37,7 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, { RXCPU *cpu =3D RX_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); } =20 static bool rx_cpu_has_work(CPUState *cs) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 06b2691dc4..6948c8fa33 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -39,7 +39,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, { SuperHCPU *cpu =3D SUPERH_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.flags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; } =20 @@ -51,7 +51,7 @@ static bool superh_io_recompile_replay_branch(CPUState *c= s, CPUSH4State *env =3D &cpu->env; =20 if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) !=3D 0 - && env->pc !=3D tb->pc) { + && env->pc !=3D tb_pc(tb)) { env->pc -=3D 2; env->flags &=3D ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); return true; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 55268ed2a1..0471c2fe5a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -698,7 +698,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, { SPARCCPU *cpu =3D SPARC_CPU(cs); =20 - cpu->env.pc =3D tb->pc; + cpu->env.pc =3D tb_pc(tb); cpu->env.npc =3D tb->cs_base; } =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f0..35f3347add 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -47,7 +47,7 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, TriCoreCPU *cpu =3D TRICORE_CPU(cs); CPUTriCoreState *env =3D &cpu->env; =20 - env->PC =3D tb->pc; + env->PC =3D tb_pc(tb); } =20 static void tricore_cpu_reset(DeviceState *dev) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0f9cfe96f2..11bdb96dd1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4218,7 +4218,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(tb_pc_log(tb)))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP:\n"); @@ -4265,7 +4265,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (s->nb_indirects > 0) { #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(tb_pc_log(tb)))) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP before indirect lowering:\n"); @@ -4288,7 +4288,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(tb_pc_log(tb)))) { FILE *logfile =3D qemu_log_trylock(); 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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=NqtfRvm5YPgpHrNyEYV9MYytRntfUKxLXS0e+JpD/BY=; b=drZrcAuALfo64GnOJ12NraER3GGoBIt07S7d6RCGQkoeLG7jTuKloVstpQbnY56UBB iMUtaRU0UecAWoJi6IpPzfhPEjTUCbbTwWqXziyQ6PBgb2q5PX3Kjc6M8PLto7XS5HSL uw2ri83fhPXhYVEKWV7sba6CSE0WOpXc9fVysXli+1eIo4J7WdqozkjxyZ+mn0Vlq1zF +QhadFNp6NoftHpKG26sBAEd4lJT1IMN5p0l0EUddedWjKDS42aB9u2CMYZ6hQbl6z5w /fz+IR1+yHvRU45oAty47LAdJLIlrVztxBslox/Dx6P0PG69ykLVbkBinWxaHfZdQiQ+ gZjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=NqtfRvm5YPgpHrNyEYV9MYytRntfUKxLXS0e+JpD/BY=; b=PskM+vrjeAvMYcv4nAieeIXqIdA4NyfRxTOd3FyrSBDV7t0Z5aZbkHTahy3/eJgqVr Q9zcEgTmo48zW8XV8yQPrUHQ9jWAamFbm5V2GpuLm+InO9TfQvaTBIAzclyIz6ES5ahs m5vMZ2q1xW5wYGA0xooDbIg/7MxmPk53DL4yVhQf+bTpVe4PpJVx7i98bw3SHL/PglZA FbdMcAiWR9WOR988n4106RUg3ftxV4YR6i1ZaGXTKyOi7wrmqu/z0BGI2++lYK/l2ecz 6Fo+QjVcmUZ7350nJFi2CtlvcKGbtdUaiUFcD47xot/CpeH2tKExXfZ1PmBPyGkH+Sab Wjuw== X-Gm-Message-State: ACgBeo216VeVKh+zGGFm5agpAldMJhSVk6BiaaHf33aNwQbqw2djwhBL StNY2rKh/jSQQjlx4iG0JCLma70CtB0sLw== X-Google-Smtp-Source: AA6agR7KKer/1qNAxMxAZn1UCAYzpS0AFO72gS2jmJWkC2e/Vz9z79quHOuW1Ai4XyR9+2aqf+Iu8g== X-Received: by 2002:a63:4c50:0:b0:429:983d:22f1 with SMTP id m16-20020a634c50000000b00429983d22f1mr18737726pgl.213.1661210627861; Mon, 22 Aug 2022 16:23:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 07/17] accel/tcg: Introduce TARGET_TB_PCREL Date: Mon, 22 Aug 2022 16:23:28 -0700 Message-Id: <20220822232338.1727934-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210952353100001 Content-Type: text/plain; charset="utf-8" Prepare for targets to be able to produce TBs that can run in more than one virtual context. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ include/exec/exec-all.h | 41 ++++++++++++++++++++++++++--- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 55 ++++++++++++++++++++++++++++++--------- accel/tcg/translate-all.c | 48 ++++++++++++++++++++++------------ 5 files changed, 115 insertions(+), 33 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..87e2bc4e59 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -54,6 +54,9 @@ # error TARGET_PAGE_BITS must be defined in cpu-param.h # endif #endif +#ifndef TARGET_TB_PCREL +# define TARGET_TB_PCREL 0 +#endif =20 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cec3ef1666..b41835bb55 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -459,8 +459,32 @@ struct tb_tc { }; =20 struct TranslationBlock { - target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ - target_ulong cs_base; /* CS base for this block */ +#if !TARGET_TB_PCREL + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are + * written such that the TB is associated only with the physical + * page and may be run in any virtual address context. In this case, + * PC must always be taken from ENV in a target-specific manner. + * Unwind information is taken as byte offsets from the "current" + * value of the PC, as tracked by the translator. + */ + target_ulong pc; +#endif + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + target_ulong cs_base; + uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ =20 @@ -536,13 +560,24 @@ struct TranslationBlock { /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ static inline target_ulong tb_pc(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + qemu_build_not_reached(); +#else return tb->pc; +#endif } =20 -/* Similarly, but for logs. */ +/* + * Similarly, but for logs. In this case, when the virtual pc + * is not available, use the physical address. + */ static inline target_ulong tb_pc_log(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + return tb->page_addr[0]; +#else return tb->pc; +#endif } =20 /* Hide the qatomic_read to make code a little easier on the eyes */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8edef14199..7dcfccf6e2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -235,6 +235,7 @@ struct hvf_vcpu_state; =20 typedef struct { TranslationBlock *tb; + vaddr pc; } CPUJumpCache; =20 /* work queue */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f146960b7b..3fb7ce05f8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -185,7 +185,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb_pc(tb) =3D=3D desc->pc && + if ((TARGET_TB_PCREL || tb_pc(tb) =3D=3D desc->pc) && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -227,7 +227,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, return NULL; } desc.page_addr0 =3D phys_pc; - h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc), + flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } =20 @@ -243,21 +244,42 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); - - if (likely(tb && - tb->pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - tb_cflags(tb) =3D=3D cflags)) { - return tb; + if (TARGET_TB_PCREL) { + /* Use acquire to ensure current load of pc from tb_jmp_cache[]. */ + tb =3D qatomic_load_acquire(&cpu->tb_jmp_cache[hash].tb); + } else { + /* Use rcu_read to ensure current load of pc from *tb. */ + tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); } + if (likely(tb)) { + target_ulong jmp_pc; + + if (TARGET_TB_PCREL) { + jmp_pc =3D cpu->tb_jmp_cache[hash].pc; + } else { + jmp_pc =3D tb_pc(tb); + } + if (jmp_pc =3D=3D pc && + tb->cs_base =3D=3D cs_base && + tb->flags =3D=3D flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && + tb_cflags(tb) =3D=3D cflags) { + return tb; + } + } + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); + + if (TARGET_TB_PCREL) { + cpu->tb_jmp_cache[hash].pc =3D pc; + /* Use store_release on tb to ensure pc is current. */ + qatomic_store_release(&cpu->tb_jmp_cache[hash].tb, tb); + } else { + qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); + } return tb; } =20 @@ -445,6 +467,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { + assert(!TARGET_TB_PCREL); assert(cc->set_pc); cc->set_pc(cpu, tb_pc(last_tb)); } @@ -988,7 +1011,13 @@ int cpu_exec(CPUState *cpu) * for the fast lookup */ h =3D tb_jmp_cache_hash_func(pc); - qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); + if (TARGET_TB_PCREL) { + cpu->tb_jmp_cache[h].pc =3D pc; + /* Use store_release on tb to ensure pc is current. */ + qatomic_store_release(&cpu->tb_jmp_cache[h].tb, tb); + } else { + qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 1248ee3433..27435b97db 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -298,7 +298,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); + prev =3D (!TARGET_TB_PCREL && j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -326,7 +326,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; + target_ulong data[TARGET_INSN_START_WORDS]; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -342,6 +342,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tr= anslationBlock *tb, return -1; } =20 + memset(data, 0, sizeof(data)); + if (!TARGET_TB_PCREL) { + data[0] =3D tb_pc(tb); + } + /* Reconstruct the stored insn data while looking for the point at which the end of the insn exceeds the searched_pc. */ for (i =3D 0; i < num_insns; ++i) { @@ -884,13 +889,13 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return tb_pc(a) =3D=3D tb_pc(b) && - a->cs_base =3D=3D b->cs_base && - a->flags =3D=3D b->flags && - (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && - a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && - a->page_addr[0] =3D=3D b->page_addr[0] && - a->page_addr[1] =3D=3D b->page_addr[1]; + return ((TARGET_TB_PCREL || tb_pc(a) =3D=3D tb_pc(b)) && + a->cs_base =3D=3D b->cs_base && + a->flags =3D=3D b->flags && + (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALI= D) && + a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && + a->page_addr[0] =3D=3D b->page_addr[0] && + a->page_addr[1] =3D=3D b->page_addr[1]); } =20 void tb_htable_init(void) @@ -1169,8 +1174,8 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; } @@ -1186,10 +1191,17 @@ static void do_tb_phys_invalidate(TranslationBlock = *tb, bool rm_from_page_list) } =20 /* remove the TB from the hash list */ - h =3D tb_jmp_cache_hash_func(tb->pc); - CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h].tb) =3D=3D tb) { - qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); + if (TARGET_TB_PCREL) { + /* Any TB may be at any virtual address */ + CPU_FOREACH(cpu) { + cpu_tb_jmp_cache_clear(cpu); + } + } else { + h =3D tb_jmp_cache_hash_func(tb_pc(tb)); + CPU_FOREACH(cpu) { + if (qatomic_read(&cpu->tb_jmp_cache[h].tb) =3D=3D tb) { + qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); + } } } =20 @@ -1300,8 +1312,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 /* remove TB from the page(s) if we couldn't insert it */ @@ -1371,7 +1383,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D tcg_splitwx_to_rx(gen_code_buf); +#if !TARGET_TB_PCREL tb->pc =3D pc; +#endif tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661210800; cv=none; d=zohomail.com; s=zohoarc; b=hmrnf7C0SVugQ32wy+Hvgo+xxaAxC47b8im4yhUuZKY5CT9E6n7CAB6TqohoSS+1awdtsG3JZ/gvrmJqPrUG52856+5zEd05+WVyLh52q5zMvx57oky9+4yGm8gFO6zqULHqVAMHW2/dP6he1PZyYJLroRE3h5byNoICPcetfko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661210800; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tqkn/JG3p7hh15BhAIIM7TpuZb0gvOSNNm/i6FGCa5k=; b=S2M0RIJBSu0lFkT88bka+wgxodu80mNC6a02/VPXkUvkrEJjSwbyoEdZVPBPhqi5ViXXQDo2tb7ao7FytTEmcfA4Quz7GNzOcvT8uHV4mgSLCspxIpcEr4KkpQ4fWD18zeRNdqIV10E7jboDXJbf3KBjiw2S2dFraqENnhtyo1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661210800247373.88627310493644; Mon, 22 Aug 2022 16:26:40 -0700 (PDT) Received: from localhost ([::1]:58464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGoV-00007p-Sj for importer@patchew.org; Mon, 22 Aug 2022 19:26:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlu-0005fB-FV for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:54 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:41915) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGlq-0005cP-85 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:54 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 202so10747766pgc.8 for ; Mon, 22 Aug 2022 16:23:49 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210801106100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3fb7ce05f8..4dc0a9ec41 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -283,12 +283,11 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, return tb; } =20 -static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, - const TranslationBlock *tb) +static void log_cpu_exec1(CPUState *cpu, const TranslationBlock *tb) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) - && qemu_log_in_addr_range(pc)) { + target_ulong pc =3D tb_pc_log(tb); =20 + if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, "Trace %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx "/%08x/%08x] %s\n", @@ -315,6 +314,13 @@ static inline void log_cpu_exec(target_ulong pc, CPUSt= ate *cpu, } } =20 +static inline void log_cpu_exec(CPUState *cpu, const TranslationBlock *tb) +{ + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))) { + log_cpu_exec1(cpu, tb); + } +} + static bool check_for_breakpoints(CPUState *cpu, target_ulong pc, uint32_t *cflags) { @@ -412,7 +418,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) return tcg_code_gen_epilogue; } =20 - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(cpu, tb); =20 return tb->tc.ptr; } @@ -435,7 +441,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) TranslationBlock *last_tb; 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([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=qdoo/EFfZ9+xL61qXYRJd5BN7nP+QxbxeeGNggpMDL4=; b=tJAnrn5ZTXiXYB6yNHP6dyvDQbWcpH/vsECz03Ss4f1tFx86dkn5QD/DN7KcpVj86d HeBdAyFLwOPSAOyhA85stDhPVeJap5MLE4ZrurightZSCTCOZwNbuJAyLsDZugqGvs9S JSnTUWLoHDhvChgWMnhqYQxTcVIRQNMEOEkVcGS/KsIeWIIUIhMFxE8EiGfx/ANUlyFH QkJVirSAznGHzD2u5fxPSvVChHXjgWyQ+MKrHCDN/esfMN2UqHjhtMA99hhf1F2hXEhv zA1uBhzUoupSLC3NPj5SQDd0cEunnz92lI6X0lGEwrjzigBMrLpnryuIwI5theMOtkSI /eLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=qdoo/EFfZ9+xL61qXYRJd5BN7nP+QxbxeeGNggpMDL4=; b=2jEdf+SBVhziz60kb0s/sq1ceJLgvBUp6qdaESxPB7FTafY6xbVJclsq3D8P52Mhd/ xXWfapoksqdCYaf6uhGHe8g9WbkvbN+ElIVh76X7zkhHsg9HFlsoUiT5Yl/N550HoDau 6sxRRvYhx4VoHTjuuHciFAx68I5+rqT8/LOi7EknkaVFfIkx8H0TTRNHdIcY2a5fo+V6 yHls295aflMW10WWGStMPJS7/lr2rkwh8t42sjM3hINQCBsmfM+CRlCvOpBd0fXLDGg8 mXkLHUm5MWsgTC36edMgnXHv2oxilQHxLEnD4oXFOfffIYA0tLv4zHdVLTlbLJUkMMaA yeuQ== X-Gm-Message-State: ACgBeo1BNe2K69vQaDENSaDqtq315ktY/oSFLaAU+53UcRdOWa9fktNK 84FKFNnGBvsoq2oetI01T/Na54SZoHR33A== X-Google-Smtp-Source: AA6agR6aZ0HEn36Ws0ZRVRdPOUBSW9vmROYj4cOnhzyruPIhT+keZrR8p/TY41nTG/MDhIHlPMdO8Q== X-Received: by 2002:a63:f4d:0:b0:41c:5b90:f643 with SMTP id 13-20020a630f4d000000b0041c5b90f643mr19164370pgp.537.1661210629852; Mon, 22 Aug 2022 16:23:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 09/17] target/arm: Introduce curr_insn_len Date: Mon, 22 Aug 2022 16:23:30 -0700 Message-Id: <20220822232338.1727934-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211374925100001 Content-Type: text/plain; charset="utf-8" A simple helper to retrieve the length of the current insn. Signed-off-by: Richard Henderson --- target/arm/translate.h | 5 +++++ target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 5 ++--- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index af5d4a7086..90bf7c57fc 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -226,6 +226,11 @@ static inline void disas_set_insn_syndrome(DisasContex= t *s, uint32_t syn) s->insn_start =3D NULL; } =20 +static inline int curr_insn_len(DisasContext *s) +{ + return s->base.pc_next - s->pc_curr; +} + /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ /* CPU state was modified dynamically; exit to main loop for interrupts. */ diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index bd5ae27d09..94cc1e4b77 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -242,7 +242,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ig= nore_vfp_enabled) if (s->sme_trap_nonstreaming) { gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, - s->base.pc_next - s->pc_curr =3D=3D= 2)); + curr_insn_len(s) =3D=3D 2)); return false; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9474e4b44b..638a051281 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6660,7 +6660,7 @@ static ISSInfo make_issinfo(DisasContext *s, int rd, = bool p, bool w) /* ISS not valid if writeback */ if (p && !w) { ret =3D rd; - if (s->base.pc_next - s->pc_curr =3D=3D 2) { + if (curr_insn_len(s) =3D=3D 2) { ret |=3D ISSIs16Bit; } } else { @@ -9825,8 +9825,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(cpu_env, - tcg_constant_i32(dc->base.pc_next - dc->pc_curr= )); + gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc))); /* * The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661211120; cv=none; d=zohomail.com; s=zohoarc; b=eN4DypjYVcerkUrEDG/I1ZnsUfjPRTtUELI0WDVGopYokgQkLYwlKgPVCAgm9uIt7PsRHSyHevNSWBl/cZWv4qqXkgT8ebatxpvDFlSLypA60IcLpv3bgUZjiZ9d1BJG5hAmYzreLR10csMNTAr7ezlAvCzGPaF5AtXrrhPTT6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661211120; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8mcpoGyicxvO86RBsxLMjT2beQqB3D9uTqe6maslzKo=; b=Ogf2pO1XZ40m/q7fVr3HhJwhv0ToqL0q3Dp68C3znoiHapCTQr09eVFCp2gkyT1Ig/sCjSxdKpv4r5HSC4oYfWcqcd5V9fO2plhU6Bl2JcciqeyQVo//EGX7b5yTkBZ/ZA9ll/Hq94tlMrmAOdER7hvf5jlg4E1TKmsYh3hsTmY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661211120566589.3399687109659; Mon, 22 Aug 2022 16:32:00 -0700 (PDT) Received: from localhost ([::1]:38298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGtj-0003jk-DP for importer@patchew.org; Mon, 22 Aug 2022 19:31:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlx-0005ht-Vz for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:58 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:42854) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGls-0005dI-7S for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:56 -0400 Received: by mail-pl1-x630.google.com with SMTP id v23so6009265plo.9 for ; Mon, 22 Aug 2022 16:23:51 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=8mcpoGyicxvO86RBsxLMjT2beQqB3D9uTqe6maslzKo=; b=OJU+Ggx0BJawEPHqLVlm/fs4h6nJypZdAIlSfgKR3OCi0AzQ93LhVDaRfwHtMO6sWN fy1sXLZu+wV2QbqDzkA43BD1TzNUy2p0xwbOqkgdFam3NZXqUlDOuPaodgn4xshpH2Dt UReEl6dLFffYcL++T07UkdKpsn7M+7GAm/6rI0K7MOw/MB55jJU0BkcIU1U86BUa+RQM 94JEg9qSRbmSo9p5++lnICwokoF+iG5dkszy7W59Wi5MTV5+dDBOguWFKVRo4JB/TrqP ozZNnIX8wwpZJi68WLtkzZrMhJ8ZBvM7uNUpMjOJ/h36KOWnooG2j3SZS0RB5VBZhosn MPKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=8mcpoGyicxvO86RBsxLMjT2beQqB3D9uTqe6maslzKo=; b=BmO78VhuSJZ6pKP9kxiizKQs5LpeQW8DqIUD1YpK/0PvMV+1NeAihEMfQ0kxynnnFk 7XnIOiJJ0EZFoZ5nRCDeuXq2tmuzaSn0EAZqHhQYJngilyjEAvDahNUMk9Ex3pQP8jpF 9+4o3Hn7+BtFplSmy40cWEkb8vV7GwIjHfXsH07E6Q1cdTLFRHU9lr9uipXcOMmffPc3 OaUL9f4Yqa3HLaN/p656GkDqySzctE1733yiApcuHXrxSVmqCTRa6mgRV3DJsI5Iwf/R nZh93DlRA2Rl6VZlaNBFdirSpdfwfHfRO/Gl08/C8MUIriuijbqOtSl477YpCHWcekHa R5TQ== X-Gm-Message-State: ACgBeo266Rj6TAh94J4mnOLoZyo861BEsssc4HWsmFR1l1VvQIDuc3Z0 2SvecUF39tAL7zeAkXisX0wwAJx9vwuceA== X-Google-Smtp-Source: AA6agR5U8vUSAmYLhiBkgTCAFlD3zQBhoxKtbI8rrcCEjCxadqkQ/JCI0XYq0Wg8tKwXp7yyQ351+A== X-Received: by 2002:a17:902:ed92:b0:172:a334:acbb with SMTP id e18-20020a170902ed9200b00172a334acbbmr22171627plj.58.1661210630747; Mon, 22 Aug 2022 16:23:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 10/17] target/arm: Change gen_goto_tb to work on displacements Date: Mon, 22 Aug 2022 16:23:31 -0700 Message-Id: <20220822232338.1727934-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211121511100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------ target/arm/translate.c | 10 ++++++---- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 163df8c615..695ccd0723 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -378,8 +378,10 @@ static inline bool use_goto_tb(DisasContext *s, uint64= _t dest) return translator_use_goto_tb(&s->base, dest); } =20 -static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + uint64_t dest =3D s->pc_curr + diff; + if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); @@ -1362,7 +1364,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const = AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - uint64_t addr =3D s->pc_curr + sextract32(insn, 0, 26) * 4; + int diff =3D sextract32(insn, 0, 26) * 4; =20 if (insn & (1U << 31)) { /* BL Branch with link */ @@ -1371,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) =20 /* B Branch / BL Branch with link */ reset_btype(s); - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } =20 /* Compare and branch (immediate) @@ -1383,14 +1385,14 @@ static void disas_uncond_b_imm(DisasContext *s, uin= t32_t insn) static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { unsigned int sf, op, rt; - uint64_t addr; + int diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; =20 sf =3D extract32(insn, 31, 1); op =3D extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt =3D extract32(insn, 0, 5); - addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; + diff =3D sextract32(insn, 5, 19) * 4; =20 tcg_cmp =3D read_cpu_reg(s, rt, sf); label_match =3D gen_new_label(); @@ -1399,9 +1401,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_= t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); =20 - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } =20 /* Test and branch (immediate) @@ -1413,13 +1415,13 @@ static void disas_comp_b_imm(DisasContext *s, uint3= 2_t insn) static void disas_test_b_imm(DisasContext *s, uint32_t insn) { unsigned int bit_pos, op, rt; - uint64_t addr; + int diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; =20 bit_pos =3D (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op =3D extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - addr =3D s->pc_curr + sextract32(insn, 5, 14) * 4; + diff =3D sextract32(insn, 5, 14) * 4; rt =3D extract32(insn, 0, 5); =20 tcg_cmp =3D tcg_temp_new_i64(); @@ -1430,9 +1432,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } =20 /* Conditional branch (immediate) @@ -1444,13 +1446,13 @@ static void disas_test_b_imm(DisasContext *s, uint3= 2_t insn) static void disas_cond_b_imm(DisasContext *s, uint32_t insn) { unsigned int cond; - uint64_t addr; + int diff; =20 if ((insn & (1 << 4)) || (insn & (1 << 24))) { unallocated_encoding(s); return; } - addr =3D s->pc_curr + sextract32(insn, 5, 19) * 4; + diff =3D sextract32(insn, 5, 19) * 4; cond =3D extract32(insn, 0, 4); =20 reset_btype(s); @@ -1458,12 +1460,12 @@ static void disas_cond_b_imm(DisasContext *s, uint3= 2_t insn) /* genuinely conditional branches */ TCGLabel *label_match =3D gen_new_label(); arm_gen_test_cc(cond, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } else { /* 0xe and 0xf are both "always" conditions */ - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } } =20 @@ -1637,7 +1639,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * any pending interrupts immediately. */ reset_btype(s); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; =20 case 7: /* SB */ @@ -1649,7 +1651,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * MB and end the TB instead. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; =20 default: @@ -14965,7 +14967,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; default: case DISAS_UPDATE_EXIT: diff --git a/target/arm/translate.c b/target/arm/translate.c index 638a051281..2b9a58b442 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2597,8 +2597,10 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + target_ulong dest =3D s->pc_curr + diff; + if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); @@ -2632,7 +2634,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest); + gen_goto_tb(s, tbno, dest - s->pc_curr); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -9806,7 +9808,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: gen_set_pc_im(dc, dc->base.pc_next); @@ -9858,7 +9860,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) gen_set_pc_im(dc, dc->base.pc_next); gen_singlestep_exception(dc); } else { - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); } } } --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661210956; cv=none; d=zohomail.com; s=zohoarc; b=WAzZaHLkQ41yDKcPqE6RGAhE6cqJ28tG+8+uSdv4DHqeoAvYhLnweeIGInbnY8g9q9ypyhy4f+XbGAaV0eLpsGTYtI7X56Uwj+GLJwCge4awV/Z0YGSikc6IES5NtOItT8Q5yL03e/y4baG/cyPmwadaR9ZajKZQgX7HWSWgHH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661210956; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RRRZz0yfBzKJ1AXCYIskdo1GmhmX0vcEC/KRCrvx5Es=; b=O9uUehIXxBpNw/Z949mvECEYMjgXe2EFLW2Vb9VNFCjrlCVQs4HwI8/WycO8mH5GoPjomox/WmcAYnMLyxa17zUYz82/fUno70IhImM8Nvz/yRFHvrcEkCL4XadrY85GGXZodcwLVgva+mGXFwj8dmPCVIaG2rQoYVlH0JXaoH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661210956534773.351384573255; Mon, 22 Aug 2022 16:29:16 -0700 (PDT) Received: from localhost ([::1]:45638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGr4-0007dQ-EN for importer@patchew.org; Mon, 22 Aug 2022 19:29:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlx-0005i2-O7 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:58 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:42582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGlt-0005dk-N9 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:57 -0400 Received: by mail-pj1-x1034.google.com with SMTP id s3-20020a17090a2f0300b001facfc6fdbcso12234933pjd.1 for ; Mon, 22 Aug 2022 16:23:53 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RRRZz0yfBzKJ1AXCYIskdo1GmhmX0vcEC/KRCrvx5Es=; b=g6TV7hQD4VeMBhIjZFJqBvJtVIRzkMxH86VOBemuqY1b+cdAwGFmlJCenApkWolJ1G M5gilZQXXmCNpItH3HZiaIUIsTaThJvoAjrxo6guXmwOKqlUx3UG5r3uydavTgqMnwWZ AtJFkA7VTypiztp1mIiD6zZ0d6M/qsFPDKRllMUZ6qbhxgnh/eqmWj/Q1ft/G49dYESU bNtabY4xMgCNv4uFKyltiuOJoOtDgPktTYhhOLWvFezldeo7IpGyfdxckMpupsMDy3rr 7A2byg7fR5Eor5vCYOU+N+7EeZ04Mon95EJKDtysDW14YYEeOJsVugPE2iN8wgpGb8l3 Sivg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RRRZz0yfBzKJ1AXCYIskdo1GmhmX0vcEC/KRCrvx5Es=; b=jzgzu+U6zIw8WId7dFXD/JBVuPPmBZnZdlR/s3yn5ISYxDVeS+csdknNTY/u1ig7R+ 3iKZGczYxZApDNJoSzdNrdMMW2V0kxCtFD4+5cLR5K3W2jSkZ+camD0FifGqyHxdylRp CU4nfWjpFT27Wj+Xl2T7wUMFb10xKW4pzJWwZwGJUdpUwrzDFG8hZvfWpT24c8x6mtn0 8RA5yD0B+Kx7wEqidrqdztiqMx6YB1I9o2yiWkFstZBlgnenoEZqzjTTOdIrC3TNsRMY XoYFWiCVR8DFJmiitd0OBhA7fczpE0Da97wIA8bVROzylgUtZnuCvXPJcdV40kdehQHS Nufw== X-Gm-Message-State: ACgBeo2hdjWDYqZGkt/6Ei4teNQa2/PJkCIfGi1U/ju8PrAUE1LSvCgp xT7Ivmg0P7RzkPPsKSg3JLHyaqEXdMcvCw== X-Google-Smtp-Source: AA6agR4EgipO3HX28UuOotnhHqi5ENeFMGyJkxUKCGiYrzfwczDjtGRu/hbEq02i1fhjbBRkGKaMKw== X-Received: by 2002:a17:90b:1e53:b0:1fb:3aba:372e with SMTP id pi19-20020a17090b1e5300b001fb3aba372emr629903pjb.34.1661210631885; Mon, 22 Aug 2022 16:23:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 11/17] target/arm: Change gen_*set_pc_im to gen_*update_pc Date: Mon, 22 Aug 2022 16:23:32 -0700 Message-Id: <20220822232338.1727934-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661210958319100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values by passing in pc difference. Signed-off-by: Richard Henderson --- target/arm/translate-a32.h | 2 +- target/arm/translate.h | 6 ++-- target/arm/translate-a64.c | 32 +++++++++--------- target/arm/translate-vfp.c | 2 +- target/arm/translate.c | 68 ++++++++++++++++++++------------------ 5 files changed, 56 insertions(+), 54 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 78a84c1414..09c8f467aa 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele,= MemOp memop); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_condexec(DisasContext *s); -void gen_set_pc_im(DisasContext *s, target_ulong val); +void gen_update_pc(DisasContext *s, int diff); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); diff --git a/target/arm/translate.h b/target/arm/translate.h index 90bf7c57fc..33b94a18bb 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -254,7 +254,7 @@ static inline int curr_insn_len(DisasContext *s) * For instructions which want an immediate exit to the main loop, as oppo= sed * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, th= is * doesn't write the PC on exiting the translation loop so you need to ens= ure - * something (gen_a64_set_pc_im or runtime helper) has done so before we r= each + * something (gen_a64_update_pc or runtime helper) has done so before we r= each * return from cpu_tb_exec. */ #define DISAS_EXIT DISAS_TARGET_9 @@ -263,14 +263,14 @@ static inline int curr_insn_len(DisasContext *s) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_a64_set_pc_im(uint64_t val); +void gen_a64_update_pc(DisasContext *s, int diff); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_a64_set_pc_im(uint64_t val) +static inline void gen_a64_update_pc(DisasContext *s, int diff) { } #endif diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 695ccd0723..90f31b1dff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,9 @@ static void reset_btype(DisasContext *s) } } =20 -void gen_a64_set_pc_im(uint64_t val) +void gen_a64_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i64(cpu_pc, val); + tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); } =20 /* @@ -342,14 +342,14 @@ static void gen_exception_internal(int excp) =20 static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int = excp) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; } @@ -384,11 +384,11 @@ static void gen_goto_tb(DisasContext *s, int n, int d= iff) =20 if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); - gen_a64_set_pc_im(dest); + gen_a64_update_pc(s, diff); tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp =3D DISAS_NORETURN; } else { - gen_a64_set_pc_im(dest); + gen_a64_update_pc(s, diff); if (s->ss_active) { gen_step_complete_exception(s); } else { @@ -1960,7 +1960,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, uint32_t syndrome; =20 syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_access_check_cp_reg(cpu_env, tcg_constant_ptr(ri), tcg_constant_i32(syndrome), @@ -1970,7 +1970,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, * The readfn or writefn might raise an exception; * synchronize the CPU state in case it does. */ - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); } =20 /* Handle special cases first */ @@ -2180,7 +2180,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) /* The pre HVC helper handles cases when HVC gets trapped * as an undefined insn by runtime configuration. */ - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, @@ -2191,7 +2191,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) unallocated_encoding(s); break; } - gen_a64_set_pc_im(s->pc_curr); + gen_a64_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); gen_ss_advance(s); gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, @@ -14954,7 +14954,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) */ switch (dc->base.is_jmp) { default: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_EXIT: case DISAS_JUMP: @@ -14971,13 +14971,13 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) break; default: case DISAS_UPDATE_EXIT: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; case DISAS_UPDATE_NOCHAIN: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(); @@ -14986,11 +14986,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) case DISAS_SWI: break; case DISAS_WFE: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); gen_helper_wfe(cpu_env); break; case DISAS_YIELD: - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); gen_helper_yield(cpu_env); break; case DISAS_WFI: @@ -14998,7 +14998,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) * This is a special case because we don't want to just halt * the CPU if trying to debug across a WFI. */ - gen_a64_set_pc_im(dc->base.pc_next); + gen_a64_update_pc(dc, curr_insn_len(dc)); gen_helper_wfi(cpu_env, tcg_constant_i32(4)); /* * The helper doesn't necessarily throw an exception, but we diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 94cc1e4b77..070f465b17 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -856,7 +856,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPSID: if (s->current_el =3D=3D 1) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_check_hcr_el2_trap(cpu_env, tcg_constant_i32(a->rt), tcg_constant_i32(a->reg)); diff --git a/target/arm/translate.c b/target/arm/translate.c index 2b9a58b442..92c52edb7b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -772,9 +772,9 @@ void gen_set_condexec(DisasContext *s) } } =20 -void gen_set_pc_im(DisasContext *s, target_ulong val) +void gen_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i32(cpu_R[15], val); + tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); } =20 /* Set PC and Thumb state from var. var is marked as dead. */ @@ -866,7 +866,7 @@ static inline void gen_bxns(DisasContext *s, int rm) =20 /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory * we need to sync state before calling it, but: - * - we don't need to do gen_set_pc_im() because the bxns helper will + * - we don't need to do gen_update_pc() because the bxns helper will * always set the PC itself * - we don't need to do gen_set_condexec() because BXNS is UNPREDICT= ABLE * unless it's outside an IT block or the last insn in an IT block, @@ -887,7 +887,7 @@ static inline void gen_blxns(DisasContext *s, int rm) * We do however need to set the PC, because the blxns helper reads it. * The blxns helper may throw an exception. */ - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); gen_helper_v7m_blxns(cpu_env, var); tcg_temp_free_i32(var); s->base.is_jmp =3D DISAS_EXIT; @@ -1055,7 +1055,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1063,7 +1063,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * for single stepping.) */ s->svc_imm =3D imm16; - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_HVC; } =20 @@ -1072,16 +1072,16 @@ static inline void gen_smc(DisasContext *s) /* As with HVC, we may take an exception either before or after * the insn executes. */ - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_SMC; } =20 static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int = excp) { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1107,10 +1107,10 @@ static void gen_exception_insn_el_v(DisasContext *s= , uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); } else { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; @@ -1125,10 +1125,10 @@ void gen_exception_insn_el(DisasContext *s, uint64_= t pc, int excp, void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t s= yn) { if (s->aarch64) { - gen_a64_set_pc_im(pc); + gen_a64_update_pc(s, pc - s->pc_curr); } else { gen_set_condexec(s); - gen_set_pc_im(s, pc); + gen_update_pc(s, pc - s->pc_curr); } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; @@ -1137,7 +1137,7 @@ void gen_exception_insn(DisasContext *s, uint64_t pc,= int excp, uint32_t syn) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); s->base.is_jmp =3D DISAS_NORETURN; } @@ -2603,10 +2603,10 @@ static void gen_goto_tb(DisasContext *s, int n, int= diff) =20 if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); tcg_gen_exit_tb(s->base.tb, n); } else { - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); gen_goto_ptr(); } s->base.is_jmp =3D DISAS_NORETURN; @@ -2615,9 +2615,11 @@ static void gen_goto_tb(DisasContext *s, int n, int = diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) { + int diff =3D dest - s->pc_curr; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); s->base.is_jmp =3D DISAS_JUMP; return; } @@ -2634,7 +2636,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest - s->pc_curr); + gen_goto_tb(s, tbno, diff); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -2643,7 +2645,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) * Avoid using goto_tb so we really do exit back to the main loop * and don't chain to another TB. */ - gen_set_pc_im(s, dest); + gen_update_pc(s, diff); gen_goto_ptr(); s->base.is_jmp =3D DISAS_NORETURN; break; @@ -2911,7 +2913,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) =20 /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); tcg_reg =3D load_reg(s, rn); gen_helper_msr_banked(cpu_env, tcg_reg, tcg_constant_i32(tgtmode), @@ -2931,7 +2933,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) =20 /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); tcg_reg =3D tcg_temp_new_i32(); gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_constant_i32(tgtmode), @@ -4752,7 +4754,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } =20 gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_access_check_cp_reg(cpu_env, tcg_constant_ptr(ri), tcg_constant_i32(syndrome), @@ -4763,7 +4765,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, * synchronize the CPU state in case it does. */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); } =20 /* Handle special cases first */ @@ -4777,7 +4779,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, unallocated_encoding(s); return; } - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFI; return; default: @@ -5164,7 +5166,7 @@ static void gen_srs(DisasContext *s, addr =3D tcg_temp_new_i32(); /* get_r13_banked() will raise an exception if called from System mode= */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); + gen_update_pc(s, 0); gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); switch (amode) { case 0: /* DA */ @@ -6233,7 +6235,7 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a) * scheduling of other vCPUs. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_YIELD; } return true; @@ -6249,7 +6251,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a) * implemented so we can't sleep like WFI does. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFE; } return true; @@ -6258,7 +6260,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a) static bool trans_WFI(DisasContext *s, arg_WFI *a) { /* For WFI, halt the vCPU until an IRQ. */ - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFI; return true; } @@ -8773,7 +8775,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) (a->imm =3D=3D semihost_imm)) { gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); } else { - gen_set_pc_im(s, s->base.pc_next); + gen_update_pc(s, curr_insn_len(s)); s->svc_imm =3D a->imm; s->base.is_jmp =3D DISAS_SWI; } @@ -9787,7 +9789,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) case DISAS_TOO_MANY: case DISAS_UPDATE_EXIT: case DISAS_UPDATE_NOCHAIN: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ @@ -9811,13 +9813,13 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ case DISAS_JUMP: gen_goto_ptr(); break; case DISAS_UPDATE_EXIT: - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); /* fall through */ default: /* indicate that the hash table must be used to find the next = TB */ @@ -9857,7 +9859,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { - gen_set_pc_im(dc, dc->base.pc_next); + gen_update_pc(dc, curr_insn_len(dc)); gen_singlestep_exception(dc); } else { gen_goto_tb(dc, 1, curr_insn_len(dc)); --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Signed-off-by: Richard Henderson --- target/arm/translate.h | 4 ++-- target/arm/translate-a64.c | 28 +++++++++++-------------- target/arm/translate-m-nocp.c | 6 +++--- target/arm/translate-mve.c | 2 +- target/arm/translate-vfp.c | 6 +++--- target/arm/translate.c | 39 +++++++++++++++++------------------ 6 files changed, 40 insertions(+), 45 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 33b94a18bb..d42059aa1d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -281,9 +281,9 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, +void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, uint32_t syn, uint32_t target_el); -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t s= yn); +void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn); =20 /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 90f31b1dff..422ce9288d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1163,7 +1163,7 @@ static bool fp_access_check_only(DisasContext *s) assert(!s->fp_access_checked); s->fp_access_checked =3D true; =20 - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false, 0), s->fp_excp_el); return false; @@ -1178,7 +1178,7 @@ static bool fp_access_check(DisasContext *s) return false; } if (s->sme_trap_nonstreaming && s->is_nonstreaming) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, false)); return false; } @@ -1198,7 +1198,7 @@ bool sve_access_check(DisasContext *s) goto fail_exit; } } else if (s->sve_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); goto fail_exit; } @@ -1220,7 +1220,7 @@ bool sve_access_check(DisasContext *s) static bool sme_access_check(DisasContext *s) { if (s->sme_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_AccessTrap, false), s->sme_excp_el); return false; @@ -1250,12 +1250,12 @@ bool sme_enabled_check_with_svcr(DisasContext *s, u= nsigned req) return false; } if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_NotStreaming, false)); return false; } if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_InactiveZA, false)); return false; } @@ -1915,7 +1915,7 @@ static void gen_sysreg_undef(DisasContext *s, bool is= read, } else { syndrome =3D syn_uncategorized(); } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); + gen_exception_insn(s, 0, EXCP_UDEF, syndrome); } =20 /* MRS - move from system register @@ -2169,8 +2169,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC= */ gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16)); + gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); break; case 2: /* HVC= */ if (s->current_el =3D=3D 0) { @@ -2183,8 +2182,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_update_pc(s, 0); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, - syn_aa64_hvc(imm16), 2); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); break; case 3: /* SMC= */ if (s->current_el =3D=3D 0) { @@ -2194,8 +2192,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_update_pc(s, 0); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, - syn_aa64_smc(imm16), 3); + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); break; default: unallocated_encoding(s); @@ -14843,7 +14840,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); return; } =20 @@ -14874,8 +14871,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) if (s->btype !=3D 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype)); + gen_exception_insn(s, 0, EXCP_UDEF, syn_btitrap(s->btype)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 4029d7fdd4..694fae7e2e 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -143,7 +143,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM = *a) tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); =20 if (s->fp_excp_el !=3D 0) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } @@ -765,12 +765,12 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } =20 if (a->cp !=3D 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_NOCP, syn_uncategorized()); return true; } =20 if (s->fp_excp_el !=3D 0) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 0cf1b5ea4f..db7ea3f603 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,7 +100,7 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= ()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); return false; } } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 070f465b17..5c5d58d2c6 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -230,7 +230,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ig= nore_vfp_enabled) int coproc =3D arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; uint32_t syn =3D syn_fp_access_trap(1, 0xe, false, coproc); =20 - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el= ); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn, s->fp_excp_el); return false; } =20 @@ -240,7 +240,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ig= nore_vfp_enabled) * appear to be any insns which touch VFP which are allowed. */ if (s->sme_trap_nonstreaming) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn(s, 0, EXCP_UDEF, syn_smetrap(SME_ET_Streaming, curr_insn_len(s) =3D=3D 2)); return false; @@ -272,7 +272,7 @@ bool vfp_access_check_m(DisasContext *s, bool skip_cont= ext_update) * the encoding space handled by the patterns in m-nocp.decode, * and for them we may need to raise NOCP here. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 92c52edb7b..d441e31d3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1103,32 +1103,33 @@ static void gen_exception(int excp, uint32_t syndro= me) tcg_constant_i32(syndrome)); } =20 -static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, +static void gen_exception_insn_el_v(DisasContext *s, int pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); } else { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; } =20 -void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, +void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, uint32_t syn, uint32_t target_el) { - gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); + gen_exception_insn_el_v(s, pc_diff, excp, syn, + tcg_constant_i32(target_el)); } =20 -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t s= yn) +void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn) { if (s->aarch64) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); } else { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; @@ -1145,7 +1146,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, = uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2872,7 +2873,7 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, tcg_el =3D tcg_constant_i32(3); } =20 - gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, + gen_exception_insn_el_v(s, 0, EXCP_UDEF, syn_uncategorized(), tcg_el); tcg_temp_free_i32(tcg_el); return false; @@ -2898,7 +2899,7 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, =20 undef: /* If we get here then some access check did not pass */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); return false; } =20 @@ -5122,8 +5123,7 @@ static void gen_srs(DisasContext *s, * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el =3D=3D 1 && !s->ns && mode =3D=3D ARM_CPU_MODE_MON) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), 3); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3); return; } =20 @@ -8508,7 +8508,7 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * Do the check-and-raise-exception by hand. */ if (s->fp_excp_el) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + gen_exception_insn_el(s, 0, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); return true; } @@ -8611,7 +8611,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp =3D load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= ()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); gen_set_label(skipexc); } =20 @@ -9081,7 +9081,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= ()); + gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); return; } =20 @@ -9090,7 +9090,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); return; } =20 @@ -9655,7 +9655,7 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); + gen_exception_insn(dc, 0, EXCP_UDEF, syn_illegalstate()); return; } =20 @@ -9728,8 +9728,7 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp =3D 0; - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, - syn_uncategorized()); + gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized()); } =20 arm_post_translate_insn(dc); --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661211324; cv=none; d=zohomail.com; s=zohoarc; b=AYKabdYFbGtA/YzCogrFTD0Tkk+MPsrK9NPRWVxt2fHZMcJoq0Mvjq8ugF5vJd0X48e1OfLnS3TPqgOH4sbbJaD4Hm70KVX5P2T+LfkmVZY+JXiPIESiXLzhBkB+Gi8kdoT0Wrm+HB09dN1mcTHaGOGY7m1NHdEf4B15ygvAzd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661211324; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sptqSn2q1MUxoiSJ0oXgREmv1FSN9FwBedSu534JEYA=; b=cjO+FGt376iz92CiSaw7JIiAGUbBlxO44wWCDg0GrJI8B/yZvR0Oy74vKEQ06bqCf1LsAmkxFm40c+RJwTIRW5ifAlcULkfelV+BskYauL15AywhfI8nwodfUbvQKuxgdRRHH0rE4ogLpAE4XsZc/xlHR0wkYpYTmt301KR60hw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661211324509233.20143718112877; Mon, 22 Aug 2022 16:35:24 -0700 (PDT) Received: from localhost ([::1]:54708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGx1-0005n2-EM for importer@patchew.org; Mon, 22 Aug 2022 19:35:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlz-0005jS-2p for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:24:00 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:46949) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGlx-0005ey-7G for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:58 -0400 Received: by mail-pj1-x102d.google.com with SMTP id o14-20020a17090a0a0e00b001fabfd3369cso12896490pjo.5 for ; Mon, 22 Aug 2022 16:23:55 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=sptqSn2q1MUxoiSJ0oXgREmv1FSN9FwBedSu534JEYA=; b=Y4HA7aueTTLEjKrTksc2JhCldaozROqYR6Gx02urcSo8z+bmaYmwHNY6eVslVM5R2L dV7Awf/nQjTEoeBIeQhF159q8CAqUDZo7ez8TbHoIoKbAhaUA4ENU3y/PMhd/fcFi9TH hEP3l9hbzq1A57fXUzs9V5xbqjbeEn80m0g0QaXqMUaseNZSz6wHq5kF7ZYjLsX2prPX vCdFkydOP2UO9+HpNYz8/Tri4SV6n3ROQPYiomAOF73OMLAyd1+bYxI5N/EWhoCTMRAm GGb8eaTB8DMFZ2CKo/7TAJbrS8KnYB5rra5A8by9LaSraV4RdHGaLRCBja9DbedNol6z Q4mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=sptqSn2q1MUxoiSJ0oXgREmv1FSN9FwBedSu534JEYA=; b=Y077C/SYcrG3Zhf6XqX2ivpcViWEp9SJgO0aCSQcmoVuKA2wMtKfYjp9YliNWzS+zr i+AThCxCQ8s1xyftfGr6BH6L4hA/KPsolj1VfHCT+TFMoo7SgFYlewAw+QzXATTaCsuO jPXopYnxNLCM9oVfKFC4hX0yuZ6AAGUlDUFwZiy/gDGw6ApEM/eaOJkc/zG9RUM9488/ lWLBkQDd2768zgRiAe3W4HldA0SHM98fO8OFwYhEN0C35xh9EKqiXs18cgCsc7dk2S81 Q6ILmZ7isWVEgtzy1KnTBq6Joci3ANuQ/xWqtXEp/HztG4/cU+LfHAbzlHaxzCzvEB/0 C20Q== X-Gm-Message-State: ACgBeo2ss3IOaY1mlWQQ0CGfoziU7I0So7uffrVeI8Vd8sbksxKUjnDp au11pXljiLOW7KpAqovCPN+5PGzf6ny/zg== X-Google-Smtp-Source: AA6agR4AdK0/clLVMX6SBug0HZ3QSIxFtjor9PQ+hrQRcaX+EA9PXei7gVZSatff6/6kD4s56H/Vbw== X-Received: by 2002:a17:90b:4b47:b0:1f7:2e06:5752 with SMTP id mi7-20020a17090b4b4700b001f72e065752mr584289pjb.187.1661210634918; Mon, 22 Aug 2022 16:23:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 13/17] target/arm: Change gen_exception_internal to work on displacements Date: Mon, 22 Aug 2022 16:23:34 -0700 Message-Id: <20220822232338.1727934-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211326749100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 6 +++--- target/arm/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 422ce9288d..b777742643 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,9 +340,9 @@ static void gen_exception_internal(int excp) gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); } =20 -static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int = excp) +static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { - gen_a64_update_pc(s, pc - s->pc_curr); + gen_a64_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -2229,7 +2229,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } #endif - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); } else { unallocated_encoding(s); } diff --git a/target/arm/translate.c b/target/arm/translate.c index d441e31d3a..63a41ed438 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1078,10 +1078,10 @@ static inline void gen_smc(DisasContext *s) s->base.is_jmp =3D DISAS_SMC; } =20 -static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int = excp) +static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { gen_set_condexec(s); - gen_update_pc(s, pc - s->pc_curr); + gen_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; } @@ -1175,7 +1175,7 @@ static inline void gen_hlt(DisasContext *s, int imm) s->current_el !=3D 0 && #endif (imm =3D=3D (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); return; } =20 @@ -6565,7 +6565,7 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) !IS_USER(s) && #endif (a->imm =3D=3D 0xab)) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); } else { gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); } @@ -8773,7 +8773,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) !IS_USER(s) && #endif (a->imm =3D=3D semihost_imm)) { - gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST); + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); } else { gen_update_pc(s, curr_insn_len(s)); s->svc_imm =3D a->imm; --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661211522; cv=none; d=zohomail.com; s=zohoarc; b=Ug7103M1AgCFkjbOFcJ1uZpZ9JhKgXSajRPkXEm6p+27N6kCVagsEnCynjny7U6VZOm7wtHgoEAtSJBJuyocSRcoaRVkLYpyPgrCMogdRuMYUJhom+aas/Jx4RDCP36HkEy+5LQhsupIK+09Igpba6isD+7B7L7arKxoPwSIxCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661211522; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RKoJ35vLYvCsMuP+JFswrPYXmhyjLc71nVTkFzG8E7k=; b=E43AXHCwd4agADJqY2X35lTJfHDOZm3l6542OzsRUOCNTB+Xz5YP6tHXa54IvkNKIdQoCyqq0gRAJT1xHU6Gbq9efX/4y9I2JUpVcAlHok/0evANEHrhpbszD1qZtG638QyxHLy1qEoSiMpvOBZqkq13jfH2UU6btDMLm1d91fQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661211522934599.8267823887169; Mon, 22 Aug 2022 16:38:42 -0700 (PDT) Received: from localhost ([::1]:52338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQH0D-0003Dr-UY for importer@patchew.org; Mon, 22 Aug 2022 19:38:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGlz-0005jT-7H for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:24:00 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:43673) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGlw-0005bY-TA for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:23:58 -0400 Received: by mail-pf1-x42f.google.com with SMTP id w138so9197402pfc.10 for ; Mon, 22 Aug 2022 16:23:56 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RKoJ35vLYvCsMuP+JFswrPYXmhyjLc71nVTkFzG8E7k=; b=WLBGS1gAh6iSpNuimV6mUPfJcfa6fd14Rb5wi3pghWXNje53sSNiGEmTMgDpLElnLq 1D2PTil7WFabFFt9rGgd8mPIeMmjfV3pD14PDkaJ9deYVd3zXqgWF6avqF5T1z9L6HsZ 7Sit5f3uxi27Rt4vovhq4rvcnvn052LbYrJM9o4vSWovqPT1O5euAisry+g7nwKtsbXM z2FHfSC8NB14GEwBN/BaAntnCYYdLf5GQvGCnResfoK3AVwbD8egRD2qQRiSCONPW3IY crxY2fYoQwN5Sm/IgJE8/0gPZNyNSdEBTmf3uHOwCpw3PkCcrjEtYGb/x04mGLhiPO+z HAIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RKoJ35vLYvCsMuP+JFswrPYXmhyjLc71nVTkFzG8E7k=; b=MQ5cEtNSYIgyJFe0YuRicAfCznDs9b5TSOguq5ztPtTCzpVhq9zdnw4mXUK3RW+r9r DLxZ9pH94LdQYQ0SiUzfEikLrmyo57Db3EmvWNZpk7fue2Y7fuh4074+jAtcihcGmoau lLSLDlYKYZCcl8cSHP+Yz2ifcVYA9PMAPmygNAXz5bCzvb7dJWxAeqk6XA9SKFegiwO7 tOKcSUgKIPnjoac6tt+X/CWwNpHOJXMBp6LuSYbmGWNKdnldbvNVCyNoGIsrpKpr9uaA 4qOGoJ5fk9jL4NUlnIdt8ajvXceeeum/W4VlppIJqYb2pfCFJeOzhgA2CSYFM0EFR+7A 1Wrg== X-Gm-Message-State: ACgBeo0KGh41WwgdttDFNxn+aTP4dQifyctsXeoKJBDOtsYZzcuAKBYH KO0ZZbST7WkOlQdtU7GR+1uiCZ7c8XjywA== X-Google-Smtp-Source: AA6agR7h05kdZNzhDgq1OUmXQpnIC6zaHUhk1pbLp0ZjhzVVkuE+6upkwutOWdd2PrN81+mf9PRsbg== X-Received: by 2002:a63:6a48:0:b0:42a:3cab:cc36 with SMTP id f69-20020a636a48000000b0042a3cabcc36mr15265356pgc.135.1661210636093; Mon, 22 Aug 2022 16:23:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 14/17] target/arm: Change gen_jmp* to work on displacements Date: Mon, 22 Aug 2022 16:23:35 -0700 Message-Id: <20220822232338.1727934-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211523588100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 63a41ed438..4d13e365e2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -270,6 +270,12 @@ static uint32_t read_pc(DisasContext *s) return s->pc_curr + (s->thumb ? 4 : 8); } =20 +/* The pc_curr difference for an architectural jump. */ +static int jmp_diff(DisasContext *s, int diff) +{ + return diff + (s->thumb ? 4 : 8); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { @@ -2614,10 +2620,8 @@ static void gen_goto_tb(DisasContext *s, int n, int = diff) } =20 /* Jump, specifying which TB number to use if we gen_goto_tb() */ -static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) +static void gen_jmp_tb(DisasContext *s, int diff, int tbno) { - int diff =3D dest - s->pc_curr; - if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ gen_update_pc(s, diff); @@ -2659,9 +2663,9 @@ static inline void gen_jmp_tb(DisasContext *s, uint32= _t dest, int tbno) } } =20 -static inline void gen_jmp(DisasContext *s, uint32_t dest) +static inline void gen_jmp(DisasContext *s, int diff) { - gen_jmp_tb(s, dest, 0); + gen_jmp_tb(s, diff, 0); } =20 static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) @@ -8331,7 +8335,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) =20 static bool trans_B(DisasContext *s, arg_i *a) { - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 @@ -8346,14 +8350,14 @@ static bool trans_B_cond_thumb(DisasContext *s, arg= _ci *a) return true; } arm_skip_unless(s, a->cond); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 static bool trans_BL(DisasContext *s, arg_i *a) { tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 @@ -8373,7 +8377,8 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); store_cpu_field_constant(!s->thumb, thumb); - gen_jmp(s, (read_pc(s) & ~3) + a->imm); + /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ + gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); return true; } =20 @@ -8534,10 +8539,10 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * when we take this upcoming exit from this TB, so gen_jmp_tb() i= s OK. */ } - gen_jmp_tb(s, s->base.pc_next, 1); + gen_jmp_tb(s, curr_insn_len(s), 1); =20 gen_set_label(nextlabel); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 @@ -8617,7 +8622,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) =20 if (a->f) { /* Loop-forever: just jump back to the loop start */ - gen_jmp(s, read_pc(s) - a->imm); + gen_jmp(s, jmp_diff(s, -a->imm)); return true; } =20 @@ -8648,7 +8653,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tcg_temp_free_i32(decr); } /* Jump back to the loop start */ - gen_jmp(s, read_pc(s) - a->imm); + gen_jmp(s, jmp_diff(s, -a->imm)); =20 gen_set_label(loopend); if (a->tp) { @@ -8656,7 +8661,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); } /* End TB, continuing to following insn */ - gen_jmp_tb(s, s->base.pc_next, 1); + gen_jmp_tb(s, curr_insn_len(s), 1); return true; } =20 @@ -8755,7 +8760,7 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, tmp, 0, s->condlabel); tcg_temp_free_i32(tmp); - gen_jmp(s, read_pc(s) + a->imm); + gen_jmp(s, jmp_diff(s, a->imm)); return true; } =20 --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661211446; cv=none; d=zohomail.com; s=zohoarc; b=FZHjFlEqOQRQWXE61a1rOpI9b4s7yFVlS0tW/WLzbFS/En/kTZeely8QdTSpiG1xisijHPz6KSyhgbTqqzBshrkrAGVnoMvGXZc30kS70w4JwjDik5soESMQBTG6ZZJkzgTSxx/9/7LRXGCdi0REtu99KkayYFouuXbOtz6cR34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661211446; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bPLSwnwAm3KKQjuztom5hM3FzbmQvthZN4SqhLXx1Bg=; b=P2KnFrbS9cEETvVwntMf3c04bPL5HATgKqXMKI7GbfjA0fThdi53JOj7pBhqMtmpJNZlKBY2O4GbL+K9xDeBMvqiqSl/yMbVPEHfc22NyBnFb3xqnmPitQZa+HXnQWbFzuPPeoeJ+l5y201zLd7vPypQl0wOtmdFhQEi9lY5TJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661211446646701.2963530777847; Mon, 22 Aug 2022 16:37:26 -0700 (PDT) Received: from localhost ([::1]:42558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQGyz-0001Iu-Gq for importer@patchew.org; Mon, 22 Aug 2022 19:37:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGm0-0005jj-Eg for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:24:00 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:39788) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGly-0005fe-JH for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:24:00 -0400 Received: by mail-pg1-x52d.google.com with SMTP id q9so1705707pgq.6 for ; Mon, 22 Aug 2022 16:23:58 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:c3f1:b74f:5edd:63af]) by smtp.gmail.com with ESMTPSA id k17-20020aa79731000000b0052d3899f8c2sm3809112pfg.4.2022.08.22.16.23.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 16:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=bPLSwnwAm3KKQjuztom5hM3FzbmQvthZN4SqhLXx1Bg=; b=UeNdYtLADZG4eSDIPPAhVi4iVHBkj7Yk9I/guWApjmVI3meS3LoDAp23SpcgKqbece d+/gxLr0Xfn0UvS5MV7YKDX5pzM19o53gf96v3BAxEBQd1RvrB3vnQtJ1ixO1EAShzOp IcuF7eQLmPutmE4UVj5YG1Dl3/NZ7xzrdtfKwsuE3Dd6A6H7IzBollcn2FP1Q4Gx//RP GNqau1xp2bM3YZP5dOC2A2W12Y7arlTK5i2hQfOV1YQFmXcuz+sZAfZkPTedInzGxirr +kTt4SSMbZ9PENtllAAOOh3TZDLSof6hOoT3BpW4nJ/tWZZg+nZutuHp/YZTS4WdJogq g4Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=bPLSwnwAm3KKQjuztom5hM3FzbmQvthZN4SqhLXx1Bg=; b=yn93mu9jARU1QLSWWaPM8eLjPraLJaqCoqPio0smY4wLQae0NZol2a9I06F3Nywial at4onQcfcywYuCZLhGFb/wwP5dVyNCXl53eLfbb9bn/v+xMBBTD1UT2U7jmAOU+9TXcN iisFVoWHug7cwl1K5zptHGY/ultr4gsCYdoLvCuIkCHQRyN1Zz3QIRUg0B1Jbe9RuxIy 15Vm0Ghh4IFBiY1TTvVfRH86W/D1EkHSAcA6bnalgIK47oSHw0r1IJpMWhMnWTyaOpTA m+MIa2G0BUWfOHdqv4jP+4miLi8C9Doam1B1IFUkyvwdGKuiGHH94xv6G/PyCn9VhFG2 AZtA== X-Gm-Message-State: ACgBeo3fNMcyApMZBPxLmonxiQ9H/CceAnVhE/HwLyQeLneiHLSBdK+b kautqPAMI+d8IA503zvZS74GDIr0Y6+Wag== X-Google-Smtp-Source: AA6agR503Gl5KI0r5OF/+fBGfpzlWtaFm5Dsb0jZ0f9K06pcXVSYd4iWyZBUjWplASy6/m5Gq4mX/Q== X-Received: by 2002:a63:ee49:0:b0:428:8e10:200a with SMTP id n9-20020a63ee49000000b004288e10200amr18580455pgk.453.1661210637193; Mon, 22 Aug 2022 16:23:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 15/17] target/arm: Introduce gen_pc_plus_diff for aarch64 Date: Mon, 22 Aug 2022 16:23:36 -0700 Message-Id: <20220822232338.1727934-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822232338.1727934-1-richard.henderson@linaro.org> References: <20220822232338.1727934-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661211447286100001 Content-Type: text/plain; charset="utf-8" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b777742643..322a09c503 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,14 @@ static void reset_btype(DisasContext *s) } } =20 +static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, int diff) +{ + tcg_gen_movi_i64(dest, s->pc_curr + diff); +} + void gen_a64_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_pc, diff); } =20 /* @@ -1368,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) =20 if (insn & (1U << 31)) { /* BL Branch with link */ - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); } =20 /* B Branch / BL Branch with link */ @@ -2319,11 +2324,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc =3D=3D 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr =3D cpu_reg(s, 30); + if (dst =3D=3D lr) { + TCGv_i64 tmp =3D new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst =3D tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; =20 case 8: /* BRAA */ @@ -2346,11 +2357,17 @@ static void disas_uncond_b_reg(DisasContext *s, uin= t32_t insn) } else { dst =3D cpu_reg(s, rn); } - gen_a64_set_pc(s, dst); /* BLRAA also needs to load return address */ if (opc =3D=3D 9) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr =3D cpu_reg(s, 30); + if (dst =3D=3D lr) { + TCGv_i64 tmp =3D new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst =3D tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; =20 case 4: /* ERET */ @@ -2918,7 +2935,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - clean_addr =3D tcg_constant_i64(s->pc_curr + imm); + clean_addr =3D new_tmp_a64(s); + gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -4262,23 +4280,22 @@ static void disas_ldst(DisasContext *s, uint32_t in= sn) static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { unsigned int page, rd; - uint64_t base; - uint64_t offset; + int64_t offset; =20 page =3D extract32(insn, 31, 1); /* SignExtend(immhi:immlo) -> offset */ offset =3D sextract64(insn, 5, 19); offset =3D offset << 2 | extract32(insn, 29, 2); rd =3D extract32(insn, 0, 5); - base =3D s->pc_curr; =20 if (page) { /* ADRP (page based) */ - base &=3D ~0xfff; offset <<=3D 12; + /* The page offset is ok for TARGET_TB_PCREL. */ + offset -=3D s->pc_curr & 0xfff; } =20 - tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); + gen_pc_plus_diff(s, cpu_reg(s, rd), offset); } =20 /* --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson --- target/arm/translate.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4d13e365e2..f01c8df60a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -276,11 +276,16 @@ static int jmp_diff(DisasContext *s, int diff) return diff + (s->thumb ? 4 : 8); } =20 +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int diff) +{ + tcg_gen_movi_i32(var, s->pc_curr + diff); +} + /* Set a variable to the value of a CPU register. */ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg =3D=3D 15) { - tcg_gen_movi_i32(var, read_pc(s)); + gen_pc_plus_diff(s, var, jmp_diff(s, 0)); } else { tcg_gen_mov_i32(var, cpu_R[reg]); } @@ -296,7 +301,8 @@ TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int = ofs) TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 if (reg =3D=3D 15) { - tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs); + /* This difference computes a page offset so ok for TARGET_TB_PCRE= L. */ + gen_pc_plus_diff(s, tmp, (read_pc(s) & ~3) - s->pc_curr + ofs); } else { tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); } @@ -1158,7 +1164,7 @@ void unallocated_encoding(DisasContext *s) /* Force a TB lookup after an instruction that changes the CPU state. */ void gen_lookup_tb(DisasContext *s) { - tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); + gen_pc_plus_diff(s, cpu_R[15], curr_insn_len(s)); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -6485,7 +6491,7 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return false; } tmp =3D load_reg(s, a->rm); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_bx(s, tmp); return true; } @@ -8356,7 +8362,7 @@ static bool trans_B_cond_thumb(DisasContext *s, arg_c= i *a) =20 static bool trans_BL(DisasContext *s, arg_i *a) { - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8375,7 +8381,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) if (s->thumb && (a->imm & 2)) { return false; } - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | s->thumb); store_cpu_field_constant(!s->thumb, thumb); /* This difference computes a page offset so ok for TARGET_TB_PCREL. */ gen_jmp(s, (read_pc(s) & ~3) - s->pc_curr + a->imm); @@ -8385,7 +8391,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) { assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + gen_pc_plus_diff(s, cpu_R[14], jmp_diff(s, a->imm << 12)); return true; } =20 @@ -8395,7 +8401,7 @@ static bool trans_BL_suffix(DisasContext *s, arg_BL_s= uffix *a) =20 assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8411,7 +8417,7 @@ static bool trans_BLX_suffix(DisasContext *s, arg_BLX= _suffix *a) tmp =3D tcg_temp_new_i32(); tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_pc_plus_diff(s, cpu_R[14], curr_insn_len(s) | 1); gen_bx(s, tmp); return true; } @@ -8734,10 +8740,11 @@ static bool op_tbranch(DisasContext *s, arg_tbranch= *a, bool half) tcg_gen_add_i32(addr, addr, tmp); =20 gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB); - tcg_temp_free_i32(addr); =20 tcg_gen_add_i32(tmp, tmp, tmp); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + gen_pc_plus_diff(s, addr, jmp_diff(s, 0)); + tcg_gen_add_i32(tmp, tmp, addr); + tcg_temp_free_i32(addr); store_reg(s, 15, tmp); return true; } --=20 2.34.1 From nobody Sun May 12 19:40:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661212313; cv=none; d=zohomail.com; s=zohoarc; b=ROAt+kMv0wkVaAucLTCVjdYwbEh9M9dETMV5AmSj8ypsdDgjcA0lazClUUHRydM1V8maozmvc/GcGeQ7JjPv3IkHdW/UmnXYg1GYMyLluhWp4TjWXBTUviozsDI3MzfsOPbjziYOkEzfQCpZRGf5tLW8oP80r4uHJowAW16OLnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661212313; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k/lBvxUYj7/biMnws+9sbX8m6+YHiVr97vq+CVkxwR0=; b=gkOsOjqRAgpV5uriP6fhin/WZOM7iRVBhSs+xklWHO7zkPJ+q2JK3tmB6OMgt6Mtcx93CmAUKkpU5aSWdvmxtU99hHFqMW10q2aIMjQqHr65ZTsZ96FSX/tqB861V19OaIEDN35w2/hhkTCuk0862KSu13VSSUaIs/1KxzD6Jcs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661212313944998.8930923004648; Mon, 22 Aug 2022 16:51:53 -0700 (PDT) Received: from localhost ([::1]:44584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQHCy-000612-Rj for importer@patchew.org; Mon, 22 Aug 2022 19:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQGm4-0005me-Do for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:24:04 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:36672) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQGm2-0005gj-6v for qemu-devel@nongnu.org; Mon, 22 Aug 2022 19:24:04 -0400 Received: by mail-pj1-x1034.google.com with SMTP id r14-20020a17090a4dce00b001faa76931beso15491696pjl.1 for ; Mon, 22 Aug 2022 16:24:00 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661212315651100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 ++ target/arm/translate.h | 6 ++++ target/arm/cpu.c | 23 +++++++------- target/arm/translate-a64.c | 37 ++++++++++++++++++----- target/arm/translate.c | 62 ++++++++++++++++++++++++++++++-------- 5 files changed, 100 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..ef62371d8f 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -34,4 +34,6 @@ =20 #define NB_MMU_MODES 15 =20 +#define TARGET_TB_PCREL 1 + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index d42059aa1d..7717ea3f45 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -12,6 +12,12 @@ typedef struct DisasContext { =20 /* The address of the current instruction being translated. */ target_ulong pc_curr; + /* + * For TARGET_TB_PCREL, the value relative to pc_curr against which + * offsets must be computed for cpu_pc. -1 if unknown due to jump. + */ + target_ulong pc_save; + target_ulong pc_cond_save; target_ulong page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 047bf3f4ab..f5e74b6c3b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -64,17 +64,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - */ - if (is_a64(env)) { - env->pc =3D tb_pc(tb); - } else { - env->regs[15] =3D tb_pc(tb); + /* The program counter is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + CPUARMState *env =3D cs->env_ptr; + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb_pc(tb); + } else { + env->regs[15] =3D tb_pc(tb); + } } } #endif /* CONFIG_TCG */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 322a09c503..a433189722 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -150,12 +150,18 @@ static void reset_btype(DisasContext *s) =20 static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, int diff) { - tcg_gen_movi_i64(dest, s->pc_curr + diff); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i64(dest, s->pc_curr + diff); + } } =20 void gen_a64_update_pc(DisasContext *s, int diff) { gen_pc_plus_diff(s, cpu_pc, diff); + s->pc_save =3D s->pc_curr + diff; } =20 /* @@ -209,6 +215,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) * then loading an address into the PC will clear out any tag. */ gen_top_byte_ignore(s, cpu_pc, src, s->tbii); + s->pc_save =3D -1; } =20 /* @@ -347,16 +354,22 @@ static void gen_exception_internal(int excp) =20 static void gen_exception_internal_insn(DisasContext *s, int pc_diff, int = excp) { + target_ulong pc_save =3D s->pc_save; + gen_a64_update_pc(s, pc_diff); gen_exception_internal(excp); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { + target_ulong pc_save =3D s->pc_save; + gen_a64_update_pc(s, 0); gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_step_complete_exception(DisasContext *s) @@ -385,11 +398,16 @@ static inline bool use_goto_tb(DisasContext *s, uint6= 4_t dest) =20 static void gen_goto_tb(DisasContext *s, int n, int diff) { - uint64_t dest =3D s->pc_curr + diff; + target_ulong pc_save =3D s->pc_save; =20 - if (use_goto_tb(s, dest)) { - tcg_gen_goto_tb(n); - gen_a64_update_pc(s, diff); + if (use_goto_tb(s, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_a64_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_a64_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); s->base.is_jmp =3D DISAS_NORETURN; } else { @@ -401,6 +419,7 @@ static void gen_goto_tb(DisasContext *s, int n, int dif= f) s->base.is_jmp =3D DISAS_NORETURN; } } + s->pc_save =3D pc_save; } =20 static void init_tmp_a64_array(DisasContext *s) @@ -14717,7 +14736,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, =20 dc->isar =3D &arm_cpu->isar; dc->condjmp =3D 0; - + dc->pc_save =3D dc->base.pc_first; dc->aarch64 =3D true; dc->thumb =3D false; dc->sctlr_b =3D 0; @@ -14799,8 +14818,12 @@ static void aarch64_tr_tb_start(DisasContextBase *= db, CPUState *cpu) static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_arg =3D dc->base.pc_next; =20 - tcg_gen_insn_start(dc->base.pc_next, 0, 0); + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, 0, 0); dc->insn_start =3D tcg_last_op(); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index f01c8df60a..a25ba48e87 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -164,6 +164,7 @@ void arm_gen_condlabel(DisasContext *s) if (!s->condjmp) { s->condlabel =3D gen_new_label(); s->condjmp =3D 1; + s->pc_cond_save =3D s->pc_save; } } =20 @@ -278,7 +279,12 @@ static int jmp_diff(DisasContext *s, int diff) =20 static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int diff) { - tcg_gen_movi_i32(var, s->pc_curr + diff); + assert(s->pc_save !=3D -1); + if (TARGET_TB_PCREL) { + tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff); + } else { + tcg_gen_movi_i32(var, s->pc_curr + diff); + } } =20 /* Set a variable to the value of a CPU register. */ @@ -321,6 +327,7 @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); s->base.is_jmp =3D DISAS_JUMP; + s->pc_save =3D -1; } else if (reg =3D=3D 13 && arm_dc_feature(s, ARM_FEATURE_M)) { /* For M-profile SP bits [1:0] are always zero */ tcg_gen_andi_i32(var, var, ~3); @@ -786,7 +793,8 @@ void gen_set_condexec(DisasContext *s) =20 void gen_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_R[15], diff); + s->pc_save =3D s->pc_curr + diff; } =20 /* Set PC and Thumb state from var. var is marked as dead. */ @@ -796,6 +804,7 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); + s->pc_save =3D -1; } =20 /* @@ -1118,6 +1127,8 @@ static void gen_exception(int excp, uint32_t syndrome) static void gen_exception_insn_el_v(DisasContext *s, int pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_el) { + target_ulong pc_save =3D s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1126,6 +1137,7 @@ static void gen_exception_insn_el_v(DisasContext *s, = int pc_diff, int excp, } gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 void gen_exception_insn_el(DisasContext *s, int pc_diff, int excp, @@ -1137,6 +1149,8 @@ void gen_exception_insn_el(DisasContext *s, int pc_di= ff, int excp, =20 void gen_exception_insn(DisasContext *s, int pc_diff, int excp, uint32_t s= yn) { + target_ulong pc_save =3D s->pc_save; + if (s->aarch64) { gen_a64_update_pc(s, pc_diff); } else { @@ -1145,6 +1159,7 @@ void gen_exception_insn(DisasContext *s, int pc_diff,= int excp, uint32_t syn) } gen_exception(excp, syn); s->base.is_jmp =3D DISAS_NORETURN; + s->pc_save =3D pc_save; } =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) @@ -2612,11 +2627,14 @@ static void gen_goto_ptr(void) */ static void gen_goto_tb(DisasContext *s, int n, int diff) { - target_ulong dest =3D s->pc_curr + diff; - - if (translator_use_goto_tb(&s->base, dest)) { - tcg_gen_goto_tb(n); - gen_update_pc(s, diff); + if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { + if (TARGET_TB_PCREL) { + gen_update_pc(s, diff); + tcg_gen_goto_tb(n); + } else { + tcg_gen_goto_tb(n); + gen_update_pc(s, diff); + } tcg_gen_exit_tb(s->base.tb, n); } else { gen_update_pc(s, diff); @@ -2628,10 +2646,13 @@ static void gen_goto_tb(DisasContext *s, int n, int= diff) /* Jump, specifying which TB number to use if we gen_goto_tb() */ static void gen_jmp_tb(DisasContext *s, int diff, int tbno) { + target_ulong pc_save =3D s->pc_save; + if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ gen_update_pc(s, diff); s->base.is_jmp =3D DISAS_JUMP; + s->pc_save =3D pc_save; return; } switch (s->base.is_jmp) { @@ -2667,6 +2688,7 @@ static void gen_jmp_tb(DisasContext *s, int diff, int= tbno) */ g_assert_not_reached(); } + s->pc_save =3D pc_save; } =20 static inline void gen_jmp(DisasContext *s, int diff) @@ -9333,7 +9355,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->isar =3D &cpu->isar; dc->condjmp =3D 0; - + dc->pc_save =3D dc->base.pc_first; dc->aarch64 =3D false; dc->thumb =3D EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; @@ -9488,13 +9510,17 @@ static void arm_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) * fields here. */ uint32_t condexec_bits; + target_ulong pc_arg =3D dc->base.pc_next; =20 + if (TARGET_TB_PCREL) { + pc_arg &=3D ~TARGET_PAGE_MASK; + } if (dc->eci) { condexec_bits =3D dc->eci << 4; } else { condexec_bits =3D (dc->condexec_cond << 4) | (dc->condexec_mask >>= 1); } - tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); + tcg_gen_insn_start(pc_arg, condexec_bits, 0); dc->insn_start =3D tcg_last_op(); } =20 @@ -9537,7 +9563,10 @@ static bool arm_check_ss_active(DisasContext *dc) =20 static void arm_post_translate_insn(DisasContext *dc) { - if (dc->condjmp && !dc->base.is_jmp) { + if (dc->condjmp && dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->pc_save !=3D dc->pc_cond_save) { + gen_update_pc(dc, dc->pc_cond_save - dc->pc_save); + } gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -9867,6 +9896,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) =20 if (dc->condjmp) { /* "Condition failed" instruction codepath for the branch/trap ins= n */ + dc->pc_save =3D dc->pc_cond_save; gen_set_label(dc->condlabel); gen_set_condexec(dc); if (unlikely(dc->ss_active)) { @@ -9929,11 +9959,19 @@ void restore_state_to_opc(CPUARMState *env, Transla= tionBlock *tb, target_ulong *data) { if (is_a64(env)) { - env->pc =3D data[0]; + if (TARGET_TB_PCREL) { + env->pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + env->pc =3D data[0]; + } env->condexec_bits =3D 0; env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } else { - env->regs[15] =3D data[0]; + if (TARGET_TB_PCREL) { + env->regs[15] =3D (env->regs[15] & TARGET_PAGE_MASK) | data[0]; + } else { + env->regs[15] =3D data[0]; + } env->condexec_bits =3D data[1]; env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } --=20 2.34.1