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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Ilw+7P1s37Y2jNcUV45jTcqxm83VECE5VnusacIVBZ0=; b=wBnjAVA3P+8srMrTF+7tQdaEZukzf/oEtqCvHzPPqPbkPMCMLWgHMQUkeY+UMwgx1h jWTUTTTvKrWZRYR5NQl72p8FEqXXTpXMC/QtALipLBMcn97B6DCeO3sdnVVf5mO6lG2H LPX2+RvYWVjMPwG3l6XBnicpiQmh6UI2yjnKSVgFxTuSQ7suU1NJTxE0iLFQH2K+s608 pXFZJ3j2un7xPCyay9KCA+S7+rYImb7/V9q3yfUzQkkqKayZbuYWd+rkwlg4hIxRVyHi B8gHkSblioksn2Dg8tgU0hj3F1EORgTzYHHreosxXC51pdKtT49Z7BHqOie/g9HG0akm GOzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Ilw+7P1s37Y2jNcUV45jTcqxm83VECE5VnusacIVBZ0=; b=ws2z/I/j97xb5Va0XwGCQCMJ39BsZujSzh+JsRaRfm+u/fqdXy2CxRpA3Z6Em0rH3D NWLTdKddpZ4moGvljB3ehEuPuFYrFOTa6qCXzDhOfqJBsX+aSzg1eZO0CFU0xELh7au4 cmu7X28AsVhmjmlAPCHvaAibAcaC9WRrN7Wf6cuF85ZUXk4q9ZdaGGShSqIKivXXZLKK gmbL/FqAeRCVgmOgX7Ml1zb7bQcwA0rkR4vNKn6lzPmA2+o0V2yp+0hevERmBYJWt5Pw DxtR39GccvnIg9GFup44ESsCJ5hWn502RV+ZmcXW/y7E/8eBg2boENL4PUgGRWItBS6j CjTg== X-Gm-Message-State: ACgBeo0S7tS9Wcs3MxhnSdZFy3j13bwcuUOiPr6bbZCbNHKkdm86B2zG G4fFkUqjZzHf0dwiioITbcMfN37pOL9bsA== X-Google-Smtp-Source: AA6agR7ZALECQCY95E7aGDb/vgoCc1/gRPXwgzpg1LO1Oe1nGJ5J4SQuPVmveWG0PPlUXf6c96Sl2A== X-Received: by 2002:a63:fb4a:0:b0:429:8605:6ebf with SMTP id w10-20020a63fb4a000000b0042986056ebfmr17273940pgj.225.1661182094863; Mon, 22 Aug 2022 08:28:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 36/66] target/arm: Reorg get_phys_addr_disabled Date: Mon, 22 Aug 2022 08:27:11 -0700 Message-Id: <20220822152741.1617527-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183942491100001 Content-Type: text/plain; charset="utf-8" Use a switch. Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 115 +++++++++++++++++++++++++++-------------------- 1 file changed, 67 insertions(+), 48 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c798b30db2..fa76f98b04 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2281,64 +2281,83 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint64_t hcr; - uint8_t memattr; + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t memattr, shareability; =20 - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + memattr =3D 0x00; /* unused, but Device, nGnRnE */ + shareability =3D 0; /* unused, but non-shareable */ + break; =20 - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); + shareability =3D 0; /* non-shareable */ + goto check_range; } + /* fall through */ + + default: + if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + shareability =3D 2; /* Outer sharable */ + } else { + memattr =3D 0x00; /* unused, but Device, nGnRnE */ + shareability =3D 0; /* non-shareable */ + } + /* fall through */ + + check_range: + { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of + * the bits above PAMax are zero, so logically we only + * need to clear the top byte for TBI. But it's clearer + * to follow the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + break; } =20 result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } + result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; } --=20 2.34.1