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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=iXS0aJbutd/f8RQ8+U+qwbi40Uh9HNiJ8CeYjNnRgmU=; b=r3R4MY7A+vxIM8ux/FhZRt+x8nNWqlUZkim+nYjquB65yzGMh5WIqDjwLHm2lZkaVC FZkujjThzqt79bc2NOTD6xne4dV1fYyyvtPy0cLqrR8KpmfWj1T0ucd1tDC4InaSaytG O/B2FKFQGUgYN1tB0t76/rsz5815MPYHCC4uFl4jiaqRXIO75XImARPj/x7nu+cP4U3T qNRErMNFj8M8ZxQ41SCQ/1Ml9YmCwV6pR12N2akeBlNPZOz5wK2jhaJsszuO7t3NYc1j ALiRF/iwZm9g30AHWVdb57kZrMkF/7MvXMrKUlxVxTsim0ORQL69bhEdvsQ7W8YYgMxE Fi7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=iXS0aJbutd/f8RQ8+U+qwbi40Uh9HNiJ8CeYjNnRgmU=; b=VuX4AMzgiPALfsUCwceSLjurBsV7OeijoKdJUFUNyDpsQPRXrZMlJF8zQqCag4IQRf 6g4tIR0iRVnJH8idqfYB2fHVpXXpG8S72X9C1mDqzd9RotD3KlsEndn+YaBPvz91d362 ES5HcZkwpR67HQ4O9MYsTlbSL7Dx5N61XK7W3FeuIfYJeN50OX87SZHgvtYJgwxnkhFq xXAcKXGIoWDfm8bZAxx/zhU7U9BORjHXgXnG5uBYtsz29HR3MuesbLxmE/hs0yR26uFV 7T+MlBCNjn9vp+uyIWCwmkVwenHE2MBIySytqaXN7bHE2PBGpXuFrRRD9vjCXIw7WL1s BV7w== X-Gm-Message-State: ACgBeo3J76Vz1/OU0o7G77uZLmenmNKleodZDAUAiNCdea/1KDHS00Ot U125hNc7pMGldP6yRoFFNrXxDZnRvHzcSg== X-Google-Smtp-Source: AA6agR5ozWBFFDuN99luOBh606LF/2rSVYBkjfAfJi3E12DJuJ1TkP+fJ5sMe/JEUUEzvVNuwvNQVQ== X-Received: by 2002:a17:902:a5cc:b0:170:d1cf:ac83 with SMTP id t12-20020a170902a5cc00b00170d1cfac83mr20431235plq.14.1661182094058; Mon, 22 Aug 2022 08:28:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 35/66] target/arm: Split out get_phys_addr_disabled Date: Mon, 22 Aug 2022 08:27:10 -0700 Message-Id: <20220822152741.1617527-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661191058911100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4da932b464..c798b30db2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2271,6 +2271,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, return ret; } =20 +/* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.S1DisabledOutput(). + */ +static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + uint64_t hcr; + uint8_t memattr; + + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + result->cacheattrs.shareability =3D 0; + result->cacheattrs.is_s2_format =3D false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + result->cacheattrs.shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + result->cacheattrs.attrs =3D memattr; + return 0; +} + /** * get_phys_addr - get the physical address for this virtual address * @@ -2451,71 +2523,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; - - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of = the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); - } - } - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } - result->cacheattrs.attrs =3D memattr; - return 0; + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); --=20 2.34.1