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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=O81TsU9W9xgRybd2C2RW59kpRj18EtKgy1SuNeOJbJ0=; b=kiPm+u8Hc8qLcHnZFBkQXnyuVsYdWL5yXKcw5yyulDrYozxrWW120rmERBEfVYBSf/ MXkoqAxaMGAbTuH97Gz/bKwySgalZw28mPKBPOBnFE+TqwNbdh5AXFncYPQ5GiRLGkcg 53UBUnTAWIhzPnOoKD5IWWyRcBIUR+oDKvRtYW5FSdNeXQNvLKribFnh+1oF628WhVHd bcju/LMAJrCGqXXToCRyhGJn6s18FIX8doyd9shqer7H/4Bjb7ZRenw4ydWZX7fhW27L qxJdK/K2k/s5D/iijieFxcgfjgevlnDOUZwjVm9bYTPQh29XGan0n0zulb2cga1q4BGi YgIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=O81TsU9W9xgRybd2C2RW59kpRj18EtKgy1SuNeOJbJ0=; b=w9t6/ZcGH002dzL49TG2/fsFlyy91Cn2Cfvf960lxeADm6kONT/QaAc0H76YjswMqc LtrHmnqqbiOqYbwftJ580zc8fbzKwBAIhIwsCCCRnKG5lGdYfa/SNx73Apb8We1+U0T+ rwOa43H0aFkbAcTTZJi8xmGIhQiYBPsJiV2jmRXOyaHWDO4pqcnBUqC73JpQoSlulSjH XuAh3p7kWVKlCGTONhqQKUui7+kxSfSUEtLF8MXFbPIf4zIsFbu7apxBNPikMIjtML// QGbw3JAFd8Bi4Li1RHlvuz5xfi0nJpzIxp/asu7x8EePbyeVzJe/2wk136RkFkX/CNzN xHxw== X-Gm-Message-State: ACgBeo2mjSCF9Is3g3HFPNPPgu3yQ0FR/UppCN1b+SqBy1dhOAfnj6hL QI6tCJEwFuEDieUO02DDIwlZrl8nqdq5pQ== X-Google-Smtp-Source: AA6agR6E4+ybGApzzgDpfTyhyCGROJULZl4dUwPGJIKNQa28w0XmQ346r82ni/MRSuGbyez8qnJfhw== X-Received: by 2002:a63:86c2:0:b0:42a:42d5:a4a6 with SMTP id x185-20020a6386c2000000b0042a42d5a4a6mr12720471pgd.189.1661182077816; Mon, 22 Aug 2022 08:27:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 19/66] target/arm: Add is_secure parameter to regime_translation_disabled Date: Mon, 22 Aug 2022 08:26:54 -0700 Message-Id: <20220822152741.1617527-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186441447100001 Remove the use of regime_is_secure from regime_translation_disabled, using the new parameter instead. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 224ba09ecd..eca7763367 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -131,12 +131,13 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUI= dx mmu_idx, int ttbrn) } =20 /* Return true if the specified stage of address translation is disabled */ -static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x) +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x, + bool is_secure) { uint64_t hcr_el2; =20 if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -163,7 +164,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) =20 if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { return true; } } @@ -201,7 +202,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, ARMMMUFaultInfo *fi) { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2, *is_secure)) { ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; GetPhysAddrResult s2 =3D {}; @@ -1355,9 +1356,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, u= int32_t address, int n; uint32_t mask; uint32_t base; + bool is_secure =3D regime_is_secure(env, mmu_idx); bool is_user =3D regime_is_user(env, mmu_idx); =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -1521,7 +1523,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, result->page_size =3D TARGET_PAGE_SIZE; result->prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx) || + if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -1732,7 +1734,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabl= ed */ hit =3D true; } else if (m_is_ppb_region(env, address)) { hit =3D true; @@ -2306,7 +2308,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, + is_secure)) { return ret; } =20 @@ -2434,7 +2437,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 /* Definitely a real MMU, not an MPU */ =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { uint64_t hcr; uint8_t memattr; =20 --=20 2.34.1