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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=m5cKad2hrAZKHnUS2CVhyFrLT2HL6vfTPa1btDlvuDw=; b=tHtn9GTDnrQuItjNh9GTk2NmQ4iwruAGZqFMWoWjX72HekTJ6D9PplkSh2J38tSiH7 EtRO9kZdHxC2Sgb54GEvIVjPE1NODYO1mXo8i+u/nEjSZGVOHWriWXcUBRKgWYNsyiU9 Ldtmou3tiPJg+B9V4y1t6oYYyKLeilBBKryt2SNK6k7A7LU+NZdHgoURlH6CmBfHgLqq 6c7H/N0yHIQcVW7+z93FUsOlipVk6iyRcmpFoCJfB87qEIU5TivTZyMD7wSJKu9uDRP6 8JrojoHl/xbIIzPOLPqO1Hrvr4a5qz2ycMCpiSd3jqoV7++bclPzAMNjOmW8qbKzpXZ2 T3hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=m5cKad2hrAZKHnUS2CVhyFrLT2HL6vfTPa1btDlvuDw=; b=hZu0jiN9Ngo0hToHidbK/BYMpHoXgzyTW4jxKZJsrmz8TKSmRab2BeyLfYAtboXxiK xZhmPhNvxDY6GJK6OzgbftGRvk3Mn3s7DrkYnF3lIpDICkWsNBGc60LburZxdtesYKTz s72Smknn8SCFHxi2/LcsKEaizWGt011Ah9Z5WjqxqppnKSE8rHzJOJVv7KQoGwlATZsM 4vPzwzUYdTFsLa29Gobie2c9JbW2yvMv2pDhiT4fz33ZIxbwRZE1zal7yXCAELuU0W8R hY/c9hVPQpeW9/IPNEneeNxBo/w/0bFN9DPHLOIDeg94ZNcR+QZystaRK1VdtQkMRsxQ GwUw== X-Gm-Message-State: ACgBeo34OjlzM9PPQTL5Z5CR4UQuyIqWyBYFYBUtoZdx4beNNxCHLFyS 0H+97g9Ic9x4eR7juFioKeS4506ubL9pSg== X-Google-Smtp-Source: AA6agR6oa+6kltN1ntYXRUfef0NlTasCMYNejmapJYnVtgKrQTQcV4gQKWaHAMDYpRnkp1IQGAIanA== X-Received: by 2002:a17:90a:6b4c:b0:1fa:d973:e4eb with SMTP id x12-20020a17090a6b4c00b001fad973e4ebmr20228711pjl.15.1661182063263; Mon, 22 Aug 2022 08:27:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 01/66] target/arm: Create GetPhysAddrResult Date: Mon, 22 Aug 2022 08:26:36 -0700 Message-Id: <20220822152741.1617527-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661182866683100001 Content-Type: text/plain; charset="utf-8" Combine 5 output pointer arguments from get_phys_addr into a single struct. Adjust all callers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 13 ++++- target/arm/helper.c | 27 ++++----- target/arm/m_helper.c | 52 ++++++----------- target/arm/ptw.c | 120 +++++++++++++++++++++------------------- target/arm/tlb_helper.c | 22 +++----- 5 files changed, 109 insertions(+), 125 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b8fefdff67..293e27b996 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1142,11 +1142,18 @@ typedef struct ARMCacheAttrs { bool is_s2_format:1; } ARMCacheAttrs; =20 +/* Fields that are valid upon success. */ +typedef struct GetPhysAddrResult { + hwaddr phys; + target_ulong page_size; + int prot; + MemTxAttrs attrs; + ARMCacheAttrs cacheattrs; +} GetPhysAddrResult; + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 void arm_log_exception(CPUState *cs); diff --git a/target/arm/helper.c b/target/arm/helper.c index d7bc467a2a..68373bc0a9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3107,24 +3107,19 @@ static CPAccessResult ats_access(CPUARMState *env, = const ARMCPRegInfo *ri, static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx) { - hwaddr phys_addr; - target_ulong page_size; - int prot; bool ret; uint64_t par64; bool format64 =3D false; - MemTxAttrs attrs =3D {}; ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; + GetPhysAddrResult res =3D {}; =20 - ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, - &prot, &page_size, &fi, &cacheattrs); + ret =3D get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never * have to deal with the ARMCacheAttrs format for S2 only. */ - assert(!cacheattrs.is_s2_format); + assert(!res.cacheattrs.is_s2_format); =20 if (ret) { /* @@ -3230,12 +3225,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, /* Create a 64-bit PAR */ par64 =3D (1 << 11); /* LPAE bit always set */ if (!ret) { - par64 |=3D phys_addr & ~0xfffULL; - if (!attrs.secure) { + par64 |=3D res.phys & ~0xfffULL; + if (!res.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } - par64 |=3D (uint64_t)cacheattrs.attrs << 56; /* ATTR */ - par64 |=3D cacheattrs.shareability << 7; /* SH */ + par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ + par64 |=3D res.cacheattrs.shareability << 7; /* SH */ } else { uint32_t fsr =3D arm_fi_to_lfsc(&fi); =20 @@ -3255,13 +3250,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, */ if (!ret) { /* We do not set any attribute bits in the PAR */ - if (page_size =3D=3D (1 << 24) + if (res.page_size =3D=3D (1 << 24) && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (phys_addr & 0xff000000) | (1 << 1); + par64 =3D (res.phys & 0xff000000) | (1 << 1); } else { - par64 =3D phys_addr & 0xfffff000; + par64 =3D res.phys & 0xfffff000; } - if (!attrs.secure) { + if (!res.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } } else { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 308610f6b4..84c6796b8d 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -183,19 +183,14 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t add= r, uint32_t value, { CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; + GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; =20 - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { if (mode =3D=3D STACK_LAZYFP) { @@ -228,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, } goto pend_fault; } - address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value, - attrs, &txres); + address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value, + res.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to write the data */ if (mode =3D=3D STACK_LAZYFP) { @@ -276,20 +271,15 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *des= t, uint32_t addr, { CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; + GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; uint32_t value; =20 - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -308,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, goto pend_fault; } =20 - value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, + res.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); @@ -2008,13 +1998,9 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUId= x mmu_idx, CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; V8M_SAttributes sattrs =3D {}; - MemTxAttrs attrs =3D {}; + GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; =20 v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); if (!sattrs.nsc || sattrs.ns) { @@ -2028,16 +2014,15 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUI= dx mmu_idx, "...really SecureFault with SFSR.INVEP\n"); return false; } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &res, &fi)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); return false; } - *insn =3D address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); + *insn =3D address_space_lduw_le(arm_addressspace(cs, res.attrs), res.p= hys, + res.attrs, &txres); if (txres !=3D MEMTX_OK) { env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); @@ -2060,17 +2045,12 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARM= MMUIdx mmu_idx, */ CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; + GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; uint32_t value; =20 - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi)) { /* MPU/SAU lookup failed */ if (fi.type =3D=3D ARMFault_QEMU_SFault) { qemu_log_mask(CPU_LOG_INT, @@ -2088,8 +2068,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, } return false; } - value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, + res.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3261039d93..8db2abac01 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2300,18 +2300,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, * @address: virtual address to get physical address for * @access_type: 0 for read, 1 for write, 2 for execute * @mmu_idx: MMU index indicating required translation regime - * @phys_ptr: set to the physical address corresponding to the virtual add= ress - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size: set to the size of the page containing phys_ptr + * @result: set on translation success. * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); =20 @@ -2322,43 +2316,54 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, */ if (arm_feature(env, ARM_FEATURE_EL2)) { hwaddr ipa; - int s2_prot; + int s1_prot; int ret; bool ipa_secure; - ARMCacheAttrs cacheattrs2 =3D {}; + ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; =20 - ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, &= ipa, - attrs, prot, page_size, fi, cacheattrs); + ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, + result, fi); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { - *phys_ptr =3D ipa; return ret; } =20 - ipa_secure =3D attrs->secure; + ipa =3D result->phys; + ipa_secure =3D result->attrs.secure; if (arm_is_secure_below_el3(env)) { if (ipa_secure) { - attrs->secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); + result->attrs.secure =3D !(env->cp15.vstcr_el2 & VSTCR= _SW); } else { - attrs->secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); + result->attrs.secure =3D !(env->cp15.vtcr_el2 & VTCR_N= SW); } } else { assert(!ipa_secure); } =20 - s2_mmu_idx =3D attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_= Stage2; + s2_mmu_idx =3D (result->attrs.secure + ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; =20 - /* S1 is done. Now do S2 translation. */ + /* + * S1 is done, now do S2 translation. + * Save the stage1 results so that we may merge + * prot and cacheattrs later. + */ + s1_prot =3D result->prot; + cacheattrs1 =3D result->cacheattrs; + memset(result, 0, sizeof(*result)); + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, - phys_ptr, attrs, &s2_prot, - page_size, fi, &cacheattrs2); + &result->phys, &result->attrs, + &result->prot, &result->page_size, + fi, &result->cacheattrs); fi->s2addr =3D ipa; + /* Combine the S1 and S2 perms. */ - *prot &=3D s2_prot; + result->prot &=3D s1_prot; =20 /* If S2 fails, return early. */ if (ret) { @@ -2374,20 +2379,21 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, * Outer Write-Back Read-Allocate Write-Allocate. * Do not overwrite Tagged within attrs. */ - if (cacheattrs->attrs !=3D 0xf0) { - cacheattrs->attrs =3D 0xff; + if (cacheattrs1.attrs !=3D 0xf0) { + cacheattrs1.attrs =3D 0xff; } - cacheattrs->shareability =3D 0; + cacheattrs1.shareability =3D 0; } - *cacheattrs =3D combine_cacheattrs(env, *cacheattrs, cacheattr= s2); + result->cacheattrs =3D combine_cacheattrs(env, cacheattrs1, + result->cacheattrs); =20 /* Check if IPA translates to secure or non-secure PA space. */ if (arm_is_secure_below_el3(env)) { if (ipa_secure) { - attrs->secure =3D + result->attrs.secure =3D !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); } else { - attrs->secure =3D + result->attrs.secure =3D !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } @@ -2406,8 +2412,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - attrs->secure =3D regime_is_secure(env, mmu_idx); - attrs->user =3D regime_is_user(env, mmu_idx); + result->attrs.secure =3D regime_is_secure(env, mmu_idx); + result->attrs.user =3D regime_is_user(env, mmu_idx); =20 /* * Fast Context Switch Extension. This doesn't exist at all in v8. @@ -2424,20 +2430,22 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, =20 if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; - *page_size =3D TARGET_PAGE_SIZE; + result->page_size =3D TARGET_PAGE_SIZE; =20 if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - phys_ptr, attrs, prot, page_size, f= i); + &result->phys, &result->attrs, + &result->prot, &result->page_size, = fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, - phys_ptr, prot, page_size, fi); + &result->phys, &result->prot, + &result->page_size, fi); } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, - phys_ptr, prot, fi); + &result->phys, &result->prot, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -2445,9 +2453,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", - *prot & PAGE_READ ? 'r' : '-', - *prot & PAGE_WRITE ? 'w' : '-', - *prot & PAGE_EXEC ? 'x' : '-'); + result->prot & PAGE_READ ? 'r' : '-', + result->prot & PAGE_WRITE ? 'w' : '-', + result->prot & PAGE_EXEC ? 'x' : '-'); =20 return ret; } @@ -2492,14 +2500,14 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, address =3D extract64(address, 0, 52); } } - *phys_ptr =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - *page_size =3D TARGET_PAGE_SIZE; + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size =3D TARGET_PAGE_SIZE; =20 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ hcr =3D arm_hcr_el2_eff(env); - cacheattrs->shareability =3D 0; - cacheattrs->is_s2_format =3D false; + result->cacheattrs.shareability =3D 0; + result->cacheattrs.is_s2_format =3D false; if (hcr & HCR_DC) { if (hcr & HCR_DCT) { memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ @@ -2512,24 +2520,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, } else { memattr =3D 0x44; /* Normal, NC, No */ } - cacheattrs->shareability =3D 2; /* outer sharable */ + result->cacheattrs.shareability =3D 2; /* outer sharable */ } else { memattr =3D 0x00; /* Device, nGnRnE */ } - cacheattrs->attrs =3D memattr; + result->cacheattrs.attrs =3D memattr; return 0; } =20 if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - phys_ptr, attrs, prot, page_size, - fi, cacheattrs); + &result->phys, &result->attrs, + &result->prot, &result->page_size, + fi, &result->cacheattrs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); + &result->phys, &result->attrs, + &result->prot, &result->page_size, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - phys_ptr, prot, page_size, fi); + &result->phys, &result->prot, + &result->page_size, fi); } } =20 @@ -2538,21 +2549,16 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - bool ret; + GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - ARMCacheAttrs cacheattrs =3D {}; + bool ret; =20 - *attrs =3D (MemTxAttrs) {}; - - ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fi, &cacheattrs); + ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); + *attrs =3D res.attrs; =20 if (ret) { return -1; } - return phys_addr; + return res.phys; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 5a709eab56..ad225b1cb2 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -209,11 +209,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, { ARMCPU *cpu =3D ARM_CPU(cs); ARMMMUFaultInfo fi =3D {}; - hwaddr phys_addr; - target_ulong page_size; - int prot, ret; - MemTxAttrs attrs =3D {}; - ARMCacheAttrs cacheattrs =3D {}; + GetPhysAddrResult res =3D {}; + int ret; =20 /* * Walk the page table and (if the mapping exists) add the page @@ -223,25 +220,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, */ ret =3D get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &phys_addr, &attrs, &prot, &page_size, - &fi, &cacheattrs); + &res, &fi); if (likely(!ret)) { /* * Map a single [sub]page. Regions smaller than our declared * target page size are handled specially, so for those we * pass in the exact addresses. */ - if (page_size >=3D TARGET_PAGE_SIZE) { - phys_addr &=3D TARGET_PAGE_MASK; + if (res.page_size >=3D TARGET_PAGE_SIZE) { + res.phys &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } /* Notice and record tagged memory. */ - if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { - arm_tlb_mte_tagged(&attrs) =3D true; + if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { + arm_tlb_mte_tagged(&res.attrs) =3D true; } =20 - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, address, res.phys, res.attrs, + res.prot, mmu_idx, res.page_size); return true; } else if (probe) { return false; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661184915; cv=none; d=zohomail.com; s=zohoarc; b=GLq2O/kSVRaPguWIYIVykr9RkTcPlEYy/hkPZr9SIKrx0VdwmeGMc9sVKcxeYdKrr5sqQWJkg94y/IropMVrXxOcB9FTM08oGZWzM7HIPSw+I50oQCwALRtLukupElCxrSqECcCiBeDfZpjrX5SPqPu94varwJU4KJjXLyn7VsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661184915; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RTuC78nAmKRpy6AilqJ6/PXnPW0S1OBfJlreo9tIjlo=; b=MR0WBT9rpfbJpyqlbkzozmLqnfwMiSAMYbwhGuk4tHnSZQr/ZjhSfMx3sTnUYhnLP6r1SFC0EyLXBsJJNfhX/fnByfMdu2ZI9vDLFMSn9+VBNel74b2ShfagA2QPudfppbpnuh0WnrrJBYBAnotOE6zZ0yvDC+kUcoNgEqP0QWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661184915520845.7530920402728; Mon, 22 Aug 2022 09:15:15 -0700 (PDT) Received: from localhost ([::1]:33366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQA52-0001EQ-Oh for importer@patchew.org; Mon, 22 Aug 2022 12:15:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9L9-00070X-SS for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:47 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:35595) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9L7-0000eJ-D6 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:47 -0400 Received: by mail-pf1-x433.google.com with SMTP id 67so2481793pfv.2 for ; Mon, 22 Aug 2022 08:27:45 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=RTuC78nAmKRpy6AilqJ6/PXnPW0S1OBfJlreo9tIjlo=; b=DdWh6jghg6sPIZt5dYG1EFyZ9PFXE9H5lHaiNcFThNTuPrnpgd7ODCz574q8+s3+QZ 3Kqeh4TFT5HYLc5HYsjiQFi8T7A2hMRGn1H1B7wnHr7lXTV+dInGi5O4/ahCSypuO73J wrCxYCNhcb13HuhNZAZB7nuKG5giAf2librZI0y/ORJU7j34eF6Th6qk17XtyqXk5yd6 3xjWuPj2KTV0q+iU5rtney3SBOHUcAB4DZs9BgYI1hWAOywhizh3NVd65apx6a+XY2tQ A+FS0PQhIjfQVqSJElJKBfGVB2gmq517tmYObUMyiMSjuegJFP56t9cwpwQoU25EPoz6 IXZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=RTuC78nAmKRpy6AilqJ6/PXnPW0S1OBfJlreo9tIjlo=; b=GpM0RUkNiUKrtCuPfj+HyBB27uJafqrQbgAmU0Vm2MCPxcLvcm2YopxvR9s0aEPlLK XX1eRBwdLYGDkhARGK5/VZ6eljzThcghYSOymikQhVULegbpwvvGcqjQ2FDC6ECDUWnM pov+VbrTCZ1m9oLhcST7IUNSBThAUtkBuA3gqwLwm8oXTjpb7iZKl4h3UJd8YwvWdTM3 JzKwB48e+2BsrJlFh9T6yXH2T9bxXm95uPjE05tvuMSCFVpMNDHCUW6u8V8Wn/VRTxwC uNETAWOgprS+/TcriGTBsTXFXK44hFg2GF5xjstuRoNnvc0p2IcL1tH8ufRqOS6W14V4 otTA== X-Gm-Message-State: ACgBeo2xFor9tdenssRnTFJExY/uWpG9xFRg6WIsQ2HShXm+NAt2NzRi +FLaS/YcDW4yW6n0XISRXYnTX8C3anpO2A== X-Google-Smtp-Source: AA6agR4ykeEDAYALFYuUCaEm6nH3l7ISJ4+xefPDyODgMpfJ0omd/4/joXzVf1Mlg4HBxAmtsQRVxQ== X-Received: by 2002:a62:be0e:0:b0:536:76fe:ee96 with SMTP id l14-20020a62be0e000000b0053676feee96mr6999547pff.44.1661182064127; Mon, 22 Aug 2022 08:27:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 02/66] target/arm: Fix ipa_secure in get_phys_addr Date: Mon, 22 Aug 2022 08:26:37 -0700 Message-Id: <20220822152741.1617527-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661184915976100001 Content-Type: text/plain; charset="utf-8" The starting security state comes with the translation regime, not the current state of arm_is_secure_below_el3(). More use of the local variable, ipa_secure, which does not need to be written back to result->attrs.secure -- we compute that value later, after the S2 walk is complete. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8db2abac01..478ff74550 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2308,6 +2308,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); + bool is_secure =3D regime_is_secure(env, mmu_idx); =20 if (mmu_idx !=3D s1_mmu_idx) { /* @@ -2332,19 +2333,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, } =20 ipa =3D result->phys; - ipa_secure =3D result->attrs.secure; - if (arm_is_secure_below_el3(env)) { - if (ipa_secure) { - result->attrs.secure =3D !(env->cp15.vstcr_el2 & VSTCR= _SW); - } else { - result->attrs.secure =3D !(env->cp15.vtcr_el2 & VTCR_N= SW); - } + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + ipa_secure =3D !(result->attrs.secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); } else { - assert(!ipa_secure); + ipa_secure =3D false; } =20 - s2_mmu_idx =3D (result->attrs.secure - ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + s2_mmu_idx =3D (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2); is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; =20 /* @@ -2388,7 +2386,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result->cacheattrs); =20 /* Check if IPA translates to secure or non-secure PA space. */ - if (arm_is_secure_below_el3(env)) { + if (is_secure) { if (ipa_secure) { result->attrs.secure =3D !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); @@ -2412,7 +2410,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - result->attrs.secure =3D regime_is_secure(env, mmu_idx); + result->attrs.secure =3D is_secure; result->attrs.user =3D regime_is_user(env, mmu_idx); =20 /* --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183187; cv=none; d=zohomail.com; s=zohoarc; b=eAC53KaP3s/szruBmmTVzdZrqFvzsA9Z1u2wllwQNXMZSHqC+RFMVCJcs046HDYxeARI3GTXHj8UwCeAH7s9bBXLilHQPBorNJHb5W7EtfrkgYhWTF5CZ2lZBbPK+HPNh91zQRJeg3IlUvYwkLLcpOkK7VZ60zxMUxnMr08AjUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661183187; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Kjbrp5bm88e/qRtLpUBYrca0xBOcPN6yN6kx+yhAThA=; b=NqQokBjoU3KxUjWIRqtoVLdfrlVFS4yjg8kSQGFP4HYMZfjo0+Hs89q7hMobEH71LcY7UTk+15hKG/4Sl/1yXCepILTCGpU9sfwfQ6pPbcHTtGr3DZNrZBpF4llhq3enInlQ2NKl0/JjrZWsGOY6UfHL8evtDYazprL9Gc4uw10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661183187091161.70330957109798; Mon, 22 Aug 2022 08:46:27 -0700 (PDT) Received: from localhost ([::1]:55738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9dB-000863-RI for importer@patchew.org; Mon, 22 Aug 2022 11:46:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LB-00074c-Sf for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:49 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:38823) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9L8-0000eb-Qr for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:49 -0400 Received: by mail-pg1-x52e.google.com with SMTP id r22so9683749pgm.5 for ; Mon, 22 Aug 2022 08:27:46 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Kjbrp5bm88e/qRtLpUBYrca0xBOcPN6yN6kx+yhAThA=; b=DREKFKYZl1UJY36X8M9Cl/P1svJo84mNYRgBWGyv9cdspIm80gQTwdVIx2H1bn9bHZ QLyXvWMRevyHNuBVol1BQrO5T0ECxkegZ+FRkEaeUBBvyBb1ryKqva8cczZ1V2hEBCYi soGE8zv+1Vb7iL640wo2dT6xzG61b2zDuWoTjBoU6ZxLVoacp5WlNi2mWGOhoLtDQ34a 1WvoYzV+NNWMMO/kj0Uq18M6NdI8nCLUy5XvRwvICDmC0Lvpgxt2ThxJupVux4Xls7F2 Lr8Z5ZDQsd5BUrPr5WDKMSw4KWxJdPlYJK5kJFDwVZ1YUeFuHmgkQ0TZZHQyyCvkC6yY r2QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Kjbrp5bm88e/qRtLpUBYrca0xBOcPN6yN6kx+yhAThA=; b=pM3t5U42BTBF1XHicjUlq2Ed8wpUd79Pl40Y8gnnBsZM3AjtZYfY7VnU6WU4PmRnol J0h51WME9Sa0VcEhNRTHjhnQyWESAwlBiYMNpnSsExJDDTcRQPI2IlJKwmgE0wCZASKt cvREeT8Z1m8jD1I+4Aa4QYpHOYl0V+owytp5tFhOLjRXQWYhfqizP5WtdT9s+VuB3OsS DHRKd0LT+L7DuFVcHwvh0Xf29sf0LrcawjAUk4UnYqmpW9OEO4sCJi09BSrc8UHrs+2e E6lS7FsPXRjBGgvRXJB/Hs0ILUPJYpiU7zTiZBGHa9SjTICsZio+veOJYA4K2yg4ACpt 6wUw== X-Gm-Message-State: ACgBeo1Ae2uVooPgGEMsAo2xBVX6oHY45xgWRnYZoclw2jAjKhVfTblt Y75Hpgp7n+DdASLhIgxiVVprkrwXjnEqwQ== X-Google-Smtp-Source: AA6agR59z9Q+MtDcNwNIcFpHRXL11MQmxlsy5sUM8hnm7dhdX4gv0k8vb4/JqscztZiXXeI7lsw6VQ== X-Received: by 2002:aa7:9731:0:b0:536:7b04:acb6 with SMTP id k17-20020aa79731000000b005367b04acb6mr7841997pfg.43.1661182065230; Mon, 22 Aug 2022 08:27:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 03/66] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Date: Mon, 22 Aug 2022 08:26:38 -0700 Message-Id: <20220822152741.1617527-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183188464100001 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 69 ++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 43 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 478ff74550..4f248f6266 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,10 +16,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, hwaddr *phys_ptr, - MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) + bool s1_is_el0, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ @@ -204,18 +202,13 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - target_ulong s2size; - hwaddr s2pa; - int s2prot; - int ret; ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ARMCacheAttrs cacheattrs =3D {}; - MemTxAttrs txattrs =3D {}; + GetPhysAddrResult s2 =3D {}; + int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, - &s2pa, &txattrs, &s2prot, &s2size, fi, - &cacheattrs); + &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; @@ -225,7 +218,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, cacheattrs)) { + ptw_attrs_are_device(env, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -249,7 +242,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, assert(!*is_secure); } =20 - addr =3D s2pa; + addr =3D s2.phys; } return addr; } @@ -972,19 +965,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_a= a64, int level, * table walk), must be true if this is stage 2 of a stage 1+2 * walk for an EL0 access. If @mmu_idx is anything else, * @s1_is_el0 is ignored. - * @phys_ptr: set to the physical address corresponding to the virtual add= ress - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size_ptr: set to the size of the page containing phys_ptr + * @result: set on translation success, * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, hwaddr *phys_ptr, - MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) + bool s1_is_el0, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1302,16 +1289,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; xn =3D extract32(attrs, 11, 2); - *prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { ns =3D extract32(attrs, 3, 1); xn =3D extract32(attrs, 12, 1); pxn =3D extract32(attrs, 11, 1); - *prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); } =20 fault_type =3D ARMFault_Permission; - if (!(*prot & (1 << access_type))) { + if (!(result->prot & (1 << access_type))) { goto do_fault; } =20 @@ -1321,23 +1308,23 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - txattrs->secure =3D false; + result->attrs.secure =3D false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(txattrs) =3D true; + arm_tlb_bti_gp(&result->attrs) =3D true; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { - cacheattrs->is_s2_format =3D true; - cacheattrs->attrs =3D extract32(attrs, 0, 4); + result->cacheattrs.is_s2_format =3D true; + result->cacheattrs.attrs =3D extract32(attrs, 0, 4); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx =3D extract32(attrs, 0, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); - cacheattrs->is_s2_format =3D false; - cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); } =20 /* @@ -1346,13 +1333,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * that case comes from TCR_ELx, which we extracted earlier. */ if (param.ds) { - cacheattrs->shareability =3D param.sh; + result->cacheattrs.shareability =3D param.sh; } else { - cacheattrs->shareability =3D extract32(attrs, 6, 2); + result->cacheattrs.shareability =3D extract32(attrs, 6, 2); } =20 - *phys_ptr =3D descaddr; - *page_size_ptr =3D page_size; + result->phys =3D descaddr; + result->page_size =3D page_size; return false; =20 do_fault: @@ -2354,10 +2341,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, - &result->phys, &result->attrs, - &result->prot, &result->page_size, - fi, &result->cacheattrs); + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + is_el0, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2528,9 +2513,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - &result->phys, &result->attrs, - &result->prot, &result->page_size, - fi, &result->cacheattrs); + result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, &result->phys, &result->attrs, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661182357; cv=none; d=zohomail.com; s=zohoarc; b=T/wwYNwKrJn9t1duxqRXumXsQSpzGsfMb/wjzMgR5YDSOUvDqBvg6XS0/AtJS0pIH8c0dc8rb3tVgsDQGlAaoGod2ppTOvsE5XT/kuc24DS6/EA8/6m36pNDfh7+wfoelw+bMvWvOSqPH9XXiFCO/IEnOvuG0n/W4X8t31G2z80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661182357; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661182358934100001 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4f248f6266..4961bc2f9f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -536,8 +536,7 @@ do_fault: =20 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, - target_ulong *page_size, ARMMMUFaultInfo *fi) + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; @@ -597,11 +596,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - *page_size =3D 0x1000000; + result->page_size =3D 0x1000000; } else { /* Section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - *page_size =3D 0x100000; + result->page_size =3D 0x100000; } ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); @@ -627,12 +626,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); xn =3D desc & (1 << 15); - *page_size =3D 0x10000; + result->page_size =3D 0x10000; break; case 2: case 3: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); xn =3D desc & 1; - *page_size =3D 0x1000; + result->page_size =3D 0x1000; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -640,7 +639,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, } } if (domain_prot =3D=3D 3) { - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; @@ -658,14 +657,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, fi->type =3D ARMFault_AccessFlag; goto do_fault; } - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); } - if (*prot && !xn) { - *prot |=3D PAGE_EXEC; + if (result->prot && !xn) { + result->prot |=3D PAGE_EXEC; } - if (!(*prot & (1 << access_type))) { + if (!(result->prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -676,9 +675,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - attrs->secure =3D false; + result->attrs.secure =3D false; } - *phys_ptr =3D phys_addr; + result->phys =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -2516,8 +2515,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - &result->phys, &result->attrs, - &result->prot, &result->page_size, fi); + result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, &result->phys, &result->prot, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183503; cv=none; d=zohomail.com; s=zohoarc; b=QAz9XNSApRqG1rLB2ezB4zdPUwvQFRXMT/322J4/0oExHsA9ncrRClqmKiDDmRZifNIX9cLyuRPzgT1YaO7Hhbj/F6a12NZ8x1qCSKJqq/GY1d8Thk/2rfIXCpEyFDxjfP7WX+oXsAdzhUJsrInhpIu/utW8eBf9HH4lJmbW9pQ= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183503600100001 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4961bc2f9f..b006e87a63 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -414,9 +414,7 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMM= UIdx mmu_idx, int ap) =20 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { int level =3D 1; uint32_t table; @@ -464,7 +462,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* 1Mb section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); ap =3D (desc >> 10) & 3; - *page_size =3D 1024 * 1024; + result->page_size =3D 1024 * 1024; } else { /* Lookup l2 entry. */ if (type =3D=3D 1) { @@ -486,12 +484,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - *page_size =3D 0x10000; + result->page_size =3D 0x10000; break; case 2: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - *page_size =3D 0x1000; + result->page_size =3D 0x1000; break; case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ if (type =3D=3D 1) { @@ -499,7 +497,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, if (arm_feature(env, ARM_FEATURE_XSCALE) || arm_feature(env, ARM_FEATURE_V6)) { phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - *page_size =3D 0x1000; + result->page_size =3D 0x1000; } else { /* * UNPREDICTABLE in ARMv5; we choose to take a @@ -510,7 +508,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, } } else { phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - *page_size =3D 0x400; + result->page_size =3D 0x400; } ap =3D (desc >> 4) & 3; break; @@ -519,14 +517,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, g_assert_not_reached(); } } - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - *prot |=3D *prot ? PAGE_EXEC : 0; - if (!(*prot & (1 << access_type))) { + result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->prot |=3D result->prot ? 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661182870171100001 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b006e87a63..15d152432f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1351,7 +1351,7 @@ do_fault: =20 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, int *prot, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; @@ -1361,12 +1361,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled. */ - *phys_ptr =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } =20 - *phys_ptr =3D address; + result->phys =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; if ((base & 1) =3D=3D 0) { @@ -1402,16 +1402,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - *prot =3D PAGE_READ | PAGE_WRITE; + result->prot =3D PAGE_READ | PAGE_WRITE; break; case 2: - *prot =3D PAGE_READ; + result->prot =3D PAGE_READ; if (!is_user) { - *prot |=3D PAGE_WRITE; + result->prot |=3D PAGE_WRITE; } break; case 3: - *prot =3D PAGE_READ | PAGE_WRITE; + result->prot =3D PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1419,10 +1419,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - *prot =3D PAGE_READ; + result->prot =3D PAGE_READ; break; case 6: - *prot =3D PAGE_READ; + result->prot =3D PAGE_READ; break; default: /* Bad permission. */ @@ -1430,7 +1430,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, ui= nt32_t address, fi->level =3D 1; return true; } - *prot |=3D PAGE_EXEC; + result->prot |=3D PAGE_EXEC; return false; } =20 @@ -2425,7 +2425,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, - &result->phys, &result->prot, fi); + result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661185709861100001 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 15d152432f..3dd6708eee 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1513,17 +1513,16 @@ static bool pmsav7_use_background_region(ARMCPU *cp= u, ARMMMUIdx mmu_idx, =20 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D env_archcpu(env); int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 - *phys_ptr =3D address; - *page_size =3D TARGET_PAGE_SIZE; - *prot =3D 0; + result->phys =3D address; + result->page_size =3D TARGET_PAGE_SIZE; + result->prot =3D 0; =20 if (regime_translation_disabled(env, mmu_idx) || m_is_ppb_region(env, address)) { @@ -1535,7 +1534,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, * which always does a direct read using address_space_ldl(), rath= er * than going via this function, so we don't need to check that he= re. */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ @@ -1577,7 +1576,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, if (ranges_overlap(base, rmask, address & TARGET_PAGE_MASK, TARGET_PAGE_SIZE)) { - *page_size =3D 1; + result->page_size =3D 1; } continue; } @@ -1615,7 +1614,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, continue; } if (rsize < TARGET_PAGE_BITS) { - *page_size =3D 1 << rsize; + result->page_size =3D 1 << rsize; } break; } @@ -1626,7 +1625,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, fi->type =3D ARMFault_Background; return true; } - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->p= rot); } else { /* a MPU hit! */ uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); @@ -1643,16 +1642,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 5: break; /* no access */ case 3: - *prot |=3D PAGE_WRITE; + result->prot |=3D PAGE_WRITE; /* fall through */ case 2: case 6: - *prot |=3D PAGE_READ | PAGE_EXEC; + result->prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - *prot |=3D PAGE_READ | PAGE_EXEC; + result->prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1668,16 +1667,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 1: case 2: case 3: - *prot |=3D PAGE_WRITE; + result->prot |=3D PAGE_WRITE; /* fall through */ case 5: case 6: - *prot |=3D PAGE_READ | PAGE_EXEC; + result->prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - *prot |=3D PAGE_READ | PAGE_EXEC; + result->prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1690,14 +1689,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 /* execute never */ if (xn) { - *prot &=3D ~PAGE_EXEC; + result->prot &=3D ~PAGE_EXEC; } } } =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(*prot & (1 << access_type)); + return !(result->prot & (1 << access_type)); } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, @@ -2420,8 +2419,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, - &result->phys, &result->prot, - &result->page_size, fi); + result, fi); } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186813; cv=none; d=zohomail.com; s=zohoarc; b=U51YEWpDmcULrtEciQcbP4Fj6HRRpbAV4CtZRYCdx6IEkd9tAXGy92/yWydUHSZnFEz5Wv/lYkXXgwtODPVbJb+BBm4t0BXtCEwuAwNhAvM2XeYc7RHqdtTVhD9O11bSH9ogcCDylkh3XyLZQPCxxjfdTOx6FBP/D+A8bhSmqnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186813; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J9NKDua5mjCfaRrViIxkitiohmvoSvAqzV9syZybY5w=; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=J9NKDua5mjCfaRrViIxkitiohmvoSvAqzV9syZybY5w=; b=ys4tnb7KNFr9y4Jp2QDvFBy0no4nD1ZKcUgXYoxVUGPc4khNK1ZE7mUA/ABGhczfQF V9n7VSzZ3hQZHblw3nthVDO4/tkxbxCLIC8w+xxa/kqZFmTaQsYyr/BogaLIVc8y3uSG 55RY1aBcAmn4Zpy8TZIapnF7ResxzAKaL0Wzx1y9YOERFEwmUEZSc+g0F61ezlRIxC7l nq6EilMuPM524RFQVDZSn+MvqIdaAdXZBpBzJZSWPLKG8BfaHkPqqMgBweVylVduuz9l i2ZIWgLXN0yuMA6EMHzmVL7xdAe9uTk0cM+ZPqgRJh8snIsxIJoicKOueRwbQHNAlAin 53YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=J9NKDua5mjCfaRrViIxkitiohmvoSvAqzV9syZybY5w=; b=sY7cD0PQdlYrbRGqMyEo/MZOilg+gWnqGHiPPE89beoqAyNy+H30TNoyXGD1qOVQYa rLhkxc5KS/YxGFm0bvMwPAxoC++3HAdbP9TGgzt5PXitZyKbS5HyG/YFccAvQxNlPl4Q DhqxmYnMubUYzJHFW0MIna4Z8L9cQ2PeeUnBSljq5kCsaxwhSFexHgHUSkFEmpVyWMfT tKv5P+rPAlOvKraUWGe8mquzsY6dXdV0eHeHW6DTFZOnmz991eO60JcfpMZaFJbaK+p7 6awHdRo5ppnJ7UghNL2ztgePvTsAaGzA+d5m4BGztufKMydGOYXbTuQbfadolx0de1WL SGVA== X-Gm-Message-State: ACgBeo0omDFEo5WI3J+YxCP/hOstBzrXEF4jscQBmgrI1fBnLiHPsHG0 kh2MdbiLdWCIUsHE+ppUr287lHXOHozGGw== X-Google-Smtp-Source: AA6agR7eylNrQ+mnQ/XK62i/vXlBRmYvUmXJNqaxQykuzqoAN68xuAqA8DdWTHqmJg7bAbRNHJgOHA== X-Received: by 2002:a05:6a00:2789:b0:531:c43:6290 with SMTP id bd9-20020a056a00278900b005310c436290mr21269140pfb.21.1661182069096; Mon, 22 Aug 2022 08:27:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 08/66] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Date: Mon, 22 Aug 2022 08:26:43 -0700 Message-Id: <20220822152741.1617527-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186815730100002 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3dd6708eee..225405de3b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1967,8 +1967,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t a= ddress, =20 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, target_ulong *page_size, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { uint32_t secure =3D regime_is_secure(env, mmu_idx); @@ -2003,9 +2002,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } else { fi->type =3D ARMFault_QEMU_SFault; } - *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr =3D address; - *prot =3D 0; + result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; + result->phys =3D address; + result->prot =3D 0; return true; } } else { @@ -2015,7 +2014,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { - txattrs->secure =3D false; + result->attrs.secure =3D false; } else if (!secure) { /* * NS access to S memory must fault. @@ -2028,17 +2027,19 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type =3D ARMFault_QEMU_SFault; - *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr =3D address; - *prot =3D 0; + result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; + result->phys =3D address; + result->prot =3D 0; return true; } } } =20 - ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); - *page_size =3D sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, + &result->phys, &result->attrs, &result->prot, + &mpu_is_subpage, fi, NULL); + result->page_size =3D + sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } =20 @@ -2414,8 +2415,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - &result->phys, &result->attrs, - &result->prot, &result->page_size, = fi); + result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183264; cv=none; d=zohomail.com; s=zohoarc; b=VmxrekjtU8esv0bqBzPPypsTIgWBrSOOCSlitSok++PBuZB7/zR7pLol7nSzfysE55ZXWrBvVZOfVHKvgKOT1woyoeuQOhLhT48vMCGv0QD2uw+tvnqfKLxC5XhQN8/0dQCV725zOAMW8CBYjDCkMgLnhw47kD31L9E8kZDR7lc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661183264; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5p0MI+QCkoFG04riom6naP42FW0W2gy0tzxTYjzHV/c=; b=VLpp7z0AAOEounU1VaXbVBFXbTPLmpL5vRUdELl+65lsEIiw30rAX3jM4UAxzIgbKRVFxA3hPpsuicUdE/adFFczCYGRA3WI4pYe+ZMLmcejxftJF/bUxxxoC4IF1FvYRJOg9gvLZM1rdo+0m9ON/QNqRn+MMaKVCDyE9p96Nj0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661183264308330.0589155846211; Mon, 22 Aug 2022 08:47:44 -0700 (PDT) Received: from localhost ([::1]:39924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9eR-0001Xz-01 for importer@patchew.org; Mon, 22 Aug 2022 11:47:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33300) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LJ-0007KN-5W for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:57 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:39586) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LE-0000h4-Fk for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:56 -0400 Received: by mail-pg1-x52e.google.com with SMTP id q9so629313pgq.6 for ; Mon, 22 Aug 2022 08:27:51 -0700 (PDT) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183264674100001 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 11 +++++------ target/arm/m_helper.c | 16 +++++++--------- target/arm/ptw.c | 20 +++++++++----------- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 293e27b996..6786e08a78 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1125,12 +1125,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t = address, MMUAccessType access_type, ARMMMUIdx mmu_idx, V8M_SAttributes *sattrs); =20 -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); - /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { /* @@ -1156,6 +1150,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion); + void arm_log_exception(CPUState *cs); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 84c6796b8d..69d4a63fa6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2770,15 +2770,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) V8M_SAttributes sattrs =3D {}; uint32_t tt_resp; bool r, rw, nsr, nsrw, mrvalid; - int prot; - ARMMMUFaultInfo fi =3D {}; - MemTxAttrs attrs =3D {}; - hwaddr phys_addr; ARMMMUIdx mmu_idx; uint32_t mregion; bool targetpriv; bool targetsec =3D env->v7m.secure; - bool is_subpage; =20 /* * Work out what the security state and privilege level we're @@ -2809,18 +2804,21 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) !=3D 0 || alt) { + GetPhysAddrResult res =3D {}; + ARMMMUFaultInfo fi =3D {}; + bool is_subpage; + /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &phys_addr, &attrs, &prot, &is_subpage, - &fi, &mregion); + &res, &is_subpage, &fi, &mregion); if (mregion =3D=3D -1) { mrvalid =3D false; mregion =3D 0; } else { mrvalid =3D true; } - r =3D prot & PAGE_READ; - rw =3D prot & PAGE_WRITE; + r =3D res.prot & PAGE_READ; + rw =3D res.prot & PAGE_WRITE; } else { r =3D false; rw =3D false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 225405de3b..48c9363159 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1701,8 +1701,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, + GetPhysAddrResult *result, bool *is_subpage, ARMMMUFaultInfo *fi, uint32_t *mregion) { /* @@ -1724,8 +1723,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 *is_subpage =3D false; - *phys_ptr =3D address; - *prot =3D 0; + result->phys =3D address; + result->prot =3D 0; if (mregion) { *mregion =3D -1; } @@ -1807,7 +1806,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); @@ -1822,9 +1821,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn && !(pxn && !is_user)) { - *prot |=3D PAGE_EXEC; + result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (result->prot && !xn && !(pxn && !is_user)) { + result->prot |=3D PAGE_EXEC; } /* * We don't need to look the attribute up in the MAIR0/MAIR1 @@ -1837,7 +1836,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(*prot & (1 << access_type)); + return !(result->prot & (1 << access_type)); } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2036,8 +2035,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } =20 ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, - &result->phys, &result->attrs, &result->prot, - &mpu_is_subpage, fi, NULL); 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=KQgnmJmdBnU/p9031agTMRXsX9duSik3VaZXmB+O4Tc=; b=tKaCPwZ169NkHNwnExeSmdk9iFrMlcgTKfMpwM7GdtmWLRDxaNY9jHcIlNFlCf8Uin Y+Q4dUNU5m2qX9zS4BtUR2VjWCdSjH6eFg6AmOvLsxHr+3s+SmYUVAbR+HyII/Ndqg2I Xqyo8FQTsKv9tD1KztN7pTwjeBIcSNEXu7zcTwagrnIcwGLoVzCSKx4J2c3BuVQeG78Q Jm8srFWCAQ3DI04k7BtCyDBp+Z2t5AMqDPKX4ZVlnfhBlDpY4H33hGKvuyAe7l0s8cTP WhKWXXMqXc+sK9MHWjxmknUqSH0Q3dD2Jyt2JdEtmYsw/KbO1eAV39r5a5X5KK+JhWu8 Jd/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=KQgnmJmdBnU/p9031agTMRXsX9duSik3VaZXmB+O4Tc=; b=bQCWtQmMOd3QbnCrC+qacx/30aCJC9aVcyq6iQ3JcqnqrvApg6OcZTfJfZKRIVD/5Y TYgIAxAzi6/V3wl8zzKRmDMHBy+1b/JXdBTznhHlIjcqyWCsqNtbmysAGL4s5Ajsaq3c MFBCIWXbzOBuIOqcXzMAj0y1AFG1TBXwCraPQ1wmG3qNafJ2Y94VHVnvGPSD7R89Of7O WqU5qBc66/wkgD/0TObo2nv5aJp1zr8ZI9KPrGp/sNExzL3MX5IAtEkb1FjyzSn6McrN IwoUlVPp6XIjapKkDWnuf9T2lX/uOXVIT7dJFoPyL7GCmCvxFqMgCOwKJNIcQTNN8Buu y+kw== X-Gm-Message-State: ACgBeo2SO9VS6tHXR9DXC2xbhUt2EjpfQFBXKrs9BY84ASECTTVc8Ocx 1ZVJBMip3hPrJ8EITpU8aE5Z7Kh2beizwQ== X-Google-Smtp-Source: AA6agR63AUgFc4jKIVM5zkvFTqgJ0f2yFpliWXPAIF/zLk7yXZXzeC0d/FmKpSkyuGDAG7Gef2C+Tg== X-Received: by 2002:a17:903:40c9:b0:172:e8aa:96ef with SMTP id t9-20020a17090340c900b00172e8aa96efmr6154212pld.59.1661182070709; Mon, 22 Aug 2022 08:27:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 10/66] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Date: Mon, 22 Aug 2022 08:26:45 -0700 Message-Id: <20220822152741.1617527-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183594205100001 Content-Type: text/plain; charset="utf-8" This can be made redundant with result->page_size, by moving the basic set of page_size from get_phys_addr_pmsav8. We still need to overwrite page_size when v8m_security_lookup signals a subpage. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 4 ++-- target/arm/m_helper.c | 3 +-- target/arm/ptw.c | 18 +++++++++--------- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6786e08a78..fa8553a17e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1152,8 +1152,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, + uint32_t *mregion); =20 void arm_log_exception(CPUState *cs); =20 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 69d4a63fa6..01263990dc 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2806,11 +2806,10 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) if (arm_current_el(env) !=3D 0 || alt) { GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; - bool is_subpage; =20 /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &res, &is_subpage, &fi, &mregion); + &res, &fi, &mregion); if (mregion =3D=3D -1) { mrvalid =3D false; mregion =3D 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 48c9363159..ec66ba6777 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1701,8 +1701,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, + uint32_t *mregion) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1722,7 +1722,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 - *is_subpage =3D false; + result->page_size =3D TARGET_PAGE_SIZE; result->phys =3D address; result->prot =3D 0; if (mregion) { @@ -1774,13 +1774,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, ranges_overlap(base, limit - base + 1, addr_page_base, TARGET_PAGE_SIZE)) { - *is_subpage =3D true; + result->page_size =3D 1; } continue; } =20 if (base > addr_page_base || limit < addr_page_limit) { - *is_subpage =3D true; + result->page_size =3D 1; } =20 if (matchregion !=3D -1) { @@ -1972,7 +1972,6 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, uint32_t secure =3D regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs =3D {}; bool ret; - bool mpu_is_subpage; =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); @@ -2035,9 +2034,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, u= int32_t address, } =20 ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, - result, &mpu_is_subpage, fi, NULL); - result->page_size =3D - sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + result, fi, NULL); + if (sattrs.subpage) { + result->page_size =3D 1; + } return ret; } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661184519; cv=none; d=zohomail.com; s=zohoarc; b=B3daSovbwNTRGdXG1XYhBiB8zqJUS8WYOOKpN+x3950Nf/sS1rUOoAkBM/OOAfdGBBuE5tsc9CuhC5nE9Fq/7D5YhNYuZ3yAYDJoIMGUT2Kpfvayq7jxIqJrsrkispPf1f6HUT2KlV96OVCivjYLebN8N9X5xiTKu09eX5FFDn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661184519; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BWRDtrDD+OIowc2u5C+0Bs/iEHTC4XxgclrlkjL6OHk=; b=IGQMwbchlDg15HN5jRG/L5Mo8vhheCyUSaeFbYZ/ww+SKHo2T7puCEAzAuV2q/BXpNvXqd1ITQDGTTz4XRcKLCa5RXr8rrT9OYi693k43/T05lID+JVvz74E9iEKmzUOs5cfIX80w8+uO/UoTHtBQMTcC5b8M0xY+MNw0sy9ZyQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661184519767197.27380029676476; Mon, 22 Aug 2022 09:08:39 -0700 (PDT) Received: from localhost ([::1]:57722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9yf-0004qg-6f for importer@patchew.org; Mon, 22 Aug 2022 12:08:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LO-0007aa-7y for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:02 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:41955) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LG-0000hg-RP for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:01 -0400 Received: by mail-pf1-x42b.google.com with SMTP id g129so7349469pfb.8 for ; Mon, 22 Aug 2022 08:27:54 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BWRDtrDD+OIowc2u5C+0Bs/iEHTC4XxgclrlkjL6OHk=; b=jF9Ny+Dv2/w2nmx73YWnpF9y56k4nLUDp2Uk4qUriUvfuCBwIoM4Kd/42lz9L9lD+h 3LBcLwHAkjpMIvwtr6wKWD0HhLs3/euYYzGLsrFoSDAwLOxTAf6yqcQqmG1ybap+QjZV 1xgcHyKmb6lVWA8kdanMJtOL167Vmj527HZHdHcyeHV5seXYwj2Y9zMBNleoEaTm6/2s Z5l2H6bKDL0xUw1Ke3Cohop9YEzV7MM/iY5j/szKE0uydgx+EP06rib+D6PQpLq34P7z Vx0qP0M8Nno0NkICr199m4WHv0R6uFW+yBcLzw/pi72t4cJJWAfK57pM9I/0o1Rlbthr Q2Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BWRDtrDD+OIowc2u5C+0Bs/iEHTC4XxgclrlkjL6OHk=; b=WTNXklIXYb6Dv6w5VE4M/DDxjsYT7PJPc6nh7Kul/w9uQVSXvEB6anykTsD8fcqPK7 Ayl6Byu7+h3x20U5LMWLYDEvy3NZEm1efUYxNgZPJLVpsC1s5XDxtAo1pf0kM31+lqvH i/DcvykyZ0NKAFG6rldWEFlcO+C0nIJ2nvkjIL0u1m/Is4Irx4DCpJnJBs1aR6j97ZgV cJr/u7leEa6Ib7pJOGOgUG41+mSHmjrWqkVEYYcMVtGfZCjncebFT/W6fhNpAR57aCM4 RVSHgo1YJcInQWUjux08TyF2Az/NSMSCmclkCFrFaHaeRgp2Hx0nJVTBRiKNF7eESgvX kJmA== X-Gm-Message-State: ACgBeo1Hm5yv+9gSJpIpOgaULANIx1dJs5ryBggk2ERlmQA/Z7zY7iGl peCbfwDmbJNbaI1pksbXHryOkTHs25PTSg== X-Google-Smtp-Source: AA6agR7cgq5AMCgaWo46LQbmWgkt9XFNMFkSvZQ4qmBDp7VMc1pu0DlKpP+ujAeqgr/idEK56gh4jQ== X-Received: by 2002:a05:6a00:98a:b0:536:4469:12e6 with SMTP id u10-20020a056a00098a00b00536446912e6mr12705545pfg.9.1661182071497; Mon, 22 Aug 2022 08:27:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 11/66] target/arm: Add is_secure parameter to v8m_security_lookup Date: Mon, 22 Aug 2022 08:26:46 -0700 Message-Id: <20220822152741.1617527-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661184520881100001 Remove the use of regime_is_secure from v8m_security_lookup, passing the new parameter to the lookup instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 2 +- target/arm/m_helper.c | 9 ++++++--- target/arm/ptw.c | 9 +++++---- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fa8553a17e..7f3b5bb406 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1123,7 +1123,7 @@ typedef struct V8M_SAttributes { =20 void v8m_security_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - V8M_SAttributes *sattrs); + bool secure, V8M_SAttributes *sattrs); =20 /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 01263990dc..45fbf19559 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -689,7 +689,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, b= ool targets_secure, if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { V8M_SAttributes sattrs =3D {}; =20 - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); + v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + targets_secure, &sattrs); if (sattrs.ns) { attrs.secure =3D false; } else if (!targets_secure) { @@ -2002,7 +2003,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, + regime_is_secure(env, mmu_idx), &sattrs); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2826,7 +2828,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } =20 if (env->v7m.secure) { - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); + v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + targetsec, &sattrs); nsr =3D sattrs.ns && r; nsrw =3D sattrs.ns && rw; } else { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ec66ba6777..bbfb80f4dd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1856,8 +1856,8 @@ static bool v8m_is_sau_exempt(CPUARMState *env, } =20 void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_i= dx, - V8M_SAttributes *sattrs) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure, V8M_SAttributes *sattrs) { /* * Look up the security attributes for this address. Compare the @@ -1885,7 +1885,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t a= ddress, } =20 if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { - sattrs->ns =3D !regime_is_secure(env, mmu_idx); + sattrs->ns =3D !is_secure; return; } =20 @@ -1974,7 +1974,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, bool ret; =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); + v8m_security_lookup(env, address, access_type, mmu_idx, + secure, &sattrs); if (access_type =3D=3D MMU_INST_FETCH) { /* * Instruction fetches always use the MMU bank and the --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186283; cv=none; d=zohomail.com; s=zohoarc; b=dHxoE8vdCJC+CkORvlGLQwruSJa11qPGc2fLnDZqQs5TG6xjc0AHtmj5AMQxhX469aWJ9cGzqLab4N7vf1Z2WQehXm/oiyGTOpyOh72lgAtVj/hjNYeufN/Mmb/99echsX0+e3K0QdHUIWuYgL298mI6KP3wAaHqo+eEsOlagfU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186283; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6BDOSEGT0y+2WOd0fksOzxPg5dHDpE5xNyJzQhM+fiE=; b=YFmbN7pDPruyRkFoNOIIygaDtY/c+MUz/GgpVvDcuiGOBdOsXArjyjp7BlMpujR39BlFcmkTSrpfBcgHzifkoM+oCmOTajQK6jPOCc8OT+SStegy/8WXE3pZUAgrQWB4Ar9x5J35dSlYHtMSr3PMXzXghU7CFul/Y0pHLYO5eao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166118628362268.57389990029583; Mon, 22 Aug 2022 09:38:03 -0700 (PDT) Received: from localhost ([::1]:51050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAR8-0008Il-26 for importer@patchew.org; Mon, 22 Aug 2022 12:38:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33306) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LK-0007PD-JS for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:58 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:40678) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LF-0000hz-KU for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:27:58 -0400 Received: by mail-pg1-x531.google.com with SMTP id w13so4594318pgq.7 for ; Mon, 22 Aug 2022 08:27:53 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=6BDOSEGT0y+2WOd0fksOzxPg5dHDpE5xNyJzQhM+fiE=; b=cFycs40/bI4iLxYIEV+3tJl+X1dcA01yjKub0OSaS/vN4dzw0/vlwM2bd/kPps2WHP pbHi19bmpTWYXLNieKvGKnM1PjZoXFdgpXNUBjhPaCj9Ym12+yuJbJGrtb/Q19pE7Cj6 ccVwsI0gDQLqrF1HSUQKxiFQ60EI0iJSNf877xbcfS+55ZFC+f9kxFSg+QyH5GwHsPF7 00Rk3jaZ+Ke42l20XMpf5oVI3A+irqyty8EsdjXqPIlgulf6cb8/LuloualDg0koZs9f pCbZXjY2kUBNuyZkgHzqHeCgfmleBvBU3oU1U/G0+dT6gzFaRHdLKr2Py5adoFvpCPGm hJpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=6BDOSEGT0y+2WOd0fksOzxPg5dHDpE5xNyJzQhM+fiE=; b=F1rm0ChrY6WVNQfb6IStxxi2fltRx29KJTq1+HGvoqO3OIpUMV5cOwbHKDWE/CDzUe U4NVjLZsL+xiBlGsMrWObq8v7W0WawrldH4R3a20ytTgLARDPVfThH/hq9P8mWgZRc9Y 3jeP8HCrA1HwasLmS6c18J2Kofg0NuMXIv40TWgMJGvdJ8pnpC0AMvByr9huMhqRvDzL llMMsWrLBZuo9IoWW6FVDfNhKbDosp/QTXeXKzL/pPn+t+OeV7aRLWs8f+5ydKK1f3y+ yCXhhJyVmggE3IoTCzZEmoqfq8dEJRYFIs59i+x8SLjnzRWY/1PupBL2kUOkqg8qIbUB Hs2A== X-Gm-Message-State: ACgBeo260+qnfBF6tpqie57JDfDJ3A/0XydyH3N19+eByIqa0CwAF1E6 lqt7NCXmySSqRgwzWkvapzU1f/JC/qvtEA== X-Google-Smtp-Source: AA6agR4C1HJtRRno8ZIx1EG7R6feIg4X8IhkgbAvcr0jzX3kG85S9FVFM0fPYWcU2ZNeH+26UwHDMQ== X-Received: by 2002:a05:6a00:1c69:b0:536:ccaf:c551 with SMTP id s41-20020a056a001c6900b00536ccafc551mr2766243pfw.59.1661182072289; Mon, 22 Aug 2022 08:27:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 12/66] target/arm: Add secure parameter to pmsav8_mpu_lookup Date: Mon, 22 Aug 2022 08:26:47 -0700 Message-Id: <20220822152741.1617527-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186283892100001 Remove the use of regime_is_secure from pmsav8_mpu_lookup, passing the new parameter to the lookup instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 4 ++-- target/arm/m_helper.c | 2 +- target/arm/ptw.c | 7 +++---- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7f3b5bb406..ee40f41c12 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1152,8 +1152,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi, - uint32_t *mregion); + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi, uint32_t *mregion); =20 void arm_log_exception(CPUState *cs); =20 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 45fbf19559..5ee4ee15b3 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2810,7 +2810,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) ARMMMUFaultInfo fi =3D {}; =20 /* We can ignore the return value as prot is always set */ - pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec, &res, &fi, &mregion); if (mregion =3D=3D -1) { mrvalid =3D false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bbfb80f4dd..5628581ddc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1701,8 +1701,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi, - uint32_t *mregion) + bool secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi, uint32_t *mregion) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1715,7 +1715,6 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, */ ARMCPU *cpu =3D env_archcpu(env); bool is_user =3D regime_is_user(env, mmu_idx); - uint32_t secure =3D regime_is_secure(env, mmu_idx); int n; int matchregion =3D -1; bool hit =3D false; @@ -2034,7 +2033,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } } =20 - ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, + ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { result->page_size =3D 1; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183917; cv=none; d=zohomail.com; s=zohoarc; b=JJZFyTLSjiVp3xScEhinMFgTtm7V8PexviL2owXG3flQjmsA80wQ3dkKGQAe3ImSVxNvkMAfXAvi43+MzUKSz8+G4vfCRb5FSFc1B+kla9i+bVNDkFCloYJ4K5k8/NG6QtYsCIpq0ZyVCXpusORph+q9Ld7ddtFKzLeH9QBuECw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661183917; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1eh9DETdW0GbelT1RBsxHXY98fMacnuqD6EL7eauGgo=; b=b5TwE4nXrHa7WmIZlT0qHVKEgagHH59IK59OQled0k24rr4Vj0JCrFBSI2oN5ckQ18ZdzMdeohz3u/pxShN3/JJjJDaRDh7nNP5915kfgneFzEVK+UsFz8lSFNg6RTQuTB8ZoWTJBSE5k9WrTWylRV8E4nlBOQ8H6+0RzrgwMtM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661183917990762.7058432907626; Mon, 22 Aug 2022 08:58:37 -0700 (PDT) Received: from localhost ([::1]:47476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9ox-0006qp-UT for importer@patchew.org; Mon, 22 Aug 2022 11:58:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LM-0007Vk-N3 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:00 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:34374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LG-0000iG-OZ for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:00 -0400 Received: by mail-pl1-x632.google.com with SMTP id jl18so10251796plb.1 for ; Mon, 22 Aug 2022 08:27:54 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=1eh9DETdW0GbelT1RBsxHXY98fMacnuqD6EL7eauGgo=; b=uh4Mnjf1Tj+JoUM49nZJOdbZYwEzSE4XOAJOFM41uoIBywpVKK/exeLo8jOe6skHvu i36lc9g8D4KhQzmo/1ZNbDL+brtcxOig2A2vi3SsEiHiiB6snnwaMQyrfE1b0CcW+ID7 GcY9pN+vFTSXBYe8AVfvtXlGFFh0k5zPplAsCuMQttK+ZluAFA8dyRY1skHe4Ns5r8c6 PzHsVi6Ss+IxbVMSAJAfaxvymEmjzi9YHby5ioPYPSFkGDrUZcJDf9s26WPch5pPz8A+ TBMZnSZsyh198fapgEb1yEE2cwL6NoqRAoSqdHfr3F1MqBwCYbUqSM6aG3HXEQrsYKxt QtLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=1eh9DETdW0GbelT1RBsxHXY98fMacnuqD6EL7eauGgo=; b=k7S2ub+mQkKdXSWg88IwmG4S2E1A0FwJxDlIZbi32ohvgCv8caatRariTcILFsZoaN jRXe7LsXhwAUYsKHMSOKuuk4/oWFZkL4ReGrP30PuKGtQI25DCCNR4rReb1kMR0bb0wI R9tQe/ursDsNRx/w+rl0cJsTSDx1WDGMgLrj+mnaPoFY9qg2GyVQetNzrLzr7mH5BHyS FmwkBJZkAUwStdhzhsNc1JJ2jneCEgvRY9aW4Th7G6r6SzofEH9UF4YaHS/sO2yaK0C+ 6fYZ8zjyFmI9E6fsloS3rp38qqE6rsOw+5CMgA/NGzjhRv3D/PHdSvb5hqXGBjHxDSN+ Nppw== X-Gm-Message-State: ACgBeo2KvKZ2RWpVHxssfbC0Ef/n+lzzC07/Hd8QLU4JUDzlc+ZMnhKZ ldQfvA4MuvgAtWUvj6q9pthrTUenruoNWw== X-Google-Smtp-Source: AA6agR7AVDO+glixXjDV2C+oRmQe/mMbmMIZpxCh5XFb5Rf85NI1VvTYUITWJfUlXZ+XoOiWBCq8Ug== X-Received: by 2002:a17:902:d48f:b0:16f:a73:bf04 with SMTP id c15-20020a170902d48f00b0016f0a73bf04mr20911488plg.43.1661182073118; Mon, 22 Aug 2022 08:27:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 13/66] target/arm: Add is_secure parameter to get_phys_addr_v5 Date: Mon, 22 Aug 2022 08:26:48 -0700 Message-Id: <20220822152741.1617527-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183918356100001 Remove the use of regime_is_secure from get_phys_addr_v5, passing the new parameter to the lookup instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5628581ddc..4609278b42 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -414,7 +414,8 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMM= UIdx mmu_idx, int ap) =20 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { int level =3D 1; uint32_t table; @@ -433,8 +434,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -472,8 +472,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* Fine pagetable. */ table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc =3D arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -2512,7 +2511,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661185679; cv=none; d=zohomail.com; s=zohoarc; b=WMd+c1ENr/+mawb8tK3/DTImFytAix+1dIagAkZRWQrxdXFL+5oGRAfaWkEt9CkwXj0K/ulMXLI4AyHGOnTS1N+g39rzWPStISqCNZ8Yv0i9SjxG9P2pViw/md08ilHzi45MTi50s/1gC/yYY3kU9KdcW9B6ct1AtaRu2Qwww2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661185679; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BX+4xB/VDWHk38SQNes18SXGBzYUd9d/yvot5DujC+I=; b=a1/EY1pjvmfYG2tz2Bp/XuzOlTH0LYEMmivvP6xnyFalxrkMG6ozI8ZGGoiNbRADszRSNqTsW8m/2znQ7vfQRwv4hViknvdOuBdSZYONX00gJXy4hYjXSOcqntYH3mzOpcKJBsOfiKo442KYuLl62WuAGP3SBb/r5KwHZBo8hPI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661185679662748.2385019080527; Mon, 22 Aug 2022 09:27:59 -0700 (PDT) Received: from localhost ([::1]:57266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAHN-0001Cq-Nm for importer@patchew.org; Mon, 22 Aug 2022 12:27:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LR-0007ic-04 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:05 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:41944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LH-0000it-Gj for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:03 -0400 Received: by mail-pj1-x102e.google.com with SMTP id t2-20020a17090a4e4200b001f21572f3a4so11693294pjl.0 for ; Mon, 22 Aug 2022 08:27:55 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BX+4xB/VDWHk38SQNes18SXGBzYUd9d/yvot5DujC+I=; b=n6ywuIDZmU/esoI0SslXsFkFgnj4YQVQmtEk90igcrxqCbjK0fCmqqNYYuJ6i/PrV1 8xZtI3EGQ9wx979Ls7pyQr8xBd/5QLYZ29wh0vYJOGCv3Sijqg3eO9hP9Xc+CSMblkp4 pURLEQxeH28HF678GhvlvV6WO6pZ+ieI2PMynqXippJTaaEFGixlDoRyRV1vpf5GheR1 7PME3mapuHLKCGBKNbJOGncy4mt7UnYBgFTCcJm1z+YlQL2yb2X22lU7x3dh5vcdhYDT tBnW1m9vZwcVot3nOjfUrGmOveSy0sIC0Ygtd4e6vtRldKghttfSqvdKEW/3sKEL4kWr 2w4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BX+4xB/VDWHk38SQNes18SXGBzYUd9d/yvot5DujC+I=; b=vKuU3apAgQU8+QdDGrsXRx0JLO0Cwr+lbzUInxAf3yuVJ4PmRDix1suVwSgMY+EZ+X teia6fE1y5Tocy/Yd9Sm/pvfmGwT3my7dSHf3d4VoCQ6/RxZsfLjoGVIFYTdFx4F48YK wGrWd2Q2Uv/qtteUF043LyNmv8FGni/PsjvKKWBILExhHC8JRUiL35yJ5NUzjEL77jiF Uo4O058mdTC9UiUfIoAIsr3h/+SocxGWFWb2TLeSKl5rYIPPZaXuVXSsqaLuLylxLhgW kAXR3j7EuqzChelPVD66uhAT5h4oNoKVg2zs0ZJkIgjD3DKkdsaA222ZOafRrY/guNk1 gWow== X-Gm-Message-State: ACgBeo2W9yd66m1hmFQsniaBumZtwjNL2u0A447aC3/2HZ5a0wTHkMpO qO6OdPtslhkSreGGoYPQhyja/mJUwrwttg== X-Google-Smtp-Source: AA6agR5o5amRR0ROpZ3ZUzi54uBGG+9Qd8WB+aVGNz9DreFDCusFuroLq38ojCGJqRK/AauRxJTmiA== X-Received: by 2002:a17:902:f688:b0:172:f892:5c3c with SMTP id l8-20020a170902f68800b00172f8925c3cmr1906447plg.49.1661182074122; Mon, 22 Aug 2022 08:27:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 14/66] target/arm: Add is_secure parameter to get_phys_addr_v6 Date: Mon, 22 Aug 2022 08:26:49 -0700 Message-Id: <20220822152741.1617527-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661185681879100001 Remove the use of regime_is_secure from get_phys_addr_v6, passing the new parameter to the lookup instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4609278b42..a6880d051b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -533,7 +533,8 @@ do_fault: =20 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; @@ -556,8 +557,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -610,8 +610,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, ns =3D extract32(desc, 3, 1); /* Lookup l2 entry. */ table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -2508,7 +2507,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - result, fi); + is_secure, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661185057; cv=none; d=zohomail.com; s=zohoarc; b=Wgl6idQ8cmMPNyfJDApfPrC5OzQ6eIzOCLtK+dgFCX6uSUZTfbPy2fYCSoF8EPpcWuv8mQItNMFcpdhExdW8YVhomX/jl6NZ8yAZW6GRrhFmZ6x+w3759ZFCjBkYJ9P67oL9vBXq6GWfdeDRAmnxXgbbFUoQosnsmTBYI0nJEdw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661185057; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GSDRuelmXHTBnV2ZkAtPbMvnakhm9Yy5oZigW0sA2/o=; b=R8+FWIpy64Eg0hdQrkpGWyU196QrbWNJsAkVGygX/yhIKeO9YvU7TBaQ3894NAYKOKnWP941E165QwBZ+msruqMlLX77n9cW4yWYiXLtQ64cUc89yPqVf1vaQMLS00qPeniIoMxqQYZ0LpZVzGFsGqMGEgw0j5guARTwwFIUi2I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661185057679220.7608192894429; Mon, 22 Aug 2022 09:17:37 -0700 (PDT) Received: from localhost ([::1]:53092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQA7L-00031q-Cm for importer@patchew.org; Mon, 22 Aug 2022 12:17:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LQ-0007gY-7e for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:04 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:42644) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LI-0000j5-Cp for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:03 -0400 Received: by mail-pj1-x102b.google.com with SMTP id s3-20020a17090a2f0300b001facfc6fdbcso10989455pjd.1 for ; Mon, 22 Aug 2022 08:27:55 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=GSDRuelmXHTBnV2ZkAtPbMvnakhm9Yy5oZigW0sA2/o=; b=cHY4ia1PZSpVvJpUxvTTZbwuO2D/HWRflpj0x13V4BecdfuMBpgylaFlqOAQI/8ZnD IYwmpO2jIThSBmZF/tnFxk6c/L+28IUZXkMVkaEg8UuBQAlCOfwjHkOK0WKC/+YK9uck mlVpdn9IIZpj4I4szremlgvWVUbNr3mv+euxyoyFbZ3VefTXwBdJgaBq/Ng84PSK9xFX t3LkcgrzUHzb5Anoky24lm7sQez2DleJ+rNCdXTQz4Blsa1ezTznyfx1uDsCmSz6SmJK SO+1X7TmsVI7S3KJsecg8mji9pkNa2Kn2S8KzSmJ9IOnJkwxOsRgYEuKfpPSf9M+du6h xO6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=GSDRuelmXHTBnV2ZkAtPbMvnakhm9Yy5oZigW0sA2/o=; b=mEI3aQX/L7vW9092s+dlcEf0JJQqSNCCwD4JfO7leG3DzgImv2avXNdcTVVOi7nmBT rzTGaPnWaIp7NX3AOUgKaW7w7/e66sq479huEbEuig/fAfYjhVLWKIaiAfMpbuhQQYeL 125z2VRzyU84ohdCnOVt9/WtYP3tl+k4upNZoFq5flgsRoEXLbUf8flV6op0HGdPx2bm jPEUjJexK76SXWveXybpIbP8+G8c6FOmUSHDsXWldalQOEcHzQJGbNW2QAVYxvNT/Ps3 wg5flx4kcnfTVqI1zJNzt8Fjs2bgYi4+a03TJIw0yEEnm3zz3VcklnvVfkr7a1dciTR9 4jVw== X-Gm-Message-State: ACgBeo3fqYM/U9XNfEOHROLAcKRoH+PWM3suj2/ybKGR6Mac2b5+8ewD rm5ipKGYltwRspbYrTmIC2x6ayU9plSY6A== X-Google-Smtp-Source: AA6agR74a3Kua1RUQ2FTMYSgGFm4G+xzSJF6XaR3TwflcTqQqJdumkXJ2tmxpngfHg40xSGQT8pE0A== X-Received: by 2002:a17:902:a511:b0:172:97a7:6f5d with SMTP id s17-20020a170902a51100b0017297a76f5dmr20720936plq.159.1661182074999; Mon, 22 Aug 2022 08:27:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 15/66] target/arm: Add secure parameter to get_phys_addr_pmsav8 Date: Mon, 22 Aug 2022 08:26:50 -0700 Message-Id: <20220822152741.1617527-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661185059813100001 Remove the use of regime_is_secure from get_phys_addr_pmsav8. Since we already had a local variable named secure, use that. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a6880d051b..fccac2d71f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1963,10 +1963,9 @@ void v8m_security_lookup(CPUARMState *env, uint32_t = address, =20 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - GetPhysAddrResult *result, + bool secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint32_t secure =3D regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs =3D {}; bool ret; =20 @@ -2411,7 +2410,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - result, fi); + is_secure, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661182554; cv=none; d=zohomail.com; s=zohoarc; b=W0HX/KT8kE9rY1mHKTQ5aiVyuyrWukogJSuPMu5PhDkxuKBniCQY0YswBzm2XZj/mvd+NTNGhaRV0DnGQcCvr5up1b7OLOjCbvCHLBVjTqsuIVrh75R20P178kI9wl50PoyJK+cRMCcD5mWwvlwsLJXGTQzUbfKF4kOyKZeAbOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661182554; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Qgb+9tm2qJZiaV7ObM3Kp5VKd2kY2geHHlay7myc1Lo=; b=W0IidMwvkS97kdCRRsyc3YKub+ZD/HhgUFkBEaAn+sUt1v5NvGrTrjdW3ty6m92hk4N/eQprhbMwnuxuc5vCMyzIZKUNZdzYAH3cwg//CtvA+GdNNqaNvBeg0nv/LjcpIpsXftiJzv52ZeyWvRD/G607c1twGCgtF7nmnKvGhtQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661182554167759.1862056296113; Mon, 22 Aug 2022 08:35:54 -0700 (PDT) Received: from localhost ([::1]:35370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9Sy-0006G2-HQ for importer@patchew.org; Mon, 22 Aug 2022 11:35:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LP-0007ec-Jz for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:03 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:33436) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LI-0000dc-CI for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:03 -0400 Received: by mail-pl1-x631.google.com with SMTP id 2so10268530pll.0 for ; Mon, 22 Aug 2022 08:27:55 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Qgb+9tm2qJZiaV7ObM3Kp5VKd2kY2geHHlay7myc1Lo=; b=BdvkrmNKjWAL38fOCA7Viz1NU1Sb7U8NKOCigP2Gyk36OKdgBFtpy9t6gRnuNW/qc8 RH+n4pZ2V7FjcypVfW0nKZihdHsxWOROIuO4m++AnbdeUMfQmaMqIyXxxEPv5UgB3j1j DZ0wi0qew4G5h2dTRix9/Yzyf6hsJktfUST//ImTGxW39GXgSC7jpsDqPRwp5kFHfxx9 zzqngs2qlxKvPwPsAwVQpTYilbsP/a87N20y9h/rtzACxxhDlRqL3Ev8zGgiCYMSh7kc cO/stD4UsXs6mMGvpWI16Li4wwQQ3KeTLQpTTTTjWz3MJsXb+F7eREdvW50H/RdsXaXi AXXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Qgb+9tm2qJZiaV7ObM3Kp5VKd2kY2geHHlay7myc1Lo=; b=xn42bcbH2hSBKw7YnQrNrTVw9bUWtUJhwFD4pSFSyrOZUhvKraDOPG6QRsizRM85rN o3pahw39v+uZYnY3YLeeTOSusGVoqwcvgCNb/lOacNlvwQBkb4mFOVvFn5In7VWzsAib fFnYu4O7mZNNJhdZHAMDUWzU0iAyvYh8xvaDwH5v9sGzFKzd+R3pIlPho+Y9yzG5WUQr K455ZKwHCu8aPtqOLNl1cMfFIky8qHZ5tNITDJucnEpEBrRf9EuuaJhXo9PleihrhW90 Pc6o/jLwmG71vwWw/sefZmKI4+oFWDNHCAYX+CeZ6KKP2hw74XyPUlz/CpXsYLRRDh4y m5OA== X-Gm-Message-State: ACgBeo0hClYnvCo8QI5l22TaRyO1TIDZlj7m8f6IuKPsPjsErJrTNdxh q23vA5ip4MO0kOinbIhwSZlN1gGLQ74NnQ== X-Google-Smtp-Source: AA6agR4y7ReE142bo2B0kRh7NisiOz5vdlIjbs0jR4ioUMfi4XDMAvtBhPSoGz2hlI8a9jhXjNlW0w== X-Received: by 2002:a17:902:d714:b0:170:c27c:d4a with SMTP id w20-20020a170902d71400b00170c27c0d4amr20347705ply.18.1661182075611; Mon, 22 Aug 2022 08:27:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 16/66] target/arm: Add is_secure parameter to pmsav7_use_background_region Date: Mon, 22 Aug 2022 08:26:51 -0700 Message-Id: <20220822152741.1617527-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661182556175100001 Remove the use of regime_is_secure from pmsav7_use_background_region, using the new parameter instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fccac2d71f..b7911e88c1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1489,7 +1489,7 @@ static bool m_is_system_region(CPUARMState *env, uint= 32_t address) } =20 static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, - bool is_user) + bool is_secure, bool is_user) { /* * Return true if we should use the default memory map as a @@ -1502,8 +1502,7 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,= ARMMMUIdx mmu_idx, } =20 if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] - & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MA= SK; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } @@ -1516,6 +1515,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, { ARMCPU *cpu =3D env_archcpu(env); int n; + bool secure =3D regime_is_secure(env, mmu_idx); bool is_user =3D regime_is_user(env, mmu_idx); =20 result->phys =3D address; @@ -1618,7 +1618,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, } =20 if (n =3D=3D -1) { /* no hits */ - if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_use= r)) { /* background fault */ fi->type =3D ARMFault_Background; return true; @@ -1738,7 +1738,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, } else if (m_is_ppb_region(env, address)) { hit =3D true; } else { - if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) { hit =3D true; } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661187837; cv=none; d=zohomail.com; s=zohoarc; b=hyMWXuTPVMAqh6N0hUJYN3AYMcTbdA9pC9wCofyqmw1TiVlTir8S5omWZeqgHN5oCAdwrtuUM6F9qwPb8QZNpncGznpbTMvaeynNgR8bYekXgRqbYVyy1/BXLWbOSqr6w4+wNbKfxAhqAf6/tf1fuI4qHkFiN5YSFVSnh0txeTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661187837; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uZ0BWDD1zBt6bJvdrc6PkSh3qsVXaWKa3Xv5dez69Ms=; b=fywdA+yG0ieFQldX9rVGJD8B2yXMUxuVg5IV3scotqwTf27v8j4SYfQ2yweoWpIq3L8dADLHiO5g3BLiqzhU5xqXmCWgf1G3ciOlmxBiJfM7rzjivmee4NUevi2D76qQZiZE/E01HPy00LYJI13cyAMkJuKHW0sPvMaIYyUVKu8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661187837545370.67052077835876; Mon, 22 Aug 2022 10:03:57 -0700 (PDT) Received: from localhost ([::1]:51702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAqB-000511-BR for importer@patchew.org; Mon, 22 Aug 2022 13:03:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LW-0007sZ-MJ for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:11 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:39846) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LK-0000ja-0k for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:09 -0400 Received: by mail-pl1-x629.google.com with SMTP id d10so10236078plr.6 for ; Mon, 22 Aug 2022 08:27:57 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=uZ0BWDD1zBt6bJvdrc6PkSh3qsVXaWKa3Xv5dez69Ms=; b=fOP1LlOGMN6mfCeMpw9nJBqwfjvPhESkLcrYvh+OazEJdXUlHcvJTmaSnUK6+6cJO3 Vf6Smv5bMK0wdtD7sLggtNW4sSUtKIT8AZZk7Fpnblm3TilKfzvXOxs0C6/AmbiGRakO uwRz+FDSUlz4KMcWv3OmX5YI7kj0kwIIrjAQFOM9KX8VcuYrkQ3A+KisvkUjwTiXd8Lz 6NRSMe7cYwpU/20N/Cg3xUYoh8Yog/y3SvAhhh6eB2ZncWmOSQauDaBxndFUicE0Kr4I Y8rBRJ74QzQALAg0xeagec3xX5W5GE5uFjzKQERf4QzCd+VSdhfDEVgbTJ8HqTYuyYof Gl3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=uZ0BWDD1zBt6bJvdrc6PkSh3qsVXaWKa3Xv5dez69Ms=; b=0eq1f+asVWibHDgkykV9TGveV3OneZTLuUDzKszzCKlnKRuWHCZq8CNK525jAJ9Xw5 OZxVSLBBZcG73g+Ygj9aohnIJj5Qn9l4wxLaRpT8tPdrsVcFJxU6fGLLdKpsmYKBICT5 Mj7/rd3psxWLGDAc8lFOUJhtjU5JQZ9qG79wbChVu/FDEdnGU/QBZxDnC18WSHB+7Naf IuKW+X4UGOC3kQD5rfEI4kKm9ohDSQ18pZCpbckhz50G53/l7q7y6IpZi1ixeZPMp170 2Y2YL0vkWmqOkPCiK25NeX0jw90hfQPACpjVKi7MC9zUI7QWmWk0xXAVh1JdLlhsmMDr 8PjA== X-Gm-Message-State: ACgBeo0xKemqcnrzFzD8kgBXPEvVHggpO5A8Iwk02zZHiT42ZCD4pACr m1Za3iIomWcg+pFt9fr27VycvAPSDZ7/0g== X-Google-Smtp-Source: AA6agR5c89mKcIzyl0OHtBqzdZOMLoNa40DI4GWtlW+jFTVny+GrJPN0iHcID2KDlrDbNLk1+Hnk9A== X-Received: by 2002:a17:902:70c4:b0:172:d8f5:b4bc with SMTP id l4-20020a17090270c400b00172d8f5b4bcmr9697659plt.32.1661182076515; Mon, 22 Aug 2022 08:27:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 17/66] target/arm: Add is_secure parameter to get_phys_addr_lpae Date: Mon, 22 Aug 2022 08:26:52 -0700 Message-Id: <20220822152741.1617527-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661187839022100001 Remove the use of regime_is_secure from get_phys_addr_lpae, using the new parameter instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/ptw.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b7911e88c1..e95fd6b0d9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,8 +16,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ @@ -207,8 +207,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, GetPhysAddrResult s2 =3D {}; int ret; =20 - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, - &s2, fi); + ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, + *is_secure, false, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; @@ -965,8 +965,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa6= 4, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + bool is_secure, bool s1_is_el0, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1183,7 +1183,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. */ - tableattrs =3D regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); + tableattrs =3D is_secure ? 0 : (1 << 4); for (;;) { uint64_t descriptor; bool nstable; @@ -2334,7 +2334,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, memset(result, 0, sizeof(*result)); =20 ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - is_el0, result, fi); + ipa_secure, is_el0, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2502,8 +2502,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - result, fi); + return get_phys_addr_lpae(env, address, access_type, mmu_idx, + is_secure, false, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183877; cv=none; d=zohomail.com; s=zohoarc; b=Ify/tpzngmNaAhGh3i+zB9M5x6ZNuU7TGiABKSsVTNMGR+yDkhArItA5Xks5VTk02oYJr5Crb9DvM7f+I4mT6rhpTjb8/ONWdfw+0x9BjoGTaWZu1s4xXbTOqij6uH+Wr6OoskGgpLXGG59S6R6wBDL8WxkYPOBQT3vcTHVaeHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661183877; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SMbOfNjA07XEkQhhsLqoAxwBL+AS6vzLDZt69vTOMCc=; b=XUNiWExgpXIR1U/01w8KDmwha2WO3x9FqAcyvPGbpF4lbS9yi/GnCtpzs1y/a3XaIbkgF/Dp+xnpolKQnsudSm3fI+JMijoCJgW8qhLzq+C1piOmWmwU+KuTdiFFFhWjw//Ch5J27ufarhB9t59aIc6Cr9K2Wns+gxoPLwBMNrA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661183877716562.6253431223588; Mon, 22 Aug 2022 08:57:57 -0700 (PDT) Received: from localhost ([::1]:48852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9oK-0005WR-Ik for importer@patchew.org; Mon, 22 Aug 2022 11:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LS-0007mv-TG for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:06 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:44770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LK-0000jl-FL for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:06 -0400 Received: by mail-pj1-x102e.google.com with SMTP id r15-20020a17090a1bcf00b001fabf42a11cso11649835pjr.3 for ; Mon, 22 Aug 2022 08:27:57 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=SMbOfNjA07XEkQhhsLqoAxwBL+AS6vzLDZt69vTOMCc=; b=y3gNImoSdCwStRufdXqqyxKcmhSASmalR28HV59f04Z/K54PkxhRapmiYCMz8uEUWP UomGuP92hkEYfn26/6/RPoZWrX8MXkAJUMYVt8+wGnelO5Pz6IvpXyL7IMhIvWe7l7ch n3k0uas44pj/gJe5aTgxvPREVX+W2/++bbAqkXVFAi55QSVe1mTKLEIVI6eXRBBCBERu OSfdWK0ldzHQwjdosoedTAKRytRofQGHxE6acGKCgZAXHg4tKDkO2bn8qfly/77AaVsU j5eLzKFW1+mHcbigDJhjwntS3CCXvA1UgPLYGriwXtCGLJnRbLtZr1YBDfVdCYDsgPBB GURQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=SMbOfNjA07XEkQhhsLqoAxwBL+AS6vzLDZt69vTOMCc=; b=RlJow8kU3may4/5BzFzf5X2A8I+dMSswziGx6RZL00ifQUiNCdAdYE3/Caf2tfCbv+ wsziwsfX4KlvzNRiwsc/Og0PdxTXIV4kb4jkmSQTO1103QxQHbIYj7EDlad+HzRnegEX a+U4zY2EKhteE8Vj3EJX2G2z1u0zys+byedTfeaBBD36fzMcZlHiL863liTM1lep+30p K0WzJnOJwY/XE6nDwEXNvNaJHEPCyDTn/38MwATW1HIo9jMTHGv8oQQ7tQnT+p2qK4dz CbAbVURz3aQ9LNcxEcoSR6Up2K982jCITPOClYWvVVVturToOn9J1sNJVNOOyOHiTjhQ uCcA== X-Gm-Message-State: ACgBeo2DemtQPAi5dfUjLIOkFS25NBmZZ2AksVoQYw3ES99lXG4oe4fO 0DPGl9DLi9dRKbdcDVS8TJW4aL9w6JB2UA== X-Google-Smtp-Source: AA6agR6rfxTm8r6DnIlseDV9ZBQ5q9MeDpMty/nLaQqSz0XIF/rHrM/B0AirGheWhM8Jq7uEGTpu1g== X-Received: by 2002:a17:902:e8d8:b0:172:7e6b:c8ec with SMTP id v24-20020a170902e8d800b001727e6bc8ecmr20494695plg.171.1661182077204; Mon, 22 Aug 2022 08:27:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 18/66] target/arm: Add secure parameter to get_phys_addr_pmsav7 Date: Mon, 22 Aug 2022 08:26:53 -0700 Message-Id: <20220822152741.1617527-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183879956100001 Remove the use of regime_is_secure from get_phys_addr_pmsav7, using the new parameter instead. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e95fd6b0d9..224ba09ecd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1510,12 +1510,11 @@ static bool pmsav7_use_background_region(ARMCPU *cp= u, ARMMMUIdx mmu_idx, =20 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - GetPhysAddrResult *result, + bool secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D env_archcpu(env); int n; - bool secure =3D regime_is_secure(env, mmu_idx); bool is_user =3D regime_is_user(env, mmu_idx); =20 result->phys =3D address; @@ -2414,7 +2413,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, - result, fi); + is_secure, result, fi); } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186439; cv=none; d=zohomail.com; s=zohoarc; b=Dlm8Sxd1V5iFMM8XaDu1zs+Y+AFT/K8ATeX+ulRfC9yoEktJEhJFisPJFdxHTn4hjWF3hdOI9As9IS4aNjS+o4VUdck1B+MUg7fZCA6e30z2i85ObUeafIE3iG2hBzKenOkXRnGaNgJFsLUlzk4a59tpJ+eORoWVOakglRQyFlk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186439; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O81TsU9W9xgRybd2C2RW59kpRj18EtKgy1SuNeOJbJ0=; b=eR7ooGehhFsRrfDgBqZ4AjZcnnA979XSMhNT5dT3Z1St+d2oQJVifMIEpuK8QeIE8Jp47TWI8WjIMJcx65SctrQF3JegGQSJD2FTY7J631RrcvtTRfqkr+6aL219h4AwAGiA4t2slxQcT/HQshU0YXKahoiOwJokpThB0HyKGwE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661186439264650.7173434903741; Mon, 22 Aug 2022 09:40:39 -0700 (PDT) Received: from localhost ([::1]:58806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQATc-00016K-VF for importer@patchew.org; Mon, 22 Aug 2022 12:40:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LT-0007ny-8l for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:07 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:44564) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LL-0000l3-8F for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:06 -0400 Received: by mail-pg1-x529.google.com with SMTP id c24so9669071pgg.11 for ; Mon, 22 Aug 2022 08:27:58 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=O81TsU9W9xgRybd2C2RW59kpRj18EtKgy1SuNeOJbJ0=; b=kiPm+u8Hc8qLcHnZFBkQXnyuVsYdWL5yXKcw5yyulDrYozxrWW120rmERBEfVYBSf/ MXkoqAxaMGAbTuH97Gz/bKwySgalZw28mPKBPOBnFE+TqwNbdh5AXFncYPQ5GiRLGkcg 53UBUnTAWIhzPnOoKD5IWWyRcBIUR+oDKvRtYW5FSdNeXQNvLKribFnh+1oF628WhVHd bcju/LMAJrCGqXXToCRyhGJn6s18FIX8doyd9shqer7H/4Bjb7ZRenw4ydWZX7fhW27L qxJdK/K2k/s5D/iijieFxcgfjgevlnDOUZwjVm9bYTPQh29XGan0n0zulb2cga1q4BGi YgIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=O81TsU9W9xgRybd2C2RW59kpRj18EtKgy1SuNeOJbJ0=; b=w9t6/ZcGH002dzL49TG2/fsFlyy91Cn2Cfvf960lxeADm6kONT/QaAc0H76YjswMqc LtrHmnqqbiOqYbwftJ580zc8fbzKwBAIhIwsCCCRnKG5lGdYfa/SNx73Apb8We1+U0T+ rwOa43H0aFkbAcTTZJi8xmGIhQiYBPsJiV2jmRXOyaHWDO4pqcnBUqC73JpQoSlulSjH XuAh3p7kWVKlCGTONhqQKUui7+kxSfSUEtLF8MXFbPIf4zIsFbu7apxBNPikMIjtML// QGbw3JAFd8Bi4Li1RHlvuz5xfi0nJpzIxp/asu7x8EePbyeVzJe/2wk136RkFkX/CNzN xHxw== X-Gm-Message-State: ACgBeo2mjSCF9Is3g3HFPNPPgu3yQ0FR/UppCN1b+SqBy1dhOAfnj6hL QI6tCJEwFuEDieUO02DDIwlZrl8nqdq5pQ== X-Google-Smtp-Source: AA6agR6E4+ybGApzzgDpfTyhyCGROJULZl4dUwPGJIKNQa28w0XmQ346r82ni/MRSuGbyez8qnJfhw== X-Received: by 2002:a63:86c2:0:b0:42a:42d5:a4a6 with SMTP id x185-20020a6386c2000000b0042a42d5a4a6mr12720471pgd.189.1661182077816; Mon, 22 Aug 2022 08:27:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 19/66] target/arm: Add is_secure parameter to regime_translation_disabled Date: Mon, 22 Aug 2022 08:26:54 -0700 Message-Id: <20220822152741.1617527-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186441447100001 Remove the use of regime_is_secure from regime_translation_disabled, using the new parameter instead. This fixes a bug in S1_ptw_translate and get_phys_addr where we had passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if Stage2 is disabled, affecting FEAT_SEL2. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 224ba09ecd..eca7763367 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -131,12 +131,13 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUI= dx mmu_idx, int ttbrn) } =20 /* Return true if the specified stage of address translation is disabled */ -static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x) +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_id= x, + bool is_secure) { uint64_t hcr_el2; =20 if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -163,7 +164,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) =20 if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { return true; } } @@ -201,7 +202,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, ARMMMUFaultInfo *fi) { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2, *is_secure)) { ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; GetPhysAddrResult s2 =3D {}; @@ -1355,9 +1356,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, u= int32_t address, int n; uint32_t mask; uint32_t base; + bool is_secure =3D regime_is_secure(env, mmu_idx); bool is_user =3D regime_is_user(env, mmu_idx); =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -1521,7 +1523,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, result->page_size =3D TARGET_PAGE_SIZE; result->prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx) || + if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -1732,7 +1734,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabl= ed */ hit =3D true; } else if (m_is_ppb_region(env, address)) { hit =3D true; @@ -2306,7 +2308,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); =20 /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, + is_secure)) { return ret; } =20 @@ -2434,7 +2437,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 /* Definitely a real MMU, not an MPU */ =20 - if (regime_translation_disabled(env, mmu_idx)) { + if (regime_translation_disabled(env, mmu_idx, is_secure)) { uint64_t hcr; uint8_t memattr; =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186814; cv=none; d=zohomail.com; s=zohoarc; b=brkstLNlTGpk7bIbI3FTJQuX4m6f7SjsORNRF1tuy5Qqu8rFW8T1KbwqoS5OODoe09OIoejlS2yYaquVOxkOuyhEWBevmTFs2wpmD7WweKS6R31ncyZYbmfG/fJJv+UiphWxopA7uQ+3bdagKkTF+iHJfPvTe0xJ/VK5fbiigRA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186814; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QVvH22x8bUjcLYNQ/ECfXWnYzFb7GNF185+z8yEomUw=; b=LxwvPYOOzS2BKEr5EYrlPZqz9kGAKLNb4mEnza12LAkCUmjB9F41KWGs7NzYA0vY1fDMrxFfeYVD1nIVgp3b1XPvJ9LLjcRGHzovJQ5eItOlxeDLVqosgQiZCQPdyfkQJiWHEAr8JtoPokkir3hj8WP0lDz/Asn6SPw43YjrmeM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661186814748721.7762002147306; Mon, 22 Aug 2022 09:46:54 -0700 (PDT) Received: from localhost ([::1]:35366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAZg-0007Wy-G8 for importer@patchew.org; Mon, 22 Aug 2022 12:46:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LU-0007pc-6o for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:08 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:41718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LL-0000li-WA for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:07 -0400 Received: by mail-pl1-x636.google.com with SMTP id p18so10225905plr.8 for ; Mon, 22 Aug 2022 08:27:59 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=QVvH22x8bUjcLYNQ/ECfXWnYzFb7GNF185+z8yEomUw=; b=W3fjhv9/KyxmUPFnf2hroekE3ORZzXOYdutjwT8D4mxUfi1z65uahKUMFAFi2QO5wI XvdGGEQUJPsPZCPYkIE0DBpA6jzanqsIMflTPPvQZJ9Dz8qgcXikdCiiKj0UOyUlklTp sY36A8jFkb8AhExryQxgv+XEXbyq+KZLQWCZvlcUa/k+POBkMxg6MmvmjXN3aRxU2KYZ 5BFcYRWi4m+//Rj1xsN0PN5zVJhpJ1kG+jwzdoQkm0TLYkSTOUUscl7Xqn571OVSTx0p tkNIeeOSM4dfxtwl+PxbOzq4FbiNIlkPtyjxcx8D9cmTj0qcyeaiyKPyuiBaftAOGsSE O9YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=QVvH22x8bUjcLYNQ/ECfXWnYzFb7GNF185+z8yEomUw=; b=RVVhGZVV1T66+uzaDdgYbDQSDxc7bpWRa6GFzPObrPS5JJmaHMrokMG1f5Kw2FXo2n vyy5Sc6RXEYC137PbbaKEh8tm+0yDt98FfjApzNZJS4iF7Tp5dDog3HH1Poh0guQUSUU 6KuSGOavn45AYBSP49QDVWbD3qd4xjackgSPpq6CNh7GTR9pdlgRV1KDCKyO5X6tSWs0 JbGQlfZdbCWnQtpJRrhDwzsMTSP13Jdz2O5vSlQR1mUc2+Dz8LyODA3ZMhs7ErZNemQq zv3KV+b9KfcC565Rowkw+Wteci00leK2U6tJLb9YZ2oTkhOahVlJwbMbNwu6loBLRTky bgDA== X-Gm-Message-State: ACgBeo10GQ33ueyaXdtfTW6+paMAvZ94xHUrfopq+6+KYBswAkVikaFU OAQqFoKzoQuPBTY6QNGKn1aVjubMLZ8/JA== X-Google-Smtp-Source: AA6agR5Wv22w6M4Vg3YKjo5SCg0RabCS3SqyjHvhic38xPgSSuAPhCyXDYkuRHqzncHmewrHJIz0kg== X-Received: by 2002:a17:902:e84c:b0:172:d932:4b11 with SMTP id t12-20020a170902e84c00b00172d9324b11mr9897950plg.125.1661182078683; Mon, 22 Aug 2022 08:27:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 20/66] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Date: Mon, 22 Aug 2022 08:26:55 -0700 Message-Id: <20220822152741.1617527-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186815703100001 Remove the use of regime_is_secure from get_phys_addr_pmsav5. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eca7763367..c338e2324a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1350,13 +1350,12 @@ do_fault: =20 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - GetPhysAddrResult *result, + bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; uint32_t mask; uint32_t base; - bool is_secure =3D regime_is_secure(env, mmu_idx); bool is_user =3D regime_is_user(env, mmu_idx); =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { @@ -2420,7 +2419,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, - result, fi); + is_secure, result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661182990; cv=none; d=zohomail.com; s=zohoarc; b=mW+MUFwvSuvZ8YAXsOwehl77PEDqAPje79vksG0D6LA7cJvj1E8cPe8votVS9bX6AaX9MBQaw/phaXVL+aqp1Wf+toibZDEziq5BZkUKmilgo0fjoaxISFcuOnBUKfze2D69FY0aiIpPzn08shI3ByLilsPguxiNnYY71fxH1oY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661182990; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B0pGM/o1ND0DOJEZi6lFDwkXEDCcB+9OE3p2uVt/JyY=; b=MJdHdisAKq6e6gfzo+lG7dfVx9m5npjq6/U1EPF27rCR0p8VZ2nwQ/Wo5RxGyHeqcYmqfW8YKfNV5X/4zvbBqpTzCETeYIY+VaI3eLyTfww0NbO1BMa2RPgODkprVjY9JYymDcnO1Uk44F1Y4jGfYm2w93t6CVB9X9szpDr2I5A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661182990189166.89344645447704; Mon, 22 Aug 2022 08:43:10 -0700 (PDT) Received: from localhost ([::1]:37158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9a1-0004v3-0l for importer@patchew.org; Mon, 22 Aug 2022 11:43:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LU-0007qr-ML for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:08 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:43679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LM-0000gS-Cb for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:08 -0400 Received: by mail-pg1-x52c.google.com with SMTP id v4so9666345pgi.10 for ; Mon, 22 Aug 2022 08:27:59 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=B0pGM/o1ND0DOJEZi6lFDwkXEDCcB+9OE3p2uVt/JyY=; b=qVaXCuNUJDaGdmBImnqoS8x4nhvidi93dvydgR6WduEpycmLSF2L1LSfU90FKlgH2R VsHl0UqGzBQVf2sh+gkHbJDyMEwjMKPW+6vBKRJOiowX59Go7OKymc0Lxod91UtGtglN wkz+ifjRQzE5BXBFT8z/VYzm3qVo1m1A6aoi5/eYjB4lwXC23/ACgzcOebFYKHN5XaEl pSstjjoXZiPDkdmbohcpKXNYSKxf5ac60L7FBtvmWxFABG+/PDHDC/HcbJT9H/HpF6nz owzznlYUKs+Mz+w5WDPwE4Zl7CfhDJWuvNQTybsffwlIVPo+StxlqQe8DdFldnbhppRs OIEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=B0pGM/o1ND0DOJEZi6lFDwkXEDCcB+9OE3p2uVt/JyY=; b=z9jPnM2F3Zfp30vYyOr0aT7CwmcMGDOXcfT1axrY6WrROLDuz6FoYFb2jMNra/eoIW me2ZssyPAUIkuwbWER+dyi2DAl9J/XqiT0LA5JAXWmMeVSAwtZgzYCtZYA3JLViTcPRI iRAYwPG497f7BLGEqKaZPZauanlfYTV1aC5CTewwz3LSlpUkwzhN62JWJU3jfDhAGQe0 62HjBQflWaV+u2w5h07hBBwGrezqj3KXMfLXnknSVz2Z1+2GFXX5J0kERtucJ1eGKKMb cQfvhmH918n/Ja7PP0g5XRZvYL+LXuVU11v9P+Rdc4fQOjz19xevwVgn7R6P1181TRYl K3wQ== X-Gm-Message-State: ACgBeo28W5ZyKRqgFk5j+GH6BDCAefdn+8EWfZMY7Wpz+8afpG6nzckb UttXhe4l3ARPzXMo5YF9fX8rQDjb78Qq7A== X-Google-Smtp-Source: AA6agR7SDWpNt3/fjDTdT+hUuMhwGNqP8gYgcM4Gzby2bubo+fsuGX6WgaBWs1dPmooX3jZmaqs1iw== X-Received: by 2002:a63:83c6:0:b0:42a:c9db:cb3 with SMTP id h189-20020a6383c6000000b0042ac9db0cb3mr2215908pge.500.1661182079574; Mon, 22 Aug 2022 08:27:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 21/66] target/arm: Split out get_phys_addr_with_secure Date: Mon, 22 Aug 2022 08:26:56 -0700 Message-Id: <20220822152741.1617527-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661182990839100001 Content-Type: text/plain; charset="utf-8" Retain the existing get_phys_addr interface using the security state derived from mmu_idx. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 6 ++++++ target/arm/ptw.c | 21 +++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ee40f41c12..3ccc79f3d9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1145,6 +1145,12 @@ typedef struct GetPhysAddrResult { ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) + __attribute__((nonnull)); + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c338e2324a..c132d0cada 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2282,12 +2282,12 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, * @result: set on translation success. * @fi: set to fault info if the translation fails */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool is_secure, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); - bool is_secure =3D regime_is_secure(env, mmu_idx); =20 if (mmu_idx !=3D s1_mmu_idx) { /* @@ -2303,8 +2303,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, ARMMMUIdx s2_mmu_idx; bool is_el0; =20 - ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, - result, fi); + ret =3D get_phys_addr_with_secure(env, address, access_type, + s1_mmu_idx, is_secure, result,= fi); =20 /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, @@ -2514,6 +2514,15 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, } } =20 +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) +{ + return get_phys_addr_with_secure(env, address, access_type, mmu_idx, + regime_is_secure(env, mmu_idx), + result, fi); +} + hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661187378; cv=none; d=zohomail.com; s=zohoarc; b=KoHDQRbPV09xQR1UmdXG3EyiKAmhriFXl63jhjQ7qnkAXD9GMpXoMLVMIH75QYztbKbBsIPU5NN87GfOkdet2K+v2R7YQFeIsoNDgZSPB8NlpTN0i4dFNUcqW7nUrXzPm/b10eZU7IC8KThdfq61Hy6Cgo3hs4QBiwgcrrvbhP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661187378; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LXSL+H12LObvuYlmrtCN7YFFVJ00RtMPHZQZ6vrA/8I=; b=QKFS62oIECAkhPwOfDMuWk2d1enRIMT4HfZe4b5uEJqwpYU2ZePVhufWLlO13CZCq6QpkLzdXBQw+108K5aWzXRLTN3c8Hro1BEdOEDdmPh9fh29YdnllmwBPgAIrcfEvdgdHxWG/FCuVMCYQtiENaf4stv4wl8697cpgHllyAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661187378708902.6537371945058; Mon, 22 Aug 2022 09:56:18 -0700 (PDT) Received: from localhost ([::1]:54238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAin-00071A-L3 for importer@patchew.org; Mon, 22 Aug 2022 12:56:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LW-0007sX-MO for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:11 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:53084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LN-0000fo-2u for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:09 -0400 Received: by mail-pj1-x102e.google.com with SMTP id f21so11353046pjt.2 for ; Mon, 22 Aug 2022 08:28:00 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.27.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:27:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=LXSL+H12LObvuYlmrtCN7YFFVJ00RtMPHZQZ6vrA/8I=; b=hiB0GAnk+Yh/9CXaY0oXI99cgG3JnZgMav8Adunl9JiKpZGzCeelI04FMsThHz/0vb Wgtusw2ynNl2eMfhQhha5/VuRO+mHiq8YGtydzHR25ziBscYKfPSx9VZSN/zIau64yr9 rG30O965ecDHmHIhGBk/BxHdE/0jWZAOYtzdYLB07tvuH4WkU4FeoLv+/5YJJi6Vs9jk 2fk4zl/6P4EIr4ALnwyLQ6uBD+3UNGqnNUIvJQEODZgNzjLYzoUOnS4HPzgKu7H0ZgdX IT3qxp+9x4W1pfFFQWYJy/jOU9rhH2nA2CUbGCWNi0hCffdmZmR6g0k2wRJbTGgazQx6 iWLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=LXSL+H12LObvuYlmrtCN7YFFVJ00RtMPHZQZ6vrA/8I=; b=mY3TJymp9E1A1aIH/Wm1jsdfbyeijNTZbxP0chs/uw8mnczPtukOsXkq0raTB6Vjje Skn1Tu603xx145R3GWpFMP4QkKwkMCLTuh8CRszjQlQxiXVDFUcs8NwncwayP9f0bghG ltRXt6GuvwjLejjRueCFN29WhhwK0a7Y6RSj6GgOhZAQfyZys4HNymVe0P6YEvWu1qhV eJ2K8OIe0Ip6nLuL75wQndWW5+NUvAdSNxpR3R6YZK7LeMKPGZW2uUozyoPQWnWuVyd8 zo2zXz/KvOh7+fjljVYv8Dm5VedkHw7XpGYCbhytGDMS2AjiZzqg+1NVbOHwLKxjHqnI Jjhw== X-Gm-Message-State: ACgBeo3ICzrHT5rhTqcZdpZbDTNd1mn6OOZx7p9tD7aD5WbWoN6lK13O RYIZnynZcxwYb9Anc9ZokcnHp0Tipo7r4A== X-Google-Smtp-Source: AA6agR6NtHwXsBuW2EJGGSDE37g+WPPNhzf0BkWVMsiV2vnJq+EnDOupPlVAo0X7XSWClvxYrNvXyA== X-Received: by 2002:a17:90a:ab14:b0:1fa:b97f:c28b with SMTP id m20-20020a17090aab1400b001fab97fc28bmr23699834pjq.71.1661182080305; Mon, 22 Aug 2022 08:28:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 22/66] target/arm: Add is_secure parameter to v7m_read_half_insn Date: Mon, 22 Aug 2022 08:26:57 -0700 Message-Id: <20220822152741.1617527-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661187380483100001 Remove the use of regime_is_secure from v7m_read_half_insn, using the new parameter instead. As it happens, both callers pass true, propagated from the argument to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument, but that is a detail of v7m_handle_execute_nsc we need not expose to the callee. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/m_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 5ee4ee15b3..203ba411f6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) return true; } =20 -static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure, uint32_t addr, uint16_t *insn) { /* @@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, - regime_is_secure(env, mmu_idx), &sattrs); + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattr= s); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) /* We want to do the MPU lookup as secure; work out what mmu_idx that = is */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) { return false; } =20 @@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) goto gen_invep; } =20 - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { + if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn))= { return false; } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661184545; cv=none; d=zohomail.com; s=zohoarc; b=bqIOGKljKb1N8RXcKnvTrsxD+iM1/GKxvWZL2vL9Q4MS/kJ6rFJtCND9/zXP5A+uwsgRNOscPKIbpq7vUNeumpFvMbVVv8O2mPqW9DPDxlMzZgDaLtS/WIAXAKdryJM+3z0WttsfrXAqC7ZkqKwEzurETeHt10asxspoDTCEHjs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661184545; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fkqNnGX/LlEsyEi6tEsb9lBzSUYuvqb6pZAxiEEB13M=; b=P2AdvbYE7lqkPwVbT55pBQC1VzkIDz+Qut3P+vmmlpzQ/7+MZ1XChggFUV3uR5FFJOtH7LcwDNImdLAIRvk0FUgbVyyVdO7sicC/hHHL44EK9QF72BfpoN7C0KI3l6N+C6k3yet8xBIUHjYqX764h3FD6zdCIxNrRjgOej4PVyA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661184545959925.1360882327367; Mon, 22 Aug 2022 09:09:05 -0700 (PDT) Received: from localhost ([::1]:54574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9z6-0005Ap-AM for importer@patchew.org; Mon, 22 Aug 2022 12:09:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LX-0007to-9z for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:11 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:45994) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LO-0000mw-OT for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:10 -0400 Received: by mail-pl1-x636.google.com with SMTP id u22so10221170plq.12 for ; Mon, 22 Aug 2022 08:28:02 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=fkqNnGX/LlEsyEi6tEsb9lBzSUYuvqb6pZAxiEEB13M=; b=P6WcUszVwC4wCvwTpred3Wmnnf8VJGGrSF6dmBJLyuFnLSGNA0xZnc5YkW/bvGsdCG BMCO6S2oCwuPjciv67c21wBoFpXxjOadqjGO9P1XWE64m0owJwBPRxBv2nDd+JBFZOGs o1JM1Mxv3cZdV+6bioIQIYRS7n3MQo3puGWfuGL/hHY+BV3Y47N4eyETg2lJEfmXKga7 Ms3bGSaPMZ3tn2/Uw7RXb4nh1h8KhJ6NW3uSdvhgPkrjvADSkbGCS9YKIkXoqsWkWPIj KhcRpK6PTGJ9B7s4jGdBZcy/4Hc+2ht4LJ3OSV++hzQIU9qAu0cfx0FZGnstZacCBn2a bRiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=fkqNnGX/LlEsyEi6tEsb9lBzSUYuvqb6pZAxiEEB13M=; b=ySIkOEbzecfBn86Ap75CZAF26bejaGx7RJM9l2MHS8jTJnjEEB5tzIyzUIaDSKjHSD 75Y6uOc6FdwcrsOw51yHFwHWo5kKIL+q5x7bKRvgkv1sxKakFlEPQCLqOgVxj2vXI4Id MS60t+i7inOjVCwYsjiiF2aze70PnCMpedxFZz+gWyZ8xoSRmVi1Cy6RDjS2AkoKligc vw0zWRGO/nk6Xh0m8aB9vvFbvfkrrGvm+wDHtK53vkXUa/y30ls7nJOmXBeNgfW+Po6x b7anT6XE5UB89ohz5zpjnZtfF7OkDUctePD7xF9ELxIFxh78G51M+twJdfJmn2SYP9x6 pszQ== X-Gm-Message-State: ACgBeo15aFO99zwt31VeiFjzp6GlG58LQGi3znE3fPRK36rRU6Cl1eUL kx7//cLKOmt2eCpnOiAmDk+bGq79JT28bw== X-Google-Smtp-Source: AA6agR7YK15O7gAlGlm04oTL8n6t70wIMmPII6ZFliobhNheaMK3JOZRLGQEi5/ZOf+YDpzDUYl8uw== X-Received: by 2002:a17:902:f395:b0:172:e677:e35f with SMTP id f21-20020a170902f39500b00172e677e35fmr6412077ple.94.1661182081122; Mon, 22 Aug 2022 08:28:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 23/66] target/arm: Add TBFLAG_M32.SECURE Date: Mon, 22 Aug 2022 08:26:58 -0700 Message-Id: <20220822152741.1617527-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661184547131100001 Content-Type: text/plain; charset="utf-8" Remove the use of regime_is_secure from arm_tr_init_disas_context. Instead, provide the value of v8m_secure directly from tb_flags. Rather than use regime_is_secure, use the env->v7m.secure directly, as per arm_mmu_idx_el. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 4 ++++ target/arm/translate.c | 3 +-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5168e3d837..ee94d8e653 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,6 +3192,8 @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* No= t cached. */ FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ +/* Set if in secure mode */ +FIELD(TBFLAG_M32, SECURE, 6, 1) =20 /* * Bit usage when in AArch64 state diff --git a/target/arm/helper.c b/target/arm/helper.c index 68373bc0a9..1fcfc85b76 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10764,6 +10764,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_M32(flags, STACKCHECK, 1); } =20 + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { + DP_TBFLAG_M32(flags, SECURE, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index ad617b9948..bf30231079 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9359,8 +9359,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vfp_enabled =3D 1; dc->be_data =3D MO_TE; dc->v7m_handler_mode =3D EX_TBFLAG_M32(tb_flags, HANDLER); - dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - regime_is_secure(env, dc->mmu_idx); + dc->v8m_secure =3D EX_TBFLAG_M32(tb_flags, SECURE); dc->v8m_stackcheck =3D EX_TBFLAG_M32(tb_flags, STACKCHECK); dc->v8m_fpccr_s_wrong =3D EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG); dc->v7m_new_fp_ctxt_needed =3D --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661187315; cv=none; d=zohomail.com; s=zohoarc; b=LMA3izYPzrV+xnMTNmjoJaqa8gKKtETauuteyDqAMu62A2HhUKNDKauhXKUNhvLaG857sSWRJB4iRibrqotzR4CXaGLTlppqynP/jQ/vuo/RrpZRQ1KDgB3+OPB7lV/7hWcuQMFbsyE6KWFRFMAJQ0y9E+uxsmotOfCh+w9iOI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661187315; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/p3yDPLt+Od/3xnGbXYFjezvrkF5xsGGNiyT/7WuzN8=; b=gelQxbAaHnVupuKkpDVY9glGIO7DGohX3jeBVx7LyJgnaXPZaTmyLB+Guq5bG+eYTOQoBrndsXwE2X3bF7wSV0iZfliiz1EIrw0t2/gz7pbjQdA1TDwpE4eozzHAxQy2r3iJ6LeLCbJRmOMaKvoiY9QnRAmkl782IGr96pIFZcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661187315648511.9825021330215; Mon, 22 Aug 2022 09:55:15 -0700 (PDT) Received: from localhost ([::1]:42486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAhm-0005GE-Kz for importer@patchew.org; Mon, 22 Aug 2022 12:55:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9LW-0007sY-M4 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:11 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:36420) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LO-0000fv-Nz for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:09 -0400 Received: by mail-pj1-x1030.google.com with SMTP id r14-20020a17090a4dce00b001faa76931beso14346975pjl.1 for ; Mon, 22 Aug 2022 08:28:02 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=/p3yDPLt+Od/3xnGbXYFjezvrkF5xsGGNiyT/7WuzN8=; b=cqoAnd08DlfOlL03+zlJ7HxSbAXTccGkSgA9TmTuUr35gNuKan2/0UrqQGIjQH81cP iaWpjL/p/bS/x88t09DHvKoU6C0H/+47mkOFcD3TAqLgk6G72wISYO3DAx1rJbosyort In5vZ3jlj82jimOLT7N1HR8FFT9tiWeq0KLaO1MDtGa4K60PZrOkmOwcFchSCCptxyzw scbNkS5crs4joKzVBuHkRhTZgdg0+ILb1Hp8DCjHw1lqwLrVCRBxqqBA2SBWLSYcxJW9 gNajQQlU+gZlTqEYsm+jjeTNwvK35iirjWFVbBeXTf40ThDSXeqbvF46VOxSMn79btwy jppA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=/p3yDPLt+Od/3xnGbXYFjezvrkF5xsGGNiyT/7WuzN8=; b=uTAvz1SjhL99cJ9R9ztZV1fZsr7mShAqGs37GTJ2x4w7YGt0/iX/KNG3X5g9ooSdon 9TjGHYypWawPsK7VHOWX3OJt1hMndBpSpQ4mH1a5bjmJri7WXhRqFkXLK8O4UEM103+S 68WPahaU4dDU4WneYVjSCHIVD8w3I/76H6rGiQQ4V5LThXhQjwbKnjBLooRD+kU7oqrB unnwXK56qyzF/4eo8o59IRUJj/EiUJ/EUW5HLsgfzTTUgLdA2R/D4l0up0YtIaRQV3Kx DySzT3X5RnihRV+hMCgCv80XzvOP03DQAN16VICzHSgVg6XwouPJfzf9WTCLaefm6lx6 vKnA== X-Gm-Message-State: ACgBeo0C5qzIK0qdRsIopcvEk2T1yyfOQP/xppJen68Ut0r7zoNdkeHn pkrshrHWCDtCClB1ykLxhEW5XU6GSq93TQ== X-Google-Smtp-Source: AA6agR4554q2rNNkV3hfi9D80qSQjnEM6BeJgCtv8Qipys4RDK7BppDp1cT9Yny1+qWlN+GU/f3GTA== X-Received: by 2002:a17:90b:3889:b0:1f5:88cd:350d with SMTP id mu9-20020a17090b388900b001f588cd350dmr29355928pjb.9.1661182081822; Mon, 22 Aug 2022 08:28:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 24/66] target/arm: Merge regime_is_secure into get_phys_addr Date: Mon, 22 Aug 2022 08:26:59 -0700 Message-Id: <20220822152741.1617527-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661187317812100001 Content-Type: text/plain; charset="utf-8" This is the last use of regime_is_secure; remove it entirely before changing the layout of ARMMMUIdx. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 42 ---------------------------------------- target/arm/ptw.c | 44 ++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 44 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3ccc79f3d9..a231000965 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -670,48 +670,6 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_i= dx) } } =20 -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E2: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c132d0cada..400ef00b63 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2518,9 +2518,49 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + bool is_secure; + + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_Stage2: + case ARMMMUIdx_MPrivNegPri: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MUser: + is_secure =3D false; + break; + case ARMMMUIdx_SE3: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_Stage1_SE1: + case ARMMMUIdx_Stage1_SE1_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_MSPrivNegPri: + case ARMMMUIdx_MSUserNegPri: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSUser: + is_secure =3D true; + break; + default: + g_assert_not_reached(); + } return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - regime_is_secure(env, mmu_idx), - result, fi); + is_secure, result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Fwz1VSgCHMlHYHX8znfhremY/2VoXOxNoCIJmQ0b+LY=; b=BN/dH4D6vY+gpK33hUjr9Tk/PypnnTU0gBoauMJgIQMQEp5B5fAlZu8Bxmp2rKJXAK F4kEIKQDazkTMI2eFbv2npqmsxxUvXQYlESfUhUeSZQYLWVPyi+94mXTAbpB69ewAa84 e0RdGrcT7YUds/4/qfGIQuDBTXOERv98bo8ZKgqQqVn9vMxaogcL6s9fg/w9c2UZnKOX 75X2b0iDEKlYFXfllGAE1yjPFljoYjfdN9MCvtb6e/yeVpU8rpUZ81dK2B2aEM7h2p2w b6ZHzDjMBSlnqBAQ+41TS3a+JVB6qkXbCO9pn8BcWPu2OImgBL5uWOVZ6fDRWhoRNlG4 dSeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Fwz1VSgCHMlHYHX8znfhremY/2VoXOxNoCIJmQ0b+LY=; b=zQJXevYwk0F6SsiveQSoxBSu7gKJ2+ZO6RQkHCli/1XvN01RTPVvBzat11Ci1KWS/4 +gdSzIkAQAJ5hZAmZXxjXhU2/FRV+5EGACdTbQyucCE9d7dNTpywJUx4SjnxGW/LB+1n QBLG7GN9RDEikyy6XPLEc/lEBuHAH+XGi2FbwpyUaSXjGW98LgwCG58YetbZwNCPYreq R3TTZg+7RZFTW9I5USC1cLSrv2DbTZ61eFp/fIpgZpaF36G6opTT5BJ852RFvxy/ZGEo KyrfbCvc9ESNNA4216rvZnN4/F8QhFWLYhzlmQQBhIUHemrp6dm3VtwRbDCmth+6BuT5 8yXQ== X-Gm-Message-State: ACgBeo3AP/CRpVWaiJ3p4qo/uV1cEwi82vDys2KQtXKAPnXsof74Bh5g 3BaK5DMF2AAshs1SIxYvMRMCp1III5CfBQ== X-Google-Smtp-Source: AA6agR50+tg2+cE/svEGe+gHiq9zue23n5LSlATBLl0X9fDu0RnviWIsVciUCKCKnhe9eii8kTgLKw== X-Received: by 2002:a63:1c64:0:b0:429:9ceb:57e with SMTP id c36-20020a631c64000000b004299ceb057emr17052468pgm.429.1661182082927; Mon, 22 Aug 2022 08:28:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write Date: Mon, 22 Aug 2022 08:27:00 -0700 Message-Id: <20220822152741.1617527-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183608317100001 Content-Type: text/plain; charset="utf-8" Use get_phys_addr_with_secure directly. This is the one place where the value of is_secure may not equal arm_is_secure(env). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1fcfc85b76..09990ca096 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3105,7 +3105,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx) + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool is_secure) { bool ret; uint64_t par64; @@ -3113,7 +3114,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; =20 - ret =3D get_phys_addr(env, value, access_type, mmu_idx, &res, &fi); + ret =3D get_phys_addr_with_secure(env, value, access_type, mmu_idx, + is_secure, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never @@ -3285,6 +3287,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3306,6 +3309,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) switch (el) { case 3: mmu_idx =3D ARMMMUIdx_SE10_0; + secure =3D true; break; case 2: g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ @@ -3321,16 +3325,18 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) case 4: /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ mmu_idx =3D ARMMMUIdx_E10_1; + secure =3D false; break; case 6: /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ mmu_idx =3D ARMMMUIdx_E10_0; + secure =3D false; break; default: g_assert_not_reached(); } =20 - par64 =3D do_ats_write(env, value, access_type, mmu_idx); + par64 =3D do_ats_write(env, value, access_type, mmu_idx, secure); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3346,7 +3352,8 @@ static void ats1h_write(CPUARMState *env, const ARMCP= RegInfo *ri, MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); + /* There is no SecureEL2 for AArch32. */ + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, false); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); #else @@ -3389,6 +3396,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, break; case 6: /* AT S1E3R, AT S1E3W */ mmu_idx =3D ARMMMUIdx_SE3; + secure =3D true; break; default: g_assert_not_reached(); @@ -3407,7 +3415,8 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, g_assert_not_reached(); } =20 - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, + mmu_idx, secure); #else /* Handled by hardware accelerator. */ g_assert_not_reached(); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661188785; cv=none; d=zohomail.com; s=zohoarc; b=kxVE/9V2uLvqFoNX+3EUXC5FGvA0X0htzm0FKskapvRT2jn293ZuRQxatXJFj8z2EIL6Xl32geOVb4nFbzXxJwcZNWX7I0l8Mr+bxoTlVKL7QZKcGyfB8Cc2RZEd2lG33+7reor86B/Ow7HzcsUGxD1hQlVjLGNxLtcPGUHei98= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661188785; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o2fwdLJJakpTHa+ZyaqQvGypLJhcXOKlbYR2MpafFB4=; b=ZzfF8eAxX4rgMeyHgIR6/c/hajZrtDMY/zsgII027VQSKL4DPot2jThv/Aog29u6uHduCdYKnWk/E1UJay8KzWZtdInA8aDMzQdB2QbDh3FbYjDl6EY7G/R14T+QoEefZfNdxyTpWdMO6GdMXcY1d3Dz+OEGhm5pDoH8e7PT4rw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166118878557850.91065726401405; Mon, 22 Aug 2022 10:19:45 -0700 (PDT) Received: from localhost ([::1]:42848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQB5U-0006RJ-GB for importer@patchew.org; Mon, 22 Aug 2022 13:19:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lh-0008Qq-RM for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:21 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:47062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LS-0000o6-GH for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:21 -0400 Received: by mail-pg1-x534.google.com with SMTP id d71so9663367pgc.13 for ; Mon, 22 Aug 2022 08:28:05 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=o2fwdLJJakpTHa+ZyaqQvGypLJhcXOKlbYR2MpafFB4=; b=oFtolGOo71txGFhrCCwdiHKyDV4h7usoEMgP9MhiGR7Cqces0L4FaQ0QRcVM7+Ypj+ eEVMzQn+oOf7B19jYM261iCDias7BMR3nEnvzh2Wlwz/kjhuk55PP6g60jqxYNZ0Y5vu tqejcTcmPLAoJVWEeAxM6UaEac0HEm5nb5+/6GFkEjHFM+WnZnMU8eOm+C3/K7WMAqvo JfwGA2hcc3QENfauCUE/+ah72XRlUpgDnQCYlVZGqvLmA8Talj9DlQsFhtUc78Zak+WP VbsaB+kGC1SqMpkebVLZTo3dpNUBgqahByrMtedjHOGso2CdpFcKWMrzb+2aYHdhe8c/ dY7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=o2fwdLJJakpTHa+ZyaqQvGypLJhcXOKlbYR2MpafFB4=; b=RRAaj5eFPtCLZV4LvJo+fXfD4ku5FKv7mNQ9ARsIt/VzbAI7KNd34PzhLXlcZdtaV8 k6JL8e0dT80euEH/4tjRkztil78e3JVrfhexRnaci1H503eYLE7r5sSk2m5liB9mTtZs pxNpJNbfON0XzpQHkCBJH5UnfV4Mr8bJni/p5XVWcNlVgNfpUJAkJLxkQ4osQPuNsIcH l9/LTy3p1ckyxIFPja/D6lLFha5yWNyEPCFcN4Vs2zkukQxXNuZpDMaNsXBwEuudwutP k5EId/v2jntK4wOE/jYcJ1ExKBozm+DkCza3dXc5NU+Ibm4aMi45+GUlDxeL27MICRCS EKzQ== X-Gm-Message-State: ACgBeo20dh4itfUUKadeBTFZXFC97HFygmQwdQR0ZC+340CSPhai6oxs w0gm9Bp0w0v64sduDu/y9JYhXNx48YAeCg== X-Google-Smtp-Source: AA6agR7RvBg8HIN8zSh9Ttuwdxm/R1GEa+4o9fPYSXsyHShh5i93b+OCs3osEA4GP2ZP8U0hR4W0iw== X-Received: by 2002:aa7:8055:0:b0:536:df46:c567 with SMTP id y21-20020aa78055000000b00536df46c567mr1467272pfm.1.1661182083712; Mon, 22 Aug 2022 08:28:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 26/66] target/arm: Fold secure and non-secure a-profile mmu indexes Date: Mon, 22 Aug 2022 08:27:01 -0700 Message-Id: <20220822152741.1617527-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661188787916100001 Content-Type: text/plain; charset="utf-8" For a-profile, which does not bank system registers, it takes quite a lot of code to switch between security states. In the process, registers such as TCR_EL{1,2} must be swapped, which in itself requires the flushing of softmmu tlbs. Therefore it doesn't buy us anything to separate tlbs by security state. Retain the distinction between Stage2 and Stage2_S. This will be important as we implement FEAT_RME, and do not wish to add a third set of mmu indexes for Realm state. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 69 +++++++----------- target/arm/internals.h | 31 +------- target/arm/helper.c | 144 +++++++++++++------------------------ target/arm/ptw.c | 25 ++----- target/arm/translate-a64.c | 8 --- target/arm/translate.c | 6 +- 7 files changed, 83 insertions(+), 202 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 68ffb12427..08681828ac 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,6 +32,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif =20 -#define NB_MMU_MODES 15 +#define NB_MMU_MODES 8 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ee94d8e653..cea2121f67 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2873,26 +2873,26 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); * table over and over. * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access * Never (PAN) bit within PSTATE. + * 7. we fold together the secure and non-secure regimes for A-profile, + * because there are no banked system registers, so the process of + * switching between secure and non-secure is already heavyweight. * * This gives us the following list of cases: * - * NS EL0 EL1&0 stage 1+2 (aka NS PL0) - * NS EL1 EL1&0 stage 1+2 (aka NS PL1) - * NS EL1 EL1&0 stage 1+2 +PAN - * NS EL0 EL2&0 - * NS EL2 EL2&0 - * NS EL2 EL2&0 +PAN - * NS EL2 (aka NS PL2) - * S EL0 EL1&0 (aka S PL0) - * S EL1 EL1&0 (not used if EL3 is 32 bit) - * S EL1 EL1&0 +PAN - * S EL3 (aka S PL1) + * EL0 EL1&0 stage 1+2 (aka NS PL0) + * EL1 EL1&0 stage 1+2 (aka NS PL1) + * EL1 EL1&0 stage 1+2 +PAN + * EL0 EL2&0 + * EL2 EL2&0 + * EL2 EL2&0 +PAN + * EL2 (aka NS PL2) + * EL3 (aka S PL1) * * for a total of 11 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes - * as A profile. They only need to distinguish NS EL0 and NS EL1 (and - * NS EL2 if we ever model a Cortex-R52). + * as A profile. They only need to distinguish EL0 and EL1 (and + * EL2 if we ever model a Cortex-R52). * * M profile CPUs are rather different as they do not have a true MMU. * They have the following different MMU indexes: @@ -2931,9 +2931,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ =20 -/* Meanings of the bits for A profile mmu idx values */ -#define ARM_MMU_IDX_A_NS 0x8 - /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 #define ARM_MMU_IDX_M_NEGPRI 0x2 @@ -2947,22 +2944,14 @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_SE10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_0 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1_PAN =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_SE20_2_PAN =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 =3D 7 | ARM_MMU_IDX_A, - - ARMMMUIdx_E10_0 =3D ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_0 =3D ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1 =3D ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2 =3D ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E10_1_PAN =3D ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E20_2_PAN =3D ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, - ARMMMUIdx_E2 =3D ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2971,9 +2960,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE0 =3D 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1 =3D 4 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_SE1_PAN =3D 5 | ARM_MMU_IDX_NOTLB, /* * Not allocated a TLB: used only for second stage of an S12 page * table walk, or for descriptor loads during first stage of an S1 @@ -2981,8 +2967,8 @@ typedef enum ARMMMUIdx { * then various TLB flush insns which currently are no-ops or flush * only stage 1 MMU indexes will need to change to flush stage 2. */ - ARMMMUIdx_Stage2 =3D 6 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S =3D 7 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2 =3D 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage2_S =3D 4 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -3012,14 +2998,7 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), - TO_CORE_BIT(SE10_0), - TO_CORE_BIT(SE20_0), - TO_CORE_BIT(SE10_1), - TO_CORE_BIT(SE20_2), - TO_CORE_BIT(SE10_1_PAN), - TO_CORE_BIT(SE20_2_PAN), - TO_CORE_BIT(SE2), - TO_CORE_BIT(SE3), + TO_CORE_BIT(E3), =20 TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/internals.h b/target/arm/internals.h index a231000965..a21a21299c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -649,21 +649,12 @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_= idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -674,11 +665,8 @@ static inline bool regime_is_pan(CPUARMState *env, ARM= MMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1_PAN: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_2_PAN: return true; default: return false; @@ -689,30 +677,20 @@ static inline bool regime_is_pan(CPUARMState *env, AR= MMMUIdx mmu_idx) static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_SE2: case ARMMMUIdx_E2: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_Stage1_SE0: - return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: + case ARMMMUIdx_E10_0: case ARMMMUIdx_Stage1_E0: + return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1= : 3; case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: @@ -954,9 +932,6 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx= mmu_idx) case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 09990ca096..b9f1a3d826 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1671,6 +1671,7 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* Begin with base v8.0 state. */ uint32_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); + uint64_t changed; =20 /* * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset alw= ays @@ -1730,7 +1731,22 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; - raw_write(env, ri, value); + changed =3D env->cp15.scr_el3 ^ value; + env->cp15.scr_el3 =3D value; + + /* + * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * we must invalidate all TLBs below EL3. + */ + if (changed & SCR_NS) { + tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2)); + } } =20 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2561,9 +2577,6 @@ static int gt_phys_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -2576,9 +2589,6 @@ static int gt_virt_redir_timeridx(CPUARMState *env) case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -3286,7 +3296,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_SE3; + mmu_idx =3D ARMMMUIdx_E3; secure =3D true; break; case 2: @@ -3294,10 +3304,9 @@ static void ats_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) /* fall through */ case 1: if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; } break; default: @@ -3308,7 +3317,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx =3D ARMMMUIdx_SE10_0; + mmu_idx =3D ARMMMUIdx_E10_0; secure =3D true; break; case 2: @@ -3316,7 +3325,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E= 0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3385,17 +3394,16 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + mmu_idx =3D ARMMMUIdx_Stage1_E1; } break; case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; + mmu_idx =3D ARMMMUIdx_E2; break; case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_SE3; + mmu_idx =3D ARMMMUIdx_E3; secure =3D true; break; default: @@ -3403,13 +3411,13 @@ static void ats_write64(CPUARMState *env, const ARM= CPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx =3D ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; + mmu_idx =3D ARMMMUIdx_E10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; + mmu_idx =3D ARMMMUIdx_E10_0; break; default: g_assert_not_reached(); @@ -3679,11 +3687,6 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env= , const ARMCPRegInfo *ri, uint16_t mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); @@ -3703,11 +3706,6 @@ static void vttbr_write(CPUARMState *env, const ARMC= PRegInfo *ri, uint16_t mask =3D ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } @@ -4178,11 +4176,6 @@ static int vae1_tlbmask(CPUARMState *env) ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - return mask; } =20 @@ -4209,10 +4202,6 @@ static int vae1_tlbbits(CPUARMState *env, uint64_t a= ddr) mmu_idx =3D ARMMMUIdx_E10_0; } =20 - if (arm_is_secure_below_el3(env)) { - mmu_idx &=3D ~ARM_MMU_IDX_A_NS; - } - return tlbbits_for_regime(env, mmu_idx, addr); } =20 @@ -4245,30 +4234,17 @@ static int alle1_tlbmask(CPUARMState *env) * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else { - return ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - } + return (ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); } =20 static int e2_tlbmask(CPUARMState *env) { - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE20_0 | - ARMMMUIdxBit_SE20_2 | - ARMMMUIdxBit_SE20_2_PAN | - ARMMMUIdxBit_SE2; - } else { - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; - } + return (ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2); } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4295,7 +4271,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -4321,7 +4297,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4349,7 +4325,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4388,12 +4364,10 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - bool secure =3D arm_is_secure_below_el3(env); - int mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUId= x_E2, - pageaddr); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr); =20 - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + ARMMMUIdxBit_E2, bits); } =20 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -4401,10 +4375,10 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); =20 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_SE3, bits); + ARMMMUIdxBit_E3, bits); } =20 #ifdef TARGET_AARCH64 @@ -4510,8 +4484,7 @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env, =20 static int vae2_tlbmask(CPUARMState *env) { - return (arm_is_secure_below_el3(env) - ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); + return ARMMMUIdxBit_E2; } =20 static void tlbi_aa64_rvae2_write(CPUARMState *env, @@ -4557,8 +4530,7 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env, * flush-last-level-only. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_SE3, - tlb_force_broadcast(env)); + do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); } =20 static void tlbi_aa64_rvae3is_write(CPUARMState *env, @@ -4572,7 +4544,7 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env, * flush-last-level-only or inner/outer specific flushes. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); + do_rvae_write(env, value, ARMMMUIdxBit_E3, true); } #endif =20 @@ -10087,8 +10059,7 @@ uint64_t arm_sctlr(CPUARMState *env, int el) /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el =3D=3D 0) { ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) - ? 2 : 1; + el =3D mmu_idx =3D=3D ARMMMUIdx_E20_0 ? 2 : 1; } return env->cp15.sctlr_el[el]; } @@ -10632,22 +10603,15 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE20_0: return 0; case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: return 2; - case ARMMMUIdx_SE3: + case ARMMMUIdx_E3: return 3; default: g_assert_not_reached(); @@ -10700,15 +10664,11 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } break; case 3: - return ARMMMUIdx_SE3; + return ARMMMUIdx_E3; default: g_assert_not_reached(); } =20 - if (arm_is_secure_below_el3(env)) { - idx &=3D ~ARM_MMU_IDX_A_NS; - } - return idx; } =20 @@ -10911,15 +10871,11 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMSta= te *env, int el, int fp_el, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ DP_TBFLAG_A64(flags, UNPRIV, 1); break; case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: /* * Note that EL20_2 is gated by HCR_EL2.E2H =3D=3D 1, but EL20= _0 is * gated by HCR_EL2. =3D=3D '11', and so is LDTR. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 400ef00b63..2c13586396 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -65,12 +65,6 @@ unsigned int arm_pamax(ARMCPU *cpu) ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - return ARMMMUIdx_Stage1_SE0; - case ARMMMUIdx_SE10_1: - return ARMMMUIdx_Stage1_SE1; - case ARMMMUIdx_SE10_1_PAN: - return ARMMMUIdx_Stage1_SE1_PAN; case ARMMMUIdx_E10_0: return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: @@ -95,11 +89,8 @@ static bool regime_translation_big_endian(CPUARMState *e= nv, ARMMMUIdx mmu_idx) static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_SE10_0: case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE20_0: case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_SE0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -2323,7 +2314,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 s2_mmu_idx =3D (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2); - is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; + is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0; =20 /* * S1 is done, now do S2 translation. @@ -2531,6 +2522,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: + is_secure =3D arm_is_secure_below_el3(env); + break; case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: @@ -2538,17 +2531,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, case ARMMMUIdx_MUser: is_secure =3D false; break; - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_Stage1_SE1: - case ARMMMUIdx_Stage1_SE1_PAN: - case ARMMMUIdx_SE2: + case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 163df8c615..1b593ada36 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -111,14 +111,6 @@ static int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_E20_2_PAN: useridx =3D ARMMMUIdx_E20_0; break; - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - useridx =3D ARMMMUIdx_SE10_0; - break; - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - useridx =3D ARMMMUIdx_SE20_0; - break; default: g_assert_not_reached(); } diff --git a/target/arm/translate.c b/target/arm/translate.c index bf30231079..27e344d486 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -237,16 +237,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) * otherwise, access as if at PL0. */ switch (s->mmu_idx) { + case ARMMMUIdx_E3: case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); - case ARMMMUIdx_SE3: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661188092; cv=none; d=zohomail.com; s=zohoarc; b=KoLXEcvqL4ovJQUJJjIwlBbcQ4TdZnSENPEJA/yAhNPsYz6zg+5rrKl9JApOP1nV34AZrq/kwjc6q6mnnJUHQbclFqcdvjVv3XpbodDw13uT3xhcuceZc7PcpY/5zWq26P2NCoxj/Nqbbf8m27ecZApvKgY4fywqzCTApKtIfDo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661188092; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PKVm0lHT4WCbN6cjWU3f5Rl68TusjrY3hk9BnIKlewk=; b=EroNkpKY/MzqOOWgqj5o8OdaG1DghyOJut8eWfzgf029XQ/XpHoF6hW2dS+pIAmAnrUjS4o32QuiPmt9fmvfMul3HX0kpF1S7I2/1nZNqx/lM3VySDX4FncYrra7r3xArHGEtiGYgF1JldglxdIbZmKIufiXUMiV0G+CByURM3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661188092598247.2277330368678; Mon, 22 Aug 2022 10:08:12 -0700 (PDT) Received: from localhost ([::1]:34822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAuJ-0006CU-8h for importer@patchew.org; Mon, 22 Aug 2022 13:08:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Le-0008Go-6u for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:18 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:44769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LR-0000oF-PJ for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:17 -0400 Received: by mail-pj1-x102c.google.com with SMTP id r15-20020a17090a1bcf00b001fabf42a11cso11650170pjr.3 for ; Mon, 22 Aug 2022 08:28:05 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=PKVm0lHT4WCbN6cjWU3f5Rl68TusjrY3hk9BnIKlewk=; b=kS1sHI1jh2LEgjdd1mGf8UbiFwKTmdlKzL4dKbF+ka0oCTo/hoSpNOM0MQCzOAbYLi 09QYUEDVR9inf7d3dmv6yLXBwXPFr5OTzSiPdPc/I3PnUG4QxY67NWDtVp6tBJrr5aIJ DbGKfEoYlZ9lSCRos81r0gbBg9ym4nr+RmNBasI2jZMzpBcRddx07mHHmj7N52jAP4AU lZB0uTTNkWZgeUsgea9lV6fcgALwIhZmrUj7W37SmTqVq2qBB2KXrtDboOZgmIzr4br4 H0hdvR6UnlCAEmLijPQQ+L6z7bK/aEvwnwGh6UbC15JVv78FL0FcKQRN+mx7v9o2JGfm jKKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=PKVm0lHT4WCbN6cjWU3f5Rl68TusjrY3hk9BnIKlewk=; b=DKby5J6hI+KGJwmLdiZY4YehgVnNSQJ1orJdFExEQ4oVKKxx/kC5O+tp2WRXJcuAOn /gkrZR4Oe4wfnAAVcReTLdf7sJ/0UG+oybqKngRORgWpAX76WoGYc2i2UwZR1w+v6uiB AeYbBUAwDWPFd+fSPyFn5ZfP9c6/bPCt4+ajuJzosD0UdYZ4liXzkjVyvDeixtX1jo2H upbXmgTmQejxVszCaC2x7c5vYx8HNRdwqAqiwRobgHH+I44MYUrC+kOf+Ztzqx7pM5hN 2mcrK5cGgxXwLghrfMwTuAvLniXf9Li/BrAr1PKLo7mu4o9wTpDWuLl5CUxUVC3yxJcI zX4Q== X-Gm-Message-State: ACgBeo29gLLFapco7PZesNefPxKr4MgCX/+14nAS6cVNEUczywq8wx92 yvkZlcHWC1z9tcytIXWJB8urJgi7NUCVkw== X-Google-Smtp-Source: AA6agR5TKmu86TeCXrOrcfw8y6WMdjEBuWtfhJylxbCwi5r9DbryQTK1ePUSV4qXoilSmm/zNRVW6w== X-Received: by 2002:a17:90b:1c90:b0:1f8:42dd:9eba with SMTP id oo16-20020a17090b1c9000b001f842dd9ebamr30141374pjb.160.1661182084283; Mon, 22 Aug 2022 08:28:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 27/66] target/arm: Reorg regime_translation_disabled Date: Mon, 22 Aug 2022 08:27:02 -0700 Message-Id: <20220822152741.1617527-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661188094798100001 Content-Type: text/plain; charset="utf-8" Use a switch on mmu_idx for the a-profile indexes, instead of three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2c13586396..ae9552f46f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -148,21 +148,39 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, =20 hcr_el2 =3D arm_hcr_el2_eff(env); =20 - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: /* HCR.DC means HCR.VM behaves as 1 */ return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; - } =20 - if (hcr_el2 & HCR_TGE) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && regime_el(env, mmu_idx) =3D=3D 1) { + if (!is_secure && (hcr_el2 & HCR_TGE)) { return true; } - } + break; =20 - if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ - return true; + if (hcr_el2 & HCR_DC) { + return true; + } + break; + + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E2: + case ARMMMUIdx_E3: + break; + + default: + g_assert_not_reached(); } =20 return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183366; cv=none; d=zohomail.com; s=zohoarc; b=cHbVVHnA4T7mJGSWSKe/0/zy0USSx3yj7Q80w87/9YsLu2JtJplNo49GzaoJ2YCZhStkIpf7okFMRxxbfYdI3QLXv2NhzGlDx8oiVQf5lPA2oX1gHkky2Dhhw6KVBy2jqjlo6v2RHYulK3FiMHsACwP+1PN4mFy2NsOnoQa3Glg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661183366; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=svQnwizGhYqj2KNlPoUGzrRVUcGJh31LTdC8nQ9RVe4=; b=CL1bPUioTMEmE02jxvIPW8fTrxF1NPnuTKC7G1acdG1/s8dZNstWP18/BgVPnz8zecDmh02Qczz1bewHDkzl+gltoSxwfLBC6SvJBCnJrkgtRaaJkR/g79UIHZ31/a3ivpTmtrk/nhi5RIA8nQQGoWqJiRsCIis7rkqxV58P5Z4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661183366768227.52347589681904; Mon, 22 Aug 2022 08:49:26 -0700 (PDT) Received: from localhost ([::1]:50744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9g4-00036M-Lm for importer@patchew.org; Mon, 22 Aug 2022 11:49:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55012) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lf-0008LP-Ct for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:19 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:47063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LS-0000ob-En for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:19 -0400 Received: by mail-pg1-x535.google.com with SMTP id d71so9663424pgc.13 for ; Mon, 22 Aug 2022 08:28:05 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=svQnwizGhYqj2KNlPoUGzrRVUcGJh31LTdC8nQ9RVe4=; b=XKvCZgKPcgXsJqp/w45cTSa1IbW2yo0eSliLIDiIa6A8Wk1SXDcAKJNmdsJaZwlmc4 AODVVhjd9eD1rp5TuE7utuygIneemHvsdAWsIgmuTKbwUXf0cSg5GMo6Dc61ZO/i8Hs1 59OzDSFSt+q1gdrwYPgphrqUaN/ehTfOwCYSnxHMx+wcYKCsoUy91A1RBvWBo7swEAeP BHlGvPWeiPVXHhoqvyXcrHy+DA5Lmvctk29RQoNDFtYLtn7Mq9BwvErbRLlpoEx6vnTU kH2Wnvnr1F7lcyW6rM6v92AEy6DY6rgy9yGboo5fFoyMO+nEKnoNRewZTRk7sJHaGIw5 Qn8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=svQnwizGhYqj2KNlPoUGzrRVUcGJh31LTdC8nQ9RVe4=; b=Sauij/hlezKhrB2HeoN0bGhpJe8h+6BFMrcuvOcCilvrTMeS9kIno093nNnYyDKjnF 8DIb56XPpWBkRaiPv8qiOwfN7SOnLti8nCGNCS+4y0oElL+qVRQcanhan8bgBorSfU1t BEqxWtcO+T5Fo/4P2uV4A1S9Sj8CnQ/MuQqz2UwaLtPY46AWtDOQzspDxSFcowaVOm1j Qlg/Id9nDidd7725obqpycwafyfRc+zVYi9cs3wGDgWTngXsPJKCQ9J3BHSRY3q4gWgk Vp5/rBBSPv4V4fI+dShZNQ/NKtg1Zk4cKcchsGPV1gtDLEpkZzPwZWLfLkxv/hPlVDce TPbQ== X-Gm-Message-State: ACgBeo19+OdJIjG0Kon/LoQqbbNlgoe62ecL6RyNIamm4sxmukXjPePd Af829oeitpT0taWwbhGtBDFQPlBgHceWxA== X-Google-Smtp-Source: AA6agR6Br77nt+4evDWgJdG6lhEiF2w43lplyIhj1lR9bdcWVB7oFmSz0ZiluJvbCmjMsAc48VmZeQ== X-Received: by 2002:a65:64c6:0:b0:42a:a392:5340 with SMTP id t6-20020a6564c6000000b0042aa3925340mr5501022pgv.588.1661182085109; Mon, 22 Aug 2022 08:28:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 28/66] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Date: Mon, 22 Aug 2022 08:27:03 -0700 Message-Id: <20220822152741.1617527-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183367374100001 Content-Type: text/plain; charset="utf-8" The effect of TGE does not only apply to non-secure state, now that Secure EL2 exists. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ae9552f46f..7c0a4316a3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -157,8 +157,8 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!is_secure && (hcr_el2 & HCR_TGE)) { + /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ + if (hcr_el2 & HCR_TGE) { return true; } break; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661185162; cv=none; d=zohomail.com; s=zohoarc; b=M+eAwaE7Yuzgr2vk6LgBbECwif+kL7pWOBh4+GawSCN+TG6tAhpHhDVitHBPg4cKvaDrOQeANJ5qwg7c6GtpKcnCN2JCG1UI8tTe/CYuLlkYRyD+VpQAIaaXLCLvbbxnh/sDcsOCUA5RWSbCqWcLqqd3sjt1xoAl3nYTRK/Texg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661185162; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4/YHldnnmnuk4Q+DchTbg+rS/RVPMy/dFmBuum/ulns=; b=e+m24jyja1Y1vmH2vMzqoe2THWBBuMePXHzO5i59okSXL5LbSWtsoBVWJ7+ktkJe+dY0BoaHNaWltgypRDMZy1s7+PPgQZm9NY9t5CxWCgfwmHGtP8gZYvY9EAYzpOUz3PtPXBjp6CJpY/vO565gGPR0MkEerOOdW70Zz2rEUsY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661185162399894.4253304464648; Mon, 22 Aug 2022 09:19:22 -0700 (PDT) Received: from localhost ([::1]:45660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQA91-0004Hl-NL for importer@patchew.org; Mon, 22 Aug 2022 12:19:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lj-0008SD-0c for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:23 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:37506) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LT-0000p2-4y for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:22 -0400 Received: by mail-pg1-x52c.google.com with SMTP id bh13so9685199pgb.4 for ; Mon, 22 Aug 2022 08:28:06 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=4/YHldnnmnuk4Q+DchTbg+rS/RVPMy/dFmBuum/ulns=; b=BZ9SaFbFLDtkhExyRbZxLr/DPJFxPRvhG0b6ZbVKH5/mRSHX8VukNmWATjiw9f+Nwn 62aXYuAELyyqnsJlONYZaocNVp0LwZHACqv8giUjP9zevJ2HwoSyclHoW4GwbaUyaEYr vhQmUDX/RP6dmsaa+JkffvVugR3ddk6J38T6nmIkxkCuPMEiwou/Jo2D3vSYD9k63s4x vwZIEBb83LTdLZYrQ4buNvLRIWohUxpAhYe8RhT6greRmHoD0qCwTG7I3OHaqnrlMv3E 5ZvjLlVsKlN/0Hs2ds/YhgVwlfMBL3Y71se6TWAtA9tLIMd5xOx99CpuN9dx9dEvsVjL 8CEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=4/YHldnnmnuk4Q+DchTbg+rS/RVPMy/dFmBuum/ulns=; b=K/CQVNAnKm+rRw47+Oib/zIiUtCxrJA47VFaxZKlGJ7xeqazawvU/Y1rTub+O79X97 xYRh9Ya/CMN5zLNwfsTGhDWvQ3DCkAtJKc/0IUzvcWHsUbNQW+dAd/fIPvdugp6k0sAo 5pjdijg/rKSvAcasEV9VLGe3uKtEFDElB8z3p1+1bVAMcKBF/XqNyLuzdL8TxPI3AJMA LhgRQySvkpKt6X/IniKbTz9atMDhMhAt8mcxuf4fYcXSZeKdHk1oRQVKn1bHbuaDe6+4 8hOmdadD5dSQVj6OJ1ADCu9xf7RVD9M1Cyz4obcx0oynDevMQRPTtbYSNMAAMePUg2Hs oorA== X-Gm-Message-State: ACgBeo3uP4snjRNdNexx3f00apOr9Yb9OjjMMrLj7qlYk0l+VTp/CbU4 SRbKMEDqhxkXBr1nTJYWV3Tq0gUtdImf3w== X-Google-Smtp-Source: AA6agR6sggTja2SJj1CEAhLVFp46nvHDXQn39k/oYq5RkkidOEyhkDRpdCN0NgENsmwSYu2rxqhs5A== X-Received: by 2002:a05:6a00:4acc:b0:536:46c4:d084 with SMTP id ds12-20020a056a004acc00b0053646c4d084mr12449878pfb.71.1661182085645; Mon, 22 Aug 2022 08:28:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate Date: Mon, 22 Aug 2022 08:27:04 -0700 Message-Id: <20220822152741.1617527-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661185164282100001 Content-Type: text/plain; charset="utf-8" For page walking, we may require HCR for a security state that is not "current". Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 20 +++++++++++++------- target/arm/helper.c | 11 ++++++++--- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cea2121f67..a08e546de4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2401,15 +2401,15 @@ static inline bool arm_is_secure(CPUARMState *env) * Return true if the current security state has AArch64 EL2 or AArch32 Hy= p. * This corresponds to the pseudocode EL2Enabled() */ +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secu= re) +{ + return (arm_feature(env, ARM_FEATURE_EL2) + && (!secure || (env->cp15.scr_el3 & SCR_EEL2))); +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_EL2)) { - if (arm_is_secure_below_el3(env)) { - return (env->cp15.scr_el3 & SCR_EEL2) !=3D 0; - } - return true; - } - return false; + return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); } =20 #else @@ -2423,6 +2423,11 @@ static inline bool arm_is_secure(CPUARMState *env) return false; } =20 +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secu= re) +{ + return false; +} + static inline bool arm_is_el2_enabled(CPUARMState *env) { return false; @@ -2435,6 +2440,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *en= v) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index b9f1a3d826..55355197b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5101,15 +5101,15 @@ static void hcr_writelow(CPUARMState *env, const AR= MCPRegInfo *ri, } =20 /* - * Return the effective value of HCR_EL2. + * Return the effective value of HCR_EL2, at the given security state. * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) { uint64_t ret =3D env->cp15.hcr_el2; =20 - if (!arm_is_el2_enabled(env)) { + if (!arm_is_el2_enabled_secstate(env, secure)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5168,6 +5168,11 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); +} + /* * Corresponds to ARM pseudocode function ELIsInHost(). */ --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661189135; cv=none; d=zohomail.com; s=zohoarc; b=ICJIpuvVtNXL4O3Nxjw3tlpMBTIJaR8BwvobNMnO9w8MOF03f6mGbYHUu+xG9DDTSyOXrmRKvpIYX4RzGOGrFqpajjtWysy7sYaES8hFXjr6Fjchr8L69l+8A8UiUFSO3N8H3YevdA9aEzg5/jS0k5OXhSvdsgk8cwh7LUTl5UY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661189135; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HtO4LZZP477l4fezaKu9Yh3w9XE4HiCdIKoUptn6t1w=; b=dr2rIOoFNYt3P/fmgNONv1T7N1arO3uSokp4zhcbx6kXnhOadqbcs/ZgAbjBzSWZrtF6LMdhneFIR018isAKTPRj3nHBABF6NDEafU4RGdMA+qfQwIMPM8pOBxRPAU+pnTYwpBT7QUxkzEM/hhBSRtRtDhb585dyXOr9j3JMFPs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661189135714660.9580790048749; Mon, 22 Aug 2022 10:25:35 -0700 (PDT) Received: from localhost ([::1]:38306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBB3-0004zk-Gg for importer@patchew.org; Mon, 22 Aug 2022 13:25:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ll-00008x-Ln for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:25 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:40943) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LU-0000pc-6U for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:25 -0400 Received: by mail-pl1-x62e.google.com with SMTP id x23so10231570pll.7 for ; Mon, 22 Aug 2022 08:28:07 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=HtO4LZZP477l4fezaKu9Yh3w9XE4HiCdIKoUptn6t1w=; b=v/XqIg3iMI28YOFRjxKs0QoUJ7dJgPOk2cpUbZ/ivo6a6h3EW/2PPQgwQCjex1uWJI azxr1CUrYakkECCOCCiHTt+UZ1m8qzES97qGoCTtpTkMwtMmsHE4bxufuSlYxS7Wlmz4 nzkZM5no2/dNEsykoa2t3oLwfkpB3oyxFRWKA0LJyiKxC9APVcNdUTxZHp3aZYJnPCYe zVHuccDt1Ffvlu2H/mdgQJd4AhdeVMPmOYL3iKMGBNTE79i28456JgjclL+t4hoipTHu z2JB4nXGRDkJ69q8MJJ8XZnKuFp0oHPzWAbJOb+OXvMxuTV67cKej9MnuY3RUKSYc0h/ Gtzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=HtO4LZZP477l4fezaKu9Yh3w9XE4HiCdIKoUptn6t1w=; b=SMYL81vLUQlbjD5TRPtEYma6ZfMQszjXYgZ3BBf5OfNMjjBdnx3B1HtdGsUNHiNBkn 5mSjbkls8zQHCcI1h/DtNUIn1eotTyxOe6cpzDrZ9esYoCU6A7OPFEsKm7SMz/lBsplr K58kgkpT9SsU5gd1Ed/rj/QvSvL1BcjqZzQWLnStzJv2LbiGJBaasz2bIwrB+kFMRu8O uEusL2yYqNh7w5tyb5boKEmRZBNnm1NA5NlxLZ/8rrp76MktuW7SgGeHWHm0QU00N9kV SFTTo22QhCHUb9zrmCsW8n/4vWUAIoCkfhAEgjf/MEjpm8xlfpoLG2VWXcsoy3e6AaNK SNwg== X-Gm-Message-State: ACgBeo2BVZuaqxWYaqf54LbZ5N4IKTEpSaHuiRlJTUGOWITtc527e5k1 DAL09e8FRcA6WmEWZe2Iv0Fq/xCZmCymFw== X-Google-Smtp-Source: AA6agR689/FoxnqzkSQ7b8rAavzlpTrYLRLcCsJ5mbgTFby6pznKGrHy/51GHnn+hpExptJvC/xX7w== X-Received: by 2002:a17:90b:3b41:b0:1fb:5376:fb06 with SMTP id ot1-20020a17090b3b4100b001fb5376fb06mr1590279pjb.240.1661182086809; Mon, 22 Aug 2022 08:28:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 30/66] target/arm: Hoist read of *is_secure in S1_ptw_translate Date: Mon, 22 Aug 2022 08:27:05 -0700 Message-Id: <20220822152741.1617527-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189137814100001 Content-Type: text/plain; charset="utf-8" Rename the argument to is_secure_ptr, and introduce a local variable is_secure with the value. We only write back to the pointer toward the end of the function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7c0a4316a3..dbe5852af6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -207,24 +207,26 @@ static bool ptw_attrs_are_device(CPUARMState *env, AR= MCacheAttrs cacheattrs) =20 /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure, + hwaddr addr, bool *is_secure_ptr, ARMMMUFaultInfo *fi) { + bool is_secure =3D *is_secure_ptr; + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, *is_secure)) { - ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; + !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S + : ARMMMUIdx_Stage2; GetPhysAddrResult s2 =3D {}; int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - *is_secure, false, &s2, fi); + is_secure, false, &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; + fi->s1ns =3D !is_secure; return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && @@ -237,19 +239,20 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; + fi->s1ns =3D !is_secure; return ~0; } =20 if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (*is_secure) { - *is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); + if (is_secure) { + is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - *is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); + is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); } + *is_secure_ptr =3D is_secure; } else { - assert(!*is_secure); + assert(!is_secure); } =20 addr =3D s2.phys; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661185806; cv=none; d=zohomail.com; s=zohoarc; b=Ojxtod/Kh1GJ92gZQjs25K1Ut6Uk9Jv7j59x8MovKRGWsnLQkLhue4khuk0FvH4Y+9+FDYsB2XfmxVyquOJKxfGcMMJJvIh4hYETU0kr+HunZGMMfVcKoolF0u4qZUcubfV2Bw9rH4diMs6t4Ztm7ATo8lqGvnw/OkHIcs8azME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661185806; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r2s4x+bZJOY5/giT1jRp8us14Aquo3FqXDJ1E/9NmhQ=; b=JZP+FpOVbLvacT+R4FPE0D9KiO0imeSR2iQWwyA8jjNJ+F+He6zvH6AiZrot3YbeK8CL6nvmRy8xpHUWnIl/U+buxR+PE6HTfNWKIHZZQX/kOI8tqFh0zA0yW23wXU95+paTl5BnIR4TNmsW8Wj6nJvc/gYj+VfADM0MEcKYzOw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661185806220454.1581932218761; Mon, 22 Aug 2022 09:30:06 -0700 (PDT) Received: from localhost ([::1]:48598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAJR-0003Be-4Q for importer@patchew.org; Mon, 22 Aug 2022 12:30:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lm-0000Ey-VY for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:27 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:54228) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LW-0000q7-Dd for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:26 -0400 Received: by mail-pj1-x1031.google.com with SMTP id m15so3292023pjj.3 for ; Mon, 22 Aug 2022 08:28:09 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=r2s4x+bZJOY5/giT1jRp8us14Aquo3FqXDJ1E/9NmhQ=; b=ohq2sb2ouf5s7iCm7STCUZ7jD7GI/JbnAn8Uuar98848AM9CBHWznKj+61xbvnY1G0 UMC4kHp6AicUdlf8UDtGtPq5VUk9gn7LFEvaynedFDe4qGyYXIpu5plgBsOyLM4e2GQP Oa5aNC0+Md4uuLvtyrr3EKXtlfagdFXpLsrfpMtK+FAwPRaOqp+yVPbqoMmELYVG7OTJ EPLu1NzZq1OU7cqhVHmoO5SY2xXI7GbJcZj1KHqooqWl9IublyZ4t8v57svtOrEa/N6X OUvl0bPQEc92zCLfdY70Y1Ac1ymtJWfWvho9Sn6UX6J/nST3XKaOWCqME4NXUQUQmoNU kt3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=r2s4x+bZJOY5/giT1jRp8us14Aquo3FqXDJ1E/9NmhQ=; b=YBgQv/JH2gHKiuIW34O5aCdjYMum4Sd/gUuLBv/aLg0TXSGY3RtQ/8ERoGoC0H1k85 XQ8d8WHoOmYNIMxvFupbtZlpvCOV9CUIiTPev9KCo/YzjKbtanTUt4L3Q3d0An1PvtSb tkoT66jMTIH5+Y6nFYZfVXDoeTJRD7NkUKhHozOZ/f3wCU5JHMdSDsqI3U03oHohqTQD f9RsUIupU1CLpRqNial7/TWbOhFRdoFU7gLILtdoahYcG1QWho0GbdISSkX0kud86Cej qISvWSkAJBkR4S4he34NOuv5AVsQre9m+4EZFfW43HsaF0neh+54QXb1V13BmTDjs448 Rgew== X-Gm-Message-State: ACgBeo21OjO9y0CQnLaZcrsZrQMm/fAhBlJG7NdGCwoJ8C1hhmuRPofR xYr0LQApzZ7cWxd4i4BjxWDHvJsjtWiYjA== X-Google-Smtp-Source: AA6agR7KH1L7SPsovw38IIQvonZYx+ezDIpwrPJgilkTsmD6qFJMuen7UUrssEtdxjLY/fVoLII5BA== X-Received: by 2002:a17:902:dac6:b0:172:e3c6:2b39 with SMTP id q6-20020a170902dac600b00172e3c62b39mr6979175plx.84.1661182088068; Mon, 22 Aug 2022 08:28:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 31/66] target/arm: Fix S2 disabled check in S1_ptw_translate Date: Mon, 22 Aug 2022 08:27:06 -0700 Message-Id: <20220822152741.1617527-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661185808501100001 Content-Type: text/plain; charset="utf-8" Pass the correct stage2 mmu_idx to regime_translation_disabled, which we computed afterward. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index dbe5852af6..680139b478 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -211,11 +211,10 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; + ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; =20 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { - ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; + !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 =3D {}; int ret; =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186429; cv=none; d=zohomail.com; s=zohoarc; b=e5npU1YdwjDQK3pv8lcIESmd7pSl4vfJW8TXLedRTalXz9po5azfGb9HlRl93dwEZpWyI/R4ALD8eIK3mxif4nFgxdci5FXn/r10A7V2RZ0Aq76jha/ur+fM9+PJEHWParp1mbvOSmlQ1EvVDv3thjhEjfuL0zUSCkQZ6INojfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186429; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b1YKmTdBto+hHkmTMtKDsXucA8L6l9ByKCghI8Y/k9s=; b=HDq5Mif42yIulubWPrCuQmx8F5FXy5peoBqFqmXDPNt3+7xqBN6QyrDz8PUJaEKHI5YbTok6+V/0YPcJhrvxYx9di+UHp2KLSefgOaxwPf8tAbE5jq1Cn4SRlOT27ZKkvgRS2jZKoRdr1MbZCLBZ1O3eJzzzBi5Tk5oRXRr3XFI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661186429005190.84041328952333; Mon, 22 Aug 2022 09:40:29 -0700 (PDT) Received: from localhost ([::1]:55802 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQATS-000106-PA for importer@patchew.org; Mon, 22 Aug 2022 12:40:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lo-0000KL-6y for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:28 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:55184) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LX-0000jk-K2 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:27 -0400 Received: by mail-pj1-x1035.google.com with SMTP id bf22so11327735pjb.4 for ; Mon, 22 Aug 2022 08:28:11 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=b1YKmTdBto+hHkmTMtKDsXucA8L6l9ByKCghI8Y/k9s=; b=IhVOKYk4Y+Hw+0a6QIxuejfY7D7alY1/bXIydPEhrliNVEn4+4FiW8Ad9otuFa7QNV 4HpzXaG6CZusyKdHIMtlz0pfUrexULtt1QB4wfjWnMxxoK2L+bbGQ2xCqsvNJ7LLuNfe ds3BWeCxzmjAhdJWPna+H2YbtWsRf4nO+9pZUNiYVqC1CNlvIuIOJgBmG/QTk1cAQT20 fhdZ9yP2/L0VIoimrAnqtA2L2kieFjswSzxIMDumeeRe4Y4RaNdauf9MElJUPbXw5+2r WxgXR23qNJ+X47AhmaUvZ6IMSgC/wzV4lkFWejGIH85HRXfe/rSeTRJnTclu+fPFqtfU 6hIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=b1YKmTdBto+hHkmTMtKDsXucA8L6l9ByKCghI8Y/k9s=; b=fEe3LsiXJpMZtPF0KYykYiKfCkbDWTzPcBO1/5/8Pvln4970tU4jHnMFUgYzvMi9Ey qHSotJVtSpBnzMmLTRaxy6AtMwUKOsG03B9HlifKWMxKF/WZyW/TNv/PnimHiYul9bm8 AIfOzGDafKflGjIXMxTpqwXg0QwjkpusvDkR2zlpM0GgmnLfcDhV3T926HLa1+jrunDc 2/gApnSbpDo4MkwqXoGtrlPLLeqjQlJZhWjgVGQe9ViOA6o5RL6n1DC+NaEIoZtvubcC N3B37pMAmdVPiewKk58ow0A+fod4gzxnpkDXKgrwP3to17E5iXjAKCRTOXVRIgDtpj8w VSAg== X-Gm-Message-State: ACgBeo21+mN2/AiAXqAG8AlbyciCnr8l93S5Ic62Q/qnVePqmCXYG9hQ YQRS6H2udFSSu0qaeGFu7USYu+vMP3yhgg== X-Google-Smtp-Source: AA6agR4YnL9GG2IsOP6dpQ+0FzB45mBUX/QtkRnJvj4hp45wtu+UewRrEy2nuALeJDG7tS1XgtbJDw== X-Received: by 2002:a17:90a:d585:b0:1f4:f9a5:22a9 with SMTP id v5-20020a17090ad58500b001f4f9a522a9mr29733222pju.49.1661182090817; Mon, 22 Aug 2022 08:28:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 32/66] target/arm: Remove env argument from combined_attrs_fwb Date: Mon, 22 Aug 2022 08:27:07 -0700 Message-Id: <20220822152741.1617527-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186431314100001 Content-Type: text/plain; charset="utf-8" This value is unused. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 680139b478..5c6e5eea88 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2171,8 +2171,7 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) * s1 and s2 for the HCR_EL2.FWB =3D=3D 1 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_fwb(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) +static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) { switch (s2.attrs) { case 7: @@ -2245,7 +2244,7 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, =20 /* Combine memory type and cacheability attributes */ if (arm_hcr_el2_eff(env) & HCR_FWB) { - ret.attrs =3D combined_attrs_fwb(env, s1, s2); + ret.attrs =3D combined_attrs_fwb(s1, s2); } else { ret.attrs =3D combined_attrs_nofwb(env, s1, s2); } --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661189648; cv=none; d=zohomail.com; s=zohoarc; b=iCiZV8oJfElZsMd0NhvReGbBb3jcUFuiUeE930ieNh1BfOO3SSHNH9Kp/fTSQznpgBu//saTgkt/qPXlRO00a95dyAQGOUaBFrvT7ilRzBX7prD5KIG026WzQOKNtibYnnwDSRnX1XPgQ5ckbgxYsfEaMYYdG3mwBh9Ra+xI2Do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661189648; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d/aaxeEB38f4APqu+4DPv/6ce6klQuxkyZkiEyQwHcw=; b=Aep/Y4TBSWiElEpWjR05EiMG4Y2EHEQ/fIkb68yZ3hizE9nghJLg0X1TTcsgSsa/ZNnIOgoXogk15rn/no7Lv53MhHarlTe/Hzr893HqRQbl12iOeAmIzbtZypAlelz4RUi3wxSRF2oMx4nYlkNUryIkAsq7vvhBhDXGJxjd7dc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166118964878441.67831781078689; Mon, 22 Aug 2022 10:34:08 -0700 (PDT) Received: from localhost ([::1]:54992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBJP-0003p7-PG for importer@patchew.org; Mon, 22 Aug 2022 13:34:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lp-0000Pu-Mj for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:29 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:33436) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9LY-0000dc-Mx for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:29 -0400 Received: by mail-pl1-x631.google.com with SMTP id 2so10269305pll.0 for ; Mon, 22 Aug 2022 08:28:12 -0700 (PDT) Received: from stoup.. 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Date: Mon, 22 Aug 2022 08:27:08 -0700 Message-Id: <20220822152741.1617527-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189650961100001 Content-Type: text/plain; charset="utf-8" These subroutines did not need ENV for anything except retrieving the effective value of HCR anyway. We have computed the effective value of HCR in the callers, and this will be especially important for interpreting HCR in a non-current security state. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5c6e5eea88..fe06bb032b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -186,7 +186,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattr= s) +static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) { /* * For an S1 page table walk, the stage 1 attributes are always @@ -198,7 +198,7 @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMC= acheAttrs cacheattrs) * when cacheattrs.attrs bit [2] is 0. */ assert(cacheattrs.is_s2_format); - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { return (cacheattrs.attrs & 0x4) =3D=3D 0; } else { return (cacheattrs.attrs & 0xc) =3D=3D 0; @@ -216,6 +216,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { GetPhysAddrResult s2 =3D {}; + uint64_t hcr; int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, @@ -228,8 +229,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, fi->s1ns =3D !is_secure; return ~0; } - if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, s2.cacheattrs)) { + + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -2058,14 +2060,14 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * ref: shared/translation/attrs/S2AttrDecode() * .../S2ConvertAttrsHints() */ -static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs) { uint8_t hiattr =3D extract32(s2attrs, 2, 2); uint8_t loattr =3D extract32(s2attrs, 0, 2); uint8_t hihint =3D 0, lohint =3D 0; =20 if (hiattr !=3D 0) { /* normal memory */ - if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ + if (hcr & HCR_CD) { /* cache disabled */ hiattr =3D loattr =3D 1; /* non-cacheable */ } else { if (hiattr !=3D 1) { /* Write-through or write-back */ @@ -2111,12 +2113,12 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1,= uint8_t s2) * s1 and s2 for the HCR_EL2.FWB =3D=3D 0 case, returning the * combined attributes in MAIR_EL1 format. */ -static uint8_t combined_attrs_nofwb(CPUARMState *env, +static uint8_t combined_attrs_nofwb(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + s2_mair_attrs =3D convert_stage2_attrs(hcr, s2.attrs); =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2216,7 +2218,7 @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, A= RMCacheAttrs s2) * @s1: Attributes from stage 1 walk * @s2: Attributes from stage 2 walk */ -static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, +static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, ARMCacheAttrs s1, ARMCacheAttrs s2) { ARMCacheAttrs ret; @@ -2243,10 +2245,10 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState= *env, } =20 /* Combine memory type and cacheability attributes */ - if (arm_hcr_el2_eff(env) & HCR_FWB) { + if (hcr & HCR_FWB) { ret.attrs =3D combined_attrs_fwb(s1, s2); } else { - ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + ret.attrs =3D combined_attrs_nofwb(hcr, s1, s2); } =20 /* @@ -2312,6 +2314,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; bool is_el0; + uint64_t hcr; =20 ret =3D get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, is_secure, result,= fi); @@ -2357,7 +2360,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 /* Combine the S1 and S2 cache attributes. */ - if (arm_hcr_el2_eff(env) & HCR_DC) { + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to * Normal Non-Shareable, @@ -2370,7 +2374,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } cacheattrs1.shareability =3D 0; } - result->cacheattrs =3D combine_cacheattrs(env, cacheattrs1, + result->cacheattrs =3D combine_cacheattrs(hcr, cacheattrs1, result->cacheattrs); =20 /* Check if IPA translates to secure or non-secure PA space. */ --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186854; cv=none; d=zohomail.com; s=zohoarc; b=hmfUHU48QBcpUcAJhGjE+5k3JdFIaE3KaMRrWcUdr59rubZUmmvz5Rm12KHb1GxatQIP2KEcWVzCzk8ut0+0Tv5o6dcZg54OEc5RHBzQ7hjmHV8k6oqVEcrAdOTDpyooE3Ed9yorvIpT9wqYyFFfEkBFMd0f6Xm9Rh/+A/YwP28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186854; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Zb+z0FjSLpuiqB1QCemcMh6uuV1Mpuz70yGjsr65duc=; b=E9rcRkjr7AHEk9+4lfY3HJ7xUVpDDndz0I28JYB4KuTCO3BGfUrDrjZmGhqZQS3vCF ekMP6jOxLfzNXDIv0Mr0qJjVB2uPz4xhTv/YDjSMbtQn5eYBoy8gB34DvlurJDtW6LC/ d1cPXxyHABiXBFp7C4EqqN5JbNTu6Z8VzjopZeCiSz3sLVzVCwiyIU9diDUjj8IKxAZG 9Lw6tBf9L8qS8qFu0kL4Ybb++Dw5FVelTL5ubKNqw1+oZXg/X2d+xzGpgbSctdzjkmw1 FkuYIANe33u0j56IGZp3m8tZDf10W18xjYZJnn45pUlYbShnFD+ewE7w6d+QNiRIQ19V sVrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Zb+z0FjSLpuiqB1QCemcMh6uuV1Mpuz70yGjsr65duc=; b=lZr9kCdI442Jo9zafE76zjxsQhtDtQP/bPjxeYbtRA0qsiF+Z3FTcEk4GIPvFjcAEx KGtvdp3HXCzmZ461vSSwxMdgMT6I0OEojryYp41LmQRwiwrq8+YAaGXIhDhtb1LIXyWR V9ksYLmnW2B7eyTn6DDE2DA6f59iuc7DWaTvnSPTNZu5KNkkITEhOt8TiImvIx4I2xTu GGT9wlKvt7NYVUbxumEK+HZD63MqqqrVAku0DmFBr9Mj/omNxW5SYyc9ufgMPQClbMsf 2oOZb1NneoSPXGmUGHGRSqBpMJSHpO/8GglJZi3JOQQu7m5OHes01Iiz06ZweNUKNv+N +Yaw== X-Gm-Message-State: ACgBeo3oi1+VPaH/K5JYqbLzKomVOsDgs0y+FXOc/xaBSACwoDJxPGlY 0qK+kUcLJ2m0LPg5SIUd36ExJWsX++Wumg== X-Google-Smtp-Source: AA6agR4j08DMw9QFKgs2ydM7KjwRLzaElgfRdAV0+jgq+Fl5W/uzAIIsxqOZkU+feB837A5hYqTlpw== X-Received: by 2002:a63:1a18:0:b0:419:aa0d:4f9c with SMTP id a24-20020a631a18000000b00419aa0d4f9cmr16693722pga.389.1661182092906; Mon, 22 Aug 2022 08:28:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 34/66] target/arm: Fix ATS12NSO* from S PL1 Date: Mon, 22 Aug 2022 08:27:09 -0700 Message-Id: <20220822152741.1617527-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186855835100001 Content-Type: text/plain; charset="utf-8" Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so that we use is_state instead of the currend security state. These AT* operations have been broken since arm_hcr_el2_eff gained a check for "el2 enabled" for Secure EL2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fe06bb032b..4da932b464 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, } } =20 - hcr_el2 =3D arm_hcr_el2_eff(env); + hcr_el2 =3D arm_hcr_el2_eff_secstate(env, is_secure); =20 switch (mmu_idx) { case ARMMMUIdx_Stage2: @@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, return ~0; } =20 - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: @@ -2360,7 +2360,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, } =20 /* Combine the S1 and S2 cache attributes. */ - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to @@ -2493,7 +2493,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, result->page_size =3D TARGET_PAGE_SIZE; =20 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff(env); + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); result->cacheattrs.shareability =3D 0; result->cacheattrs.is_s2_format =3D false; if (hcr & HCR_DC) { --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661191058; cv=none; d=zohomail.com; s=zohoarc; b=e9BtNUonEaimcpHXdsnAaPn9r2o3k1XbupqsuN7Ni5bnn7zxEuDVnI6Wq5ZaZv1XVO6Q3jtr7BfCYxd3nHi8kkZWmlt7rC1K/y7tFrEaTQcR8/ETU6heWshJwTNLrjHEwpD3X4dA1KaK1vT/IFvFlJlI0hNLjXj2VpSpyqbqYfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661191058; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iXS0aJbutd/f8RQ8+U+qwbi40Uh9HNiJ8CeYjNnRgmU=; b=L5doRytMeCmSSBxGtrhebki1fxHI4Wa/jotLWiyXoFMNoNVO8eEEWVFCUBABCznqSZYozPfAfkbpYPY6VHdHlL+aQuK1r/3MlQwycANSJhLRCXxAXfoE1+CRpuNF09XoXJTq41yxjB0YhXpf7m9kPWg91qc25Oya6gkokd+MzI4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661191058689219.8086345541392; Mon, 22 Aug 2022 10:57:38 -0700 (PDT) Received: from localhost ([::1]:41340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBg8-00024i-QH for importer@patchew.org; Mon, 22 Aug 2022 13:57:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9M4-0000zK-2E for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:44 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:47007) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9La-0000hK-TR for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:43 -0400 Received: by mail-pj1-x1033.google.com with SMTP id o14-20020a17090a0a0e00b001fabfd3369cso11649523pjo.5 for ; Mon, 22 Aug 2022 08:28:14 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=iXS0aJbutd/f8RQ8+U+qwbi40Uh9HNiJ8CeYjNnRgmU=; b=r3R4MY7A+vxIM8ux/FhZRt+x8nNWqlUZkim+nYjquB65yzGMh5WIqDjwLHm2lZkaVC FZkujjThzqt79bc2NOTD6xne4dV1fYyyvtPy0cLqrR8KpmfWj1T0ucd1tDC4InaSaytG O/B2FKFQGUgYN1tB0t76/rsz5815MPYHCC4uFl4jiaqRXIO75XImARPj/x7nu+cP4U3T qNRErMNFj8M8ZxQ41SCQ/1Ml9YmCwV6pR12N2akeBlNPZOz5wK2jhaJsszuO7t3NYc1j ALiRF/iwZm9g30AHWVdb57kZrMkF/7MvXMrKUlxVxTsim0ORQL69bhEdvsQ7W8YYgMxE Fi7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=iXS0aJbutd/f8RQ8+U+qwbi40Uh9HNiJ8CeYjNnRgmU=; b=VuX4AMzgiPALfsUCwceSLjurBsV7OeijoKdJUFUNyDpsQPRXrZMlJF8zQqCag4IQRf 6g4tIR0iRVnJH8idqfYB2fHVpXXpG8S72X9C1mDqzd9RotD3KlsEndn+YaBPvz91d362 ES5HcZkwpR67HQ4O9MYsTlbSL7Dx5N61XK7W3FeuIfYJeN50OX87SZHgvtYJgwxnkhFq xXAcKXGIoWDfm8bZAxx/zhU7U9BORjHXgXnG5uBYtsz29HR3MuesbLxmE/hs0yR26uFV 7T+MlBCNjn9vp+uyIWCwmkVwenHE2MBIySytqaXN7bHE2PBGpXuFrRRD9vjCXIw7WL1s BV7w== X-Gm-Message-State: ACgBeo3J76Vz1/OU0o7G77uZLmenmNKleodZDAUAiNCdea/1KDHS00Ot U125hNc7pMGldP6yRoFFNrXxDZnRvHzcSg== X-Google-Smtp-Source: AA6agR5ozWBFFDuN99luOBh606LF/2rSVYBkjfAfJi3E12DJuJ1TkP+fJ5sMe/JEUUEzvVNuwvNQVQ== X-Received: by 2002:a17:902:a5cc:b0:170:d1cf:ac83 with SMTP id t12-20020a170902a5cc00b00170d1cfac83mr20431235plq.14.1661182094058; Mon, 22 Aug 2022 08:28:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 35/66] target/arm: Split out get_phys_addr_disabled Date: Mon, 22 Aug 2022 08:27:10 -0700 Message-Id: <20220822152741.1617527-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661191058911100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 138 +++++++++++++++++++++++++---------------------- 1 file changed, 74 insertions(+), 64 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4da932b464..c798b30db2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2271,6 +2271,78 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, return ret; } =20 +/* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.S1DisabledOutput(). + */ +static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + uint64_t hcr; + uint8_t memattr; + + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + result->cacheattrs.shareability =3D 0; + result->cacheattrs.is_s2_format =3D false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + result->cacheattrs.shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + result->cacheattrs.attrs =3D memattr; + return 0; +} + /** * get_phys_addr - get the physical address for this virtual address * @@ -2451,71 +2523,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; - - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of = the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); - } - } - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; - result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } - result->cacheattrs.attrs =3D memattr; - return 0; + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, is_secure, false, result, fi); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661183941; cv=none; d=zohomail.com; s=zohoarc; b=cxkUcLpefwOMV0xTyRynemK4hvAeY3n9zf+JtplCRVyrTJJ+58EA2QEEPv24Rw0+ImmLDzjGKJQsqs/A5SbI743byX2ZakhZ60Q/U0ehifHNoiKItPnA0ijkTv3ItVbGICM3oOFbAGE/J/aYi3iIBDzUxkgEzcQ9P/kp6O7Lm4Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661183941; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ilw+7P1s37Y2jNcUV45jTcqxm83VECE5VnusacIVBZ0=; b=XPW3vBwASu7fQACDB6mTtuDC9m9zquoKaJCTiv1kfPFADcL8WqA/zrfpPxcTLSYrFUAliNqV/+fLaFsPBXjQYY2GbL4K9aoXyljIDoxwyZBLWkyqT9yq0pRSWd1UhB1OE32GEyfBNLvfReUVcX/J1APh1MKMb6A1NFMAYKyTmT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661183941367305.01384178729154; Mon, 22 Aug 2022 08:59:01 -0700 (PDT) Received: from localhost ([::1]:34252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9pM-0007ai-BJ for importer@patchew.org; Mon, 22 Aug 2022 11:59:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lv-0000dH-E5 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:35 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:40674) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Lc-0000sT-7A for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:34 -0400 Received: by mail-pg1-x52a.google.com with SMTP id w13so4595263pgq.7 for ; Mon, 22 Aug 2022 08:28:15 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Ilw+7P1s37Y2jNcUV45jTcqxm83VECE5VnusacIVBZ0=; b=wBnjAVA3P+8srMrTF+7tQdaEZukzf/oEtqCvHzPPqPbkPMCMLWgHMQUkeY+UMwgx1h jWTUTTTvKrWZRYR5NQl72p8FEqXXTpXMC/QtALipLBMcn97B6DCeO3sdnVVf5mO6lG2H LPX2+RvYWVjMPwG3l6XBnicpiQmh6UI2yjnKSVgFxTuSQ7suU1NJTxE0iLFQH2K+s608 pXFZJ3j2un7xPCyay9KCA+S7+rYImb7/V9q3yfUzQkkqKayZbuYWd+rkwlg4hIxRVyHi B8gHkSblioksn2Dg8tgU0hj3F1EORgTzYHHreosxXC51pdKtT49Z7BHqOie/g9HG0akm GOzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Ilw+7P1s37Y2jNcUV45jTcqxm83VECE5VnusacIVBZ0=; b=ws2z/I/j97xb5Va0XwGCQCMJ39BsZujSzh+JsRaRfm+u/fqdXy2CxRpA3Z6Em0rH3D NWLTdKddpZ4moGvljB3ehEuPuFYrFOTa6qCXzDhOfqJBsX+aSzg1eZO0CFU0xELh7au4 cmu7X28AsVhmjmlAPCHvaAibAcaC9WRrN7Wf6cuF85ZUXk4q9ZdaGGShSqIKivXXZLKK gmbL/FqAeRCVgmOgX7Ml1zb7bQcwA0rkR4vNKn6lzPmA2+o0V2yp+0hevERmBYJWt5Pw DxtR39GccvnIg9GFup44ESsCJ5hWn502RV+ZmcXW/y7E/8eBg2boENL4PUgGRWItBS6j CjTg== X-Gm-Message-State: ACgBeo0S7tS9Wcs3MxhnSdZFy3j13bwcuUOiPr6bbZCbNHKkdm86B2zG G4fFkUqjZzHf0dwiioITbcMfN37pOL9bsA== X-Google-Smtp-Source: AA6agR7ZALECQCY95E7aGDb/vgoCc1/gRPXwgzpg1LO1Oe1nGJ5J4SQuPVmveWG0PPlUXf6c96Sl2A== X-Received: by 2002:a63:fb4a:0:b0:429:8605:6ebf with SMTP id w10-20020a63fb4a000000b0042986056ebfmr17273940pgj.225.1661182094863; Mon, 22 Aug 2022 08:28:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 36/66] target/arm: Reorg get_phys_addr_disabled Date: Mon, 22 Aug 2022 08:27:11 -0700 Message-Id: <20220822152741.1617527-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661183942491100001 Content-Type: text/plain; charset="utf-8" Use a switch. Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 115 +++++++++++++++++++++++++++-------------------- 1 file changed, 67 insertions(+), 48 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c798b30db2..fa76f98b04 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2281,64 +2281,83 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint64_t hcr; - uint8_t memattr; + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t memattr, shareability; =20 - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el]; - int addrtop, tbi; + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + memattr =3D 0x00; /* unused, but Device, nGnRnE */ + shareability =3D 0; /* unused, but non-shareable */ + break; =20 - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); + shareability =3D 0; /* non-shareable */ + goto check_range; } + /* fall through */ + + default: + if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + shareability =3D 2; /* Outer sharable */ + } else { + memattr =3D 0x00; /* unused, but Device, nGnRnE */ + shareability =3D 0; /* non-shareable */ + } + /* fall through */ + + check_range: + { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el]; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of + * the bits above PAMax are zero, so logically we only + * need to clear the top byte for TBI. But it's clearer + * to follow the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + break; } =20 result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } + result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; } --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661184549; cv=none; d=zohomail.com; s=zohoarc; b=MNtRMflw0AZDbVbEiOSHUMwE6aAZrzbUbiGQOaadmImUpF+ZLD1x2Il7rP4o8URD1M2Qyue0efrLOvuMbLOSBRIzP6AvOP99mI3hBA++Kr5Td+L1PLiY+0hCg/Z3/jSG3DxMNDdodtCl1Dek8zjlEoz77dsaIClgI//wqnEdDbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661184549; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BMQjmMzkfoITuX+dec8fIu4zsxlYEyz8CB84Zxjp9Y0=; b=US3e7VQedZX4fMx8+qMu3UPFak5/8b58g/Ui089xIdDJMzV6PNFEBTM9/cyrkQzZ6QtR16PILAKkxeyMn67Bse005rIa8jn82GQ68fUZPNwByO3+BNA8FgpWHvdRtnhYJzpY9YbEfiXB10JAfC/IIVGLjS0j33YEwRWA2YEqSts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661184549239163.3798472362373; Mon, 22 Aug 2022 09:09:09 -0700 (PDT) Received: from localhost ([::1]:38730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ9z9-0005IT-26 for importer@patchew.org; Mon, 22 Aug 2022 12:09:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lw-0000gk-Qh for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:36 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:44770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Lc-0000jl-R0 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:36 -0400 Received: by mail-pj1-x102e.google.com with SMTP id r15-20020a17090a1bcf00b001fabf42a11cso11650897pjr.3 for ; Mon, 22 Aug 2022 08:28:16 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BMQjmMzkfoITuX+dec8fIu4zsxlYEyz8CB84Zxjp9Y0=; b=kX8wujSDTJ9d6uaWC3JEZDcjN69k8mKQUsPmSQuGTvRTr1qS8Ip1/KjzVCJAqryTd4 wQN6pvXweRe5EcDlhugg32z5ih18MSOY0yqz57ki3CVTLqjFQPKj3OgVTUI61NOCqfY7 YvgQtZc2KpLBk0CaUJHwxKHSta5tBmeHNvddEPgG2++bXnXzGFix8duhxH8+2LeYO9iM /lnKiy4v49NWGgfmzRiAy2wqiFT7Vr0JDzWqdz58bSZGku2HTzHG/u2heGF/8mKTDJ27 zWVhJpDBpCULzwH3H6SqBPBbDyNZkwiPK60o4lyh5Q8QKOt7PlNXSP/8wCugtPCF36nI jrQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BMQjmMzkfoITuX+dec8fIu4zsxlYEyz8CB84Zxjp9Y0=; b=gqIYAzXmynIIdUpIGVyR/4paOaKHzwUaHCag9IOAArV2iU4rEmgCR9WG2OtNRkUo/q WfCRQa3SvN7uXuvoe2urBY6w6PwW3IsU2iHshPepxW08OsPvjnYqANdz5X/2618LIsCZ mGMtL3Nb4G73RoOBVh4jmOnsu6UHiseX9o3xEZxIFRnRcwX++rzi4FgpaesQsW7NmnJp z4gxRxdzXM1ybcUoZThRHMjOO8BuasvuDWuQqujux7+nQdnk3YjkKNIrX6oOIVwidS8s DibfbtLUhQM7Ien2DEw4UQ1fgxjSNqZsENpyEhDhTCb70Uz8xWKo8hKwyoCg2kClGxyE y4Cg== X-Gm-Message-State: ACgBeo0Z9bTwM6nKMaKDN9MivrvZoEOdy0d7NkZg3IytZbxjbseJZOxc Iqw1eadQqF5a0YY0NyYu/g+7a0HqkeyfDQ== X-Google-Smtp-Source: AA6agR4FfYoZYoJzpuJNTE8zc+iEREkNsghmmEsI4E1AFc5RaaaoRPdCICxlPu/etgcjg83H2j4R8A== X-Received: by 2002:a17:90a:e7d0:b0:1fb:370c:d46d with SMTP id kb16-20020a17090ae7d000b001fb370cd46dmr4727786pjb.33.1661182095812; Mon, 22 Aug 2022 08:28:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 37/66] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull Date: Mon, 22 Aug 2022 08:27:12 -0700 Message-Id: <20220822152741.1617527-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661184551045100001 Content-Type: text/plain; charset="utf-8" This structure will shortly contain more than just data for accessing MMIO. Rename the 'addr' member to 'xlat_section' to more clearly indicate its purpose. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 22 ++++---- accel/tcg/cputlb.c | 102 +++++++++++++++++++------------------ target/arm/mte_helper.c | 14 ++--- target/arm/sve_helper.c | 4 +- target/arm/translate-a64.c | 2 +- 5 files changed, 73 insertions(+), 71 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..f70f54d850 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -108,6 +108,7 @@ typedef uint64_t target_ulong; # endif # endif =20 +/* Minimalized TLB entry for use by TCG fast path. */ typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not @@ -131,14 +132,14 @@ typedef struct CPUTLBEntry { =20 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); =20 -/* The IOTLB is not accessed directly inline by generated TCG code, - * so the CPUIOTLBEntry layout is not as critical as that of the - * CPUTLBEntry. (This is also why we don't want to combine the two - * structs into one.) +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. */ -typedef struct CPUIOTLBEntry { +typedef struct CPUTLBEntryFull { /* - * @addr contains: + * @xlat_section contains: * - in the lower TARGET_PAGE_BITS, a physical section number * - with the lower TARGET_PAGE_BITS masked off, an offset which * must be added to the virtual address to obtain: @@ -146,9 +147,9 @@ typedef struct CPUIOTLBEntry { * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) * + the offset within the target MemoryRegion (otherwise) */ - hwaddr addr; + hwaddr xlat_section; MemTxAttrs attrs; -} CPUIOTLBEntry; +} CPUTLBEntryFull; =20 /* * Data elements that are per MMU mode, minus the bits accessed by @@ -172,9 +173,8 @@ typedef struct CPUTLBDesc { size_t vindex; /* The tlb victim table, in two parts. */ CPUTLBEntry vtable[CPU_VTLB_SIZE]; - CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; - /* The iotlb. */ - CPUIOTLBEntry *iotlb; + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; + CPUTLBEntryFull *fulltlb; } CPUTLBDesc; =20 /* diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a46f3a654d..a37275bf8e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -200,13 +200,13 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, C= PUTLBDescFast *fast, } =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); =20 tlb_window_reset(desc, now, 0); /* desc->n_used_entries is cleared by the caller */ fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); =20 /* * If the allocations fail, try smaller sizes. We just freed some @@ -215,7 +215,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, * allocations to fail though, so we progressively reduce the allocati= on * size, aborting if we cannot even allocate the smallest TLB we suppo= rt. */ - while (fast->table =3D=3D NULL || desc->iotlb =3D=3D NULL) { + while (fast->table =3D=3D NULL || desc->fulltlb =3D=3D NULL) { if (new_size =3D=3D (1 << CPU_TLB_DYN_MIN_BITS)) { error_report("%s: %s", __func__, strerror(errno)); abort(); @@ -224,9 +224,9 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPU= TLBDescFast *fast, fast->mask =3D (new_size - 1) << CPU_TLB_ENTRY_BITS; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); fast->table =3D g_try_new(CPUTLBEntry, new_size); - desc->iotlb =3D g_try_new(CPUIOTLBEntry, new_size); + desc->fulltlb =3D g_try_new(CPUTLBEntryFull, new_size); } } =20 @@ -258,7 +258,7 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFa= st *fast, int64_t now) desc->n_used_entries =3D 0; fast->mask =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; fast->table =3D g_new(CPUTLBEntry, n_entries); - desc->iotlb =3D g_new(CPUIOTLBEntry, n_entries); + desc->fulltlb =3D g_new(CPUTLBEntryFull, n_entries); tlb_mmu_flush_locked(desc, fast); } =20 @@ -299,7 +299,7 @@ void tlb_destroy(CPUState *cpu) CPUTLBDescFast *fast =3D &env_tlb(env)->f[i]; =20 g_free(fast->table); - g_free(desc->iotlb); + g_free(desc->fulltlb); } } =20 @@ -1219,7 +1219,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, =20 /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); - desc->viotlb[vidx] =3D desc->iotlb[index]; + desc->vfulltlb[vidx] =3D desc->fulltlb[index]; tlb_n_used_entries_dec(env, mmu_idx); } =20 @@ -1236,8 +1236,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ - desc->iotlb[index].addr =3D iotlb - vaddr_page; - desc->iotlb[index].attrs =3D attrs; + desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; + desc->fulltlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1341,7 +1341,7 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, } } =20 -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, target_ulong addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) { @@ -1353,9 +1353,9 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); @@ -1365,14 +1365,14 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTL= BEntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, - mmu_idx, iotlbentry->attrs, r, retaddr); + mmu_idx, full->attrs, r, retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1382,8 +1382,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, } =20 /* - * Save a potentially trashed IOTLB entry for later lookup by plugin. - * This is read by tlb_plugin_lookup if the iotlb entry doesn't match + * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. + * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ static void save_iotlb_data(CPUState *cs, hwaddr addr, @@ -1397,7 +1397,7 @@ static void save_iotlb_data(CPUState *cs, hwaddr addr, #endif } =20 -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, +static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, MemOp op) { @@ -1408,9 +1408,9 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, bool locked =3D false; MemTxResult r; =20 - section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); + section =3D iotlb_to_section(cpu, full->xlat_section, full->attrs); mr =3D section->mr; - mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + mr_offset =3D (full->xlat_section & TARGET_PAGE_MASK) + addr; if (!cpu->can_do_io) { cpu_io_recompile(cpu, retaddr); } @@ -1420,20 +1420,20 @@ static void io_writex(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset); + save_iotlb_data(cpu, full->xlat_section, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs= ); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; =20 cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), - MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + MMU_DATA_STORE, mmu_idx, full->attrs, r, retaddr); } if (locked) { @@ -1480,9 +1480,10 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, copy_tlb_helper_locked(vtlb, &tmptlb); qemu_spin_unlock(&env_tlb(env)->c.lock); =20 - CPUIOTLBEntry tmpio, *io =3D &env_tlb(env)->d[mmu_idx].iotlb[i= ndex]; - CPUIOTLBEntry *vio =3D &env_tlb(env)->d[mmu_idx].viotlb[vidx]; - tmpio =3D *io; *io =3D *vio; *vio =3D tmpio; + CPUTLBEntryFull *f1 =3D &env_tlb(env)->d[mmu_idx].fulltlb[inde= x]; + CPUTLBEntryFull *f2 =3D &env_tlb(env)->d[mmu_idx].vfulltlb[vid= x]; + CPUTLBEntryFull tmpf; + tmpf =3D *f1; *f1 =3D *f2; *f2 =3D tmpf; return true; } } @@ -1550,9 +1551,9 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, = target_ulong addr) } =20 static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, - CPUIOTLBEntry *iotlbentry, uintptr_t retaddr) + CPUTLBEntryFull *full, uintptr_t retaddr) { - ram_addr_t ram_addr =3D mem_vaddr + iotlbentry->addr; + ram_addr_t ram_addr =3D mem_vaddr + full->xlat_section; =20 trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size); =20 @@ -1645,9 +1646,9 @@ int probe_access_flags(CPUArchState *env, target_ulon= g addr, /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 @@ -1672,19 +1673,19 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_MEM_READ); cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, wp_access, retaddr); + full->attrs, wp_access, retaddr); } =20 /* Handle clean RAM pages. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, 1, full, retaddr); } } =20 @@ -1715,7 +1716,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr ad= dr, * should have just filled the TLB. The one corner case is io_writex * which can cause TLB flushes and potential resizing of the TLBs * losing the information we need. In those cases we need to recover - * data from a copy of the iotlbentry. As long as this always occurs + * data from a copy of the CPUTLBEntryFull. As long as this always occurs * from the same thread (which a mem callback will be) this is safe. */ =20 @@ -1730,11 +1731,12 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong = addr, int mmu_idx, if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ if (tlb_addr & TLB_MMIO) { - CPUIOTLBEntry *iotlbentry; - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + CPUTLBEntryFull *full; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; data->is_io =3D true; - data->v.io.section =3D iotlb_to_section(cpu, iotlbentry->addr,= iotlbentry->attrs); - data->v.io.offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + = addr; + data->v.io.section =3D + iotlb_to_section(cpu, full->xlat_section, full->attrs); + data->v.io.offset =3D (full->xlat_section & TARGET_PAGE_MASK) = + addr; } else { data->is_io =3D false; data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); @@ -1842,7 +1844,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, - &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr); + &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr); } =20 return hostaddr; @@ -1950,7 +1952,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through full_load. */ @@ -1958,20 +1960,20 @@ load_helper(CPUArchState *env, target_ulong addr, M= emOpIdx oi, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_READ, retaddr); + full->attrs, BP_MEM_READ, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (likely(tlb_addr & TLB_MMIO)) { - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + return io_readx(env, full, mmu_idx, addr, retaddr, access_type, op ^ (need_swap * MO_BSWAP)); } =20 @@ -2286,12 +2288,12 @@ store_helper_unaligned(CPUArchState *env, target_ul= ong addr, uint64_t val, */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), addr, size - size2, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index].attrs, BP_MEM_WRITE, retaddr); } if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), page2, size2, - env_tlb(env)->d[mmu_idx].iotlb[index2].attrs, + env_tlb(env)->d[mmu_idx].fulltlb[index2].attr= s, BP_MEM_WRITE, retaddr); } =20 @@ -2355,7 +2357,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle anything that isn't just a straight memory access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; bool need_swap; =20 /* For anything that is unaligned, recurse through byte stores. */ @@ -2363,20 +2365,20 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, goto do_unaligned_access; } =20 - iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; =20 /* Handle watchpoints. */ if (unlikely(tlb_addr & TLB_WATCHPOINT)) { /* On watchpoint hit, this will longjmp out. */ cpu_check_watchpoint(env_cpu(env), addr, size, - iotlbentry->attrs, BP_MEM_WRITE, retaddr); + full->attrs, BP_MEM_WRITE, retaddr); } =20 need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); =20 /* Handle I/O access. */ if (tlb_addr & TLB_MMIO) { - io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, + io_writex(env, full, mmu_idx, val, addr, retaddr, op ^ (need_swap * MO_BSWAP)); return; } @@ -2388,7 +2390,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* Handle clean RAM pages. */ if (tlb_addr & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + notdirty_write(env_cpu(env), addr, size, full, retaddr); } =20 haddr =3D (void *)((uintptr_t)addr + entry->addend); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..fdd23ab3f8 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -106,7 +106,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, return tags + index; #else uintptr_t index; - CPUIOTLBEntry *iotlbentry; + CPUTLBEntryFull *full; int in_page, flags; ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; @@ -129,7 +129,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, assert(!(flags & TLB_INVALID_MASK)); =20 /* - * Find the iotlbentry for ptr. This *must* be present in the TLB + * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB * because we just found the mapping. * TODO: Perhaps there should be a cputlb helper that returns a * matching tlb entry + iotlb entry. @@ -144,10 +144,10 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, g_assert(tlb_hit(comparator, ptr)); } # endif - iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + full =3D &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + if (!arm_tlb_mte_tagged(&full->attrs)) { return NULL; } =20 @@ -181,7 +181,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - iotlbentry->attrs, wp, ra); + full->attrs, wp, ra); } =20 /* @@ -202,11 +202,11 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, tag_access =3D=3D MMU_DATA_STORE, - iotlbentry->attrs); + full->attrs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index d6f7ef94fe..9cae8fd352 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5384,8 +5384,8 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, = CPUARMState *env, g_assert(tlb_hit(comparator, addr)); # endif =20 - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; - info->attrs =3D iotlbentry->attrs; + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + info->attrs =3D full->attrs; } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1b593ada36..305044a141 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14626,7 +14626,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) * table entry even for that case. */ return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs)); + arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)= ); #endif } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661187481; cv=none; d=zohomail.com; s=zohoarc; b=j+aOx8Si6YAldRraAhZNKgPABzyUZExwei2jF1R+wAicVisC8oNBXHBvdF85HXDR7uQiQQTi+drZx2K9QYjbuX5Od3DCg/Op9LQE4fhVEF7yUn2my12c5p/yG2ZNMJLZq60ILYT5V5kvn2WV2I7AUHkJZrXUCJIkomgpI+TLKek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661187481; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8ckYZp2ZvZbbjSC1kLgVsysS87kN66e9geBqNJpjIqo=; b=mjyCC5z0dkkd1DzfMYI+aBPuP7vDiiiY7rqSD9umpRnUICLuhmrtfmKIdOOqGAFNUI234eQjYddZy4u8QxpoOR6a1sLqdIuc1ndcrFz9WPgn+D+ricM/tC8nrIMUHBCgOyyNnut8VOTS16ZRWR3ukOVsy9TyDt+AKVLGYrZzogA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166118748182868.5002817803495; Mon, 22 Aug 2022 09:58:01 -0700 (PDT) Received: from localhost ([::1]:55554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAkS-0000Ri-N9 for importer@patchew.org; Mon, 22 Aug 2022 12:58:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Lz-0000mz-4F for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:39 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:39846) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Ld-0000ja-Rc for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:38 -0400 Received: by mail-pl1-x629.google.com with SMTP id d10so10236980plr.6 for ; Mon, 22 Aug 2022 08:28:17 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 1 - accel/tcg/cputlb.c | 7 +++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..9e47184513 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -218,7 +218,6 @@ struct CPUWatchpoint { * the memory regions get moved around by io_writex. */ typedef struct SavedIOTLB { - hwaddr addr; MemoryRegionSection *section; hwaddr mr_offset; } SavedIOTLB; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a37275bf8e..1509df96b4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1386,12 +1386,11 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBE= ntryFull *full, * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match * because of the side effect of io_writex changing memory layout. */ -static void save_iotlb_data(CPUState *cs, hwaddr addr, - MemoryRegionSection *section, hwaddr mr_offset) +static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, + hwaddr mr_offset) { #ifdef CONFIG_PLUGIN SavedIOTLB *saved =3D &cs->saved_iotlb; - saved->addr =3D addr; saved->section =3D section; saved->mr_offset =3D mr_offset; #endif @@ -1420,7 +1419,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryF= ull *full, * The memory_region_dispatch may trigger a flush/resize * so for plugins we save the iotlb_data just in case. */ - save_iotlb_data(cpu, full->xlat_section, section, mr_offset); + save_iotlb_data(cpu, section, mr_offset); =20 if (!qemu_mutex_iothread_locked()) { qemu_mutex_lock_iothread(); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661190563; cv=none; d=zohomail.com; s=zohoarc; b=Fp0YSJg5tt5sEszXgp5RnH/BuuG9BHSKmuDv76TqFO/LjShofGMUIF1dhX3YvY15K+kde49zIgpR0TE6CX53j/seCj7k5jPC7j1/EYNxRrnifUt/CH7XZ+WMHfATyCNLYRXO9Eew5FaMfpFnRSoDMjV55ZMP1DZrHm8hBcUWfVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661190563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AOC1J2N1TFaqmPODpiEeJvvId1/L1t5ozJ+BKFX5tCI=; b=XiQRc3kROqlKfnyvOyxJDOcO+qIn3KOS6Eh7HHGafARSaTjRISJoRxkqoRF6M26W+QC1Ya+l//5+MnxXFia56B19ecXHiOt1i3L/h7ZTo6pdEAoY2p2lI+WAqGELW4Uh/KXiCfVotLSI2eTmY+lq8Ge6PEjRCtrsM6DV1JqkQ7A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661190563767684.1261741391312; Mon, 22 Aug 2022 10:49:23 -0700 (PDT) Received: from localhost ([::1]:37382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBYA-0003GF-Dv for importer@patchew.org; Mon, 22 Aug 2022 13:49:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9M0-0000p7-Ga for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:40 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:37876) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Le-0000h5-Rt for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:28:40 -0400 Received: by mail-pf1-x42b.google.com with SMTP id x15so9774973pfp.4 for ; Mon, 22 Aug 2022 08:28:18 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id q7-20020a17090311c700b0016bffc59718sm8665222plh.58.2022.08.22.08.28.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:28:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=AOC1J2N1TFaqmPODpiEeJvvId1/L1t5ozJ+BKFX5tCI=; b=iIvxLrzj8WxzmdYfitz6DVTQo2olvu6icUB/p/DoRCUH67QB5rjnc4S5hbAwU5iUXh vizwayS9shWSKQ+MUkki9pqv2B3gBZeSJtOe1rADfyNgW948xljZ5HeRLwy0ccnASec7 Zdbpdi2lxZQImaxDd0+JaQH/RW1+ZqNSEeLfaAy4t8/rKepiqeic+RfICdWmE7ecMpeU KkKSRUp98G9gUH4f0T5MfsMLp4d9gqQxVo7HnenbOzIrxv7X7o/xBRkPsvrXmex84U9R vgTbd/QIibgpx2GEDaPRc/8OQnCm23/n6sybFtNRhL27VZy6aSFvvya84rdE6eQJbAds 90uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=AOC1J2N1TFaqmPODpiEeJvvId1/L1t5ozJ+BKFX5tCI=; b=2e8GsdIqrhb8sAeMaUBIv0WgpITeM/IYdDSfSmbmJRcKSPVDI08v71cRBkhdxDTMzV w3PQW6g2fXXVuFH5/ggKszqDMWyYVyvj3MW/3z6I/mMEFgbEAhkSH7FIfIxTqVQS/L70 MTUam4pmNa/Ouy6onbfrgtGs7GWuwHfkpTatyzCKomeUzCJ74wFkceq1KJ2/2REF1Z1u sJLUoFc62ap8Ji2XLsZOfsa/Q6QugrEOht6KRExbMxXNaI9a9YEeteAlk33XDHI50f7G gXU+AmqXqZ+PCWiCp1orUgjVBMLqoqsOlMC07iOJ9sqE1BmS7XVHIUd1JwyVWZOGRuXG o+fw== X-Gm-Message-State: ACgBeo1t+gJ+G5aqJ7uC0MmiYspA6f3BBonM408ChByHVc2rCnyTe/9q 8EC0HR7SekpjMGNxAwMU85wDIeHdXqZaNA== X-Google-Smtp-Source: AA6agR5wfRLOHq3Rukf+PcByaduGDyq6SwchzYlGJuPy3SRhJxZHqkar+L+jTIn2ydwhQg4hr18ZVQ== X-Received: by 2002:a05:6a00:1883:b0:536:e59f:f776 with SMTP id x3-20020a056a00188300b00536e59ff776mr1086800pfh.49.1661182098016; Mon, 22 Aug 2022 08:28:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Hildenbrand Subject: [PATCH v2 39/66] accel/tcg: Suppress auto-invalidate in probe_access_internal Date: Mon, 22 Aug 2022 08:27:14 -0700 Message-Id: <20220822152741.1617527-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661190565734100001 Content-Type: text/plain; charset="utf-8" When PAGE_WRITE_INV is set when calling tlb_set_page, we immediately set TLB_INVALID_MASK in order to force tlb_fill to be called on the next lookup. Here in probe_access_internal, we have just called tlb_fill and eliminated true misses, thus the lookup must be valid. This allows us to remove a warning comment from s390x. There doesn't seem to be a reason to change the code though. Cc: David Hildenbrand Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 10 +++++++++- target/s390x/tcg/mem_helper.c | 4 ---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 1509df96b4..5359113e8d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1602,6 +1602,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); =20 + flags =3D TLB_FLAGS_MASK; page_addr =3D addr & TARGET_PAGE_MASK; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { @@ -1617,10 +1618,17 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, =20 /* TLB resize via tlb_fill may have moved the entry. */ entry =3D tlb_entry(env, mmu_idx, addr); + + /* + * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, + * to force the next access through tlb_fill. We've just + * called tlb_fill, so we know that this entry *is* valid. + */ + flags &=3D ~TLB_INVALID_MASK; } tlb_addr =3D tlb_read_ofs(entry, elt_ofs); } - flags =3D tlb_addr & TLB_FLAGS_MASK; + flags &=3D tlb_addr; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index fc52aa128b..3758b9e688 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -148,10 +148,6 @@ static int s390_probe_access(CPUArchState *env, target= _ulong addr, int size, #else int flags; =20 - /* - * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr= =3D=3DNULL - * to detect if there was an exception during tlb_fill(). - */ env->tlb_fill_exc =3D 0; flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nonfault= , phost, ra); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661191764; cv=none; d=zohomail.com; s=zohoarc; b=f6mt/vDrFQod6WBmsWKCLeNWWWgS+mdK1K1xFU8hjrou9LT6/fAnfknaIA+2ZzIL4YrggRH8/5m1GALDov83RuoHELpvsV3fXY+CUSIkRgpM0myUv8Ex/PAsJvp1rFyvn9IAOmyNktANG4DLhGtcQ6aOTVj74+jKKnqPltySU1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661191764; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sLuofTzD3XcbGEKkxECtfxPk5kwjXiJfOftJpAZ8w/Y=; b=WgQtlxl2ZnU2B93XjqxaYRnpXE9Q17IfGNfP8YT7cy2HsMlmU6lc4uH/5aACaihhYJMx52IexyMGPpFujfsnu81ByBVgLhYVgxkEihFNmVFUrD8OhQHupRmmUL1AA99NPIMQpmnNihaFrEPQY6wKeuFTqLM7fiFqGfxDjyvKNeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661191764819302.19387513939114; Mon, 22 Aug 2022 11:09:24 -0700 (PDT) Received: from localhost ([::1]:33570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBrX-00020e-D7 for importer@patchew.org; Mon, 22 Aug 2022 14:09:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Of-0004dQ-S7 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:28 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:37385) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Od-0001ad-P6 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:25 -0400 Received: by mail-pf1-x42d.google.com with SMTP id x15so9783310pfp.4 for ; Mon, 22 Aug 2022 08:31:20 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=sLuofTzD3XcbGEKkxECtfxPk5kwjXiJfOftJpAZ8w/Y=; b=eY0jKCOi/0F6BnqLwWgsFl7dY2JIWefv5PgviFwo07jZhw+hnX20H9bXyBAC5UA/ig kKqEdmzo1xAbUH4IVm8+LQv2aKFx9WGImc0BPF4KBvzdL0jhUwk+ipCPfORK8N/uFfi4 JuFRH/XZFyLDaLpxn89ej8tPGbAGg3GGE7czY5IkX0AwVuVg/1nRIk8DB+/fmccEK2PJ CZmVkFrQvExevpBD4lnUwOGkYzT1uySJrF0he/G7Movr38iY0jsf6SNqPFEluAHMNJ6c JMqTOgu61bHKsWtr7iKqVKSu0LemQvPkYLdw6vvCdnU7BDuQMIrv/7zgA103bpY8hXuc iDDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=sLuofTzD3XcbGEKkxECtfxPk5kwjXiJfOftJpAZ8w/Y=; b=DGYUqAyJbSsJjHsf2xaFoWXtbb/IrzIFMFbOS363jWJBgUOGrv16moYhkyXOydsDoK He7yoA8aVG2cPWrx9b14tfoheS87sbWwMfyNs95NN8GJspNgqlTPpbwEp3J6Vt37t42m TY0PVgSNBpfHTYB4SwLpUbFz5JNS3CtAk+1kCh0QHfaSr9yX60CDemdqnT0b9DtWPQyl L1owfOfbVubsBPGg6iFLJEB3ouvDBkdzb6XghN1P4cGUWtFnqGR1501pLTNgez+Nx4Dc 5WWIOhLnOK52PCHekRaX+civiDEd9t0fSutNbflFfoAyJq7bhw+yWojgu6uNAlVNS29A K4mQ== X-Gm-Message-State: ACgBeo3BD2WnLeWp3cwgCHcW73JEJM3TYF3MaDQRFU4lmpOdxSqa+drU NdjHhVMOc0Bbgi+/trBuCGw2M+Qvy/LHaQ== X-Google-Smtp-Source: AA6agR6czH8Mft8TafQKJto6R+8+b33d5nN6xsUeqQ+urCIJ8iR5NrrXVzuoTZ+S0FdoSrscqBl0fw== X-Received: by 2002:a05:6a00:1a49:b0:52d:4ad7:3bea with SMTP id h9-20020a056a001a4900b0052d4ad73beamr21749452pfv.66.1661182279316; Mon, 22 Aug 2022 08:31:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 40/66] accel/tcg: Introduce probe_access_full Date: Mon, 22 Aug 2022 08:27:15 -0700 Message-Id: <20220822152741.1617527-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661191765602100001 Content-Type: text/plain; charset="utf-8" Add an interface to return the CPUTLBEntryFull struct that goes with the lookup. The result is not intended to be valid across multiple lookups, so the user must use the results immediately. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 11 +++++++++++ accel/tcg/cputlb.c | 44 +++++++++++++++++++++++++---------------- 2 files changed, 38 insertions(+), 17 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 311e5fb422..e366b5c1ba 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -435,6 +435,17 @@ int probe_access_flags(CPUArchState *env, target_ulong= addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 +#ifndef CONFIG_USER_ONLY +/** + * probe_access_full: + * Like probe_access_flags, except also return into @pfull. + */ +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, + CPUTLBEntryFull **pfull, uintptr_t retaddr); +#endif + #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 /* Estimated block size for TB allocation. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5359113e8d..1c59e701e6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1579,7 +1579,8 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, static int probe_access_internal(CPUArchState *env, target_ulong addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, - void **phost, uintptr_t retaddr) + void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); @@ -1613,10 +1614,12 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; + *pfull =3D NULL; return TLB_INVALID_MASK; } =20 /* TLB resize via tlb_fill may have moved the entry. */ + index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); =20 /* @@ -1630,6 +1633,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } flags &=3D tlb_addr; =20 + *pfull =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { *phost =3D NULL; @@ -1641,37 +1646,44 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, return flags; } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, - MMUAccessType access_type, int mmu_idx, - bool nonfault, void **phost, uintptr_t retaddr) +int probe_access_full(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, CPUTLBEntryFull **pfull, + uintptr_t retaddr) { - int flags; - - flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, - nonfault, phost, retaddr); + int flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, + nonfault, phost, pfull, retaddr); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - - notdirty_write(env_cpu(env), addr, 1, full, retaddr); + notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr); flags &=3D ~TLB_NOTDIRTY; } =20 return flags; } =20 +int probe_access_flags(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, uintptr_t retaddr) +{ + CPUTLBEntryFull *full; + + return probe_access_full(env, addr, access_type, mmu_idx, + nonfault, phost, &full, retaddr); +} + void *probe_access(CPUArchState *env, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { + CPUTLBEntryFull *full; void *host; int flags; =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - false, &host, retaddr); + false, &host, &full, retaddr); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1679,9 +1691,6 @@ void *probe_access(CPUArchState *env, target_ulong ad= dr, int size, } =20 if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - /* Handle watchpoints. */ if (flags & TLB_WATCHPOINT) { int wp_access =3D (access_type =3D=3D MMU_DATA_STORE @@ -1702,11 +1711,12 @@ void *probe_access(CPUArchState *env, target_ulong = addr, int size, void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, MMUAccessType access_type, int mmu_idx) { + CPUTLBEntryFull *full; void *host; int flags; =20 flags =3D probe_access_internal(env, addr, 0, access_type, - mmu_idx, true, &host, 0); + mmu_idx, true, &host, &full, 0); =20 /* No combination of flags are expected by the caller. */ return flags ? NULL : host; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661192622; cv=none; d=zohomail.com; s=zohoarc; b=Hy91hV2XH5AWAs05qawi7hEUHXcXYGrJ9blM5EShHmk43LnySspLQgUWY32W/Vuaf3ZpIJNCIpyRbraBdDw4Y3O/mcwvXnDsmov5IYQ70wEIcn3GiMq0l8DAmaSBRxF8cnvsEnQRHlOU42S6WqI1SMNPf2jKk13rPrN6DvrZcw0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661192622; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y/iSNxff4IufTYAu9VatBCHbVe/4R7TVJMkL2BFBTek=; b=SaWp8sdyPgVu7HCHdweWajmzCwtCs3fVMy3209aQq5TJ3cMsR2pjGvzlJhXjqmQ4FPHasiR8e10q32bTopbunhei/SRMw69wkXg+VP3m6k6TQk/8lCAZ0SJkEYQ8s898DPnSS/ofKyeQnTO27GzHgtfDy0Pl1E4FTLqnG15qcl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661192622090352.0800679633244; Mon, 22 Aug 2022 11:23:42 -0700 (PDT) Received: from localhost ([::1]:55920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQC5L-0005pd-U7 for importer@patchew.org; Mon, 22 Aug 2022 14:23:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Of-0004dS-TC for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:28 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:38420) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oc-0001am-5w for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:25 -0400 Received: by mail-pj1-x102b.google.com with SMTP id s31-20020a17090a2f2200b001faaf9d92easo14332503pjd.3 for ; Mon, 22 Aug 2022 08:31:21 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=y/iSNxff4IufTYAu9VatBCHbVe/4R7TVJMkL2BFBTek=; b=xdStfUhvm4atoaStF51HDeAMRT6dXZTSmfD3Wq1S5cPom30zGwRFs83NFzBa3ABgTq KBAg2PY6mL9WbG068eRE+jcEzmcL/jvCi/Q+ouhcvfpDzJyz8aOIRsx3WT/JkxkdeR5S Cx168Y2SOL/ARd5HsnSVD8+r+3VwBS3eQDpeK1tfvH3PUWYH1CCRcLFJFQt9kJ4pwIm7 XOaF2dzah9SAIKeuZYzI7j9V4JBPbg9wv6IsxpGmLm5TP1Rs7u3wJe91tDH8lDtx+g9M HiRdqdaSbYLDHqb+WMGjPW9hBWmFMd4PpITXDnrmcyC8jP8gnr+WQI9g8Ww2L7ZFHBE2 xgDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=y/iSNxff4IufTYAu9VatBCHbVe/4R7TVJMkL2BFBTek=; b=Jkt1TBBQNPFh90bD2djE0V2fU+ec8NxAvLRT+HMKocb60XagsPv3d1PqdP0im5/uFR B/B+dTXhLPJ+Igwz7adcV3ZU/BNKE1+FJUlqjpTixsllazu9IMXbgXKKG8Zd/Et7sxpV 6qAO8loQa6HvO4caAzqmbNF3Gh+Us5wlAgOCjESqUOhFYvjg06opglrOTzXFB8bQGflJ ipXwSf3atsl+E3W+1GxDhnoZQCSPAIGbqIiVQyuX2oWfFykxK8gwhQ0GSubRyq78KAr5 TTNOhE9Su7Jh72HXiw5wIA+GCkEJedmzWArCmcM8LiDts9MD7mVEVzJmr40bRhFIAFKS xOlQ== X-Gm-Message-State: ACgBeo3ytbO0LCiasN+Tt3qoFlCkzKqnbUCR9eXprcLZLPEJ01/3JjpJ tXZSg7rhx+0hQrkD+7Maj1Nix9DQSNDpfA== X-Google-Smtp-Source: AA6agR6WPlYIOyHqSxQtvZkm2v8/De00nt3pg9TXXoGr0+0R8MOjX6XHZUPYqWD8fGaFRcTajEdcEQ== X-Received: by 2002:a17:902:7c01:b0:16f:9649:be73 with SMTP id x1-20020a1709027c0100b0016f9649be73mr20470928pll.70.1661182280432; Mon, 22 Aug 2022 08:31:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 41/66] accel/tcg: Introduce tlb_set_page_full Date: Mon, 22 Aug 2022 08:27:16 -0700 Message-Id: <20220822152741.1617527-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661192624204100001 Content-Type: text/plain; charset="utf-8" Now that we have collected all of the page data into CPUTLBEntryFull, provide an interface to record that all in one go, instead of using 4 arguments. This interface allows CPUTLBEntryFull to be extended without having to change the number of arguments. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 14 ++++++++++ include/exec/exec-all.h | 22 +++++++++++++++ accel/tcg/cputlb.c | 61 +++++++++++++++++++++++++++-------------- 3 files changed, 77 insertions(+), 20 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index f70f54d850..5e12cc1854 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -148,7 +148,21 @@ typedef struct CPUTLBEntryFull { * + the offset within the target MemoryRegion (otherwise) */ hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; } CPUTLBEntryFull; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index e366b5c1ba..e7b54e8e5c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -258,6 +258,28 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @vaddr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->ld_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, + CPUTLBEntryFull *full); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 1c59e701e6..8c95f57266 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,16 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_full(CPUState *cpu, int mmu_idx, + target_ulong vaddr, CPUTLBEntryFull *full) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); @@ -1117,35 +1117,36 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; target_ulong vaddr_page; - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - int wp_flags; + int asidx, wp_flags, prot; bool is_ram, is_romd; =20 assert_cpu_is_self(cpu); =20 - if (size <=3D TARGET_PAGE_SIZE) { + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { sz =3D TARGET_PAGE_SIZE; } else { - tlb_add_large_page(env, mmu_idx, vaddr, size); - sz =3D size; + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(env, mmu_idx, vaddr, sz); } vaddr_page =3D vaddr & TARGET_PAGE_MASK; - paddr_page =3D paddr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; =20 + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, attrs, &prot); + &xlat, &sz, full->attrs, &= prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx " prot=3D%x idx=3D%d\n", - vaddr, paddr, prot, mmu_idx); + vaddr, full->phys_addr, prot, mmu_idx); =20 address =3D vaddr_page; - if (size < TARGET_PAGE_SIZE) { + if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ address |=3D TLB_INVALID_MASK; } - if (attrs.byte_swap) { + if (full->attrs.byte_swap) { address |=3D TLB_BSWAP; } =20 @@ -1236,8 +1237,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, * subtract here is that of the page base, and not the same as the * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ + desc->fulltlb[index] =3D *full; desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; - desc->fulltlb[index].attrs =3D attrs; + desc->fulltlb[index].prot =3D prot; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1272,15 +1274,34 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, qemu_spin_unlock(&tlb->c.lock); } =20 -/* Add a new TLB entry, but without specifying the memory - * transaction attributes to be used. - */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D attrs, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); +} + void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size) { - tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED, - prot, mmu_idx, size); + CPUTLBEntryFull full =3D { + .phys_addr =3D paddr, + .attrs =3D MEMTXATTRS_UNSPECIFIED, + .prot =3D prot, + .lg_page_size =3D ctz64(size) + }; + + assert(is_power_of_2(size)); + tlb_set_page_full(cpu, mmu_idx, vaddr, &full); } =20 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661188706; cv=none; d=zohomail.com; s=zohoarc; b=m8wxd7ENMSigO/sQqv9hlBbEBvASyQUlzOuLgg1PJgJsDLBnU1BbGHtsYOpLyUVA/4B8vWBlQpuhAtVlFWRCo7ulewVIMk0+JgTAJ4t6AojUMyhovR5UijYfhhBDOk3ejuDEpXLqv+RHPyWbnPjE35UnjfOccVvZbggp8Ey+Y08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661188706; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DXX8xFRgoLfGrBLoJgCHBIES2WAuCLiCftR5z1MDZC4=; b=vX7tvs6PNftA4IM3kWT08DWV7XYyYwTEE7vuMrZTwHNZ8TKl6YsSLC2ydWdGSaM2Cl HWCq+X7Y9lLTasBv8hjC8ElqMsAHm72GUfpeSVRqldzIhIWzuN5mHdwaNFpYTXky46pk 5PS4RvswMQdQYJHr4rBiEr5V5YqvpK+/veGoaXb1AD84duzR//QtL+7Vs9Y5CS4QmH1K xpDdD5hj8MJFv9LGnfjiYUERXwyLnoNnh6fdWV9YMLJLHrvWqb7AQJmrKOnP5rPXW0AR +zGVgaylMgDpAEx5NzgF5dNwk5MWvB01R+zul64UQqww6aBvtulqLawgn0Fvo3b5M8vl LuFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DXX8xFRgoLfGrBLoJgCHBIES2WAuCLiCftR5z1MDZC4=; b=uhUiav46KGWr9JvQu/xJUkO0snPTH3DiX/RfEOlZBwTq6sSXuk0wTcNuat9huWDQvL gWOmlndYNY1Wx2WvZBnLg07Ot82qwvz5DkyDOEMfz16eaV9cBEhdFxjuEHK5NGAtPrCm Am2TYlgpPhQ18SZwTh5SrNftqN3KKms5gt+e+QZyQRM5nzNZitYV2ZyyLB0o8whyp/sk Ap/QMrhps7dCQYIJnaUmfHzR2N7oFG3IeMqSOSgV2nDyaQ3If2xNcPj+/fqP0oCprzPI N4J6rFeNozFXkccadZzNJqUkp2Bkz3nhSbJpHuLytvrvNZBmdCHg6tXC76CIvAvcI5EJ cZhQ== X-Gm-Message-State: ACgBeo2FYNuau7JFJqdCI35ivTS/JtdgopxlNAevez1HUYb1PQ3HajwD eAZbgakuOZXYnnj/XD6pMjUQojTm+EnVJg== X-Google-Smtp-Source: AA6agR67w8ds/+uspy73jIGIiBoGCKOUzCWsP2mBZ/eq1lXsGM+ksFUWAiYFbNKV7KJrzkwYAbvpxw== X-Received: by 2002:a63:2b02:0:b0:41d:9b5e:7d69 with SMTP id r2-20020a632b02000000b0041d9b5e7d69mr17083387pgr.165.1661182281250; Mon, 22 Aug 2022 08:31:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 42/66] target/arm: Use tlb_set_page_full Date: Mon, 22 Aug 2022 08:27:17 -0700 Message-Id: <20220822152741.1617527-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661188709420100001 Content-Type: text/plain; charset="utf-8" Adjust GetPhysAddrResult to fill in CPUTLBEntryFull, so that it may be passed directly to tlb_set_page_full. The change is large, but mostly mechanical. The major non-mechanical change is page_size -> lg_page_size. Most of the time this is obvious, and is related to TARGET_PAGE_BITS. Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 +- target/arm/helper.c | 12 +-- target/arm/m_helper.c | 20 ++--- target/arm/ptw.c | 181 ++++++++++++++++++++-------------------- target/arm/tlb_helper.c | 9 +- 5 files changed, 112 insertions(+), 115 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a21a21299c..e914227e55 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1071,10 +1071,7 @@ typedef struct ARMCacheAttrs { =20 /* Fields that are valid upon success. */ typedef struct GetPhysAddrResult { - hwaddr phys; - target_ulong page_size; - int prot; - MemTxAttrs attrs; + CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; } GetPhysAddrResult; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 55355197b8..887f613b40 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3237,8 +3237,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, /* Create a 64-bit PAR */ par64 =3D (1 << 11); /* LPAE bit always set */ if (!ret) { - par64 |=3D res.phys & ~0xfffULL; - if (!res.attrs.secure) { + par64 |=3D res.f.phys_addr & ~0xfffULL; + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ @@ -3262,13 +3262,13 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, */ if (!ret) { /* We do not set any attribute bits in the PAR */ - if (res.page_size =3D=3D (1 << 24) + if (res.f.lg_page_size =3D=3D 24 && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (res.phys & 0xff000000) | (1 << 1); + par64 =3D (res.f.phys_addr & 0xff000000) | (1 << 1); } else { - par64 =3D res.phys & 0xfffff000; + par64 =3D res.f.phys_addr & 0xfffff000; } - if (!res.attrs.secure) { + if (!res.f.attrs.secure) { par64 |=3D (1 << 9); /* NS */ } } else { diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 203ba411f6..355cd4d60a 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -223,8 +223,8 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr,= uint32_t value, } goto pend_fault; } - address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value, - res.attrs, &txres); + address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_add= r, + value, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to write the data */ if (mode =3D=3D STACK_LAZYFP) { @@ -298,8 +298,8 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest,= uint32_t addr, goto pend_fault; } =20 - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); @@ -2022,8 +2022,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); return false; } - *insn =3D address_space_lduw_le(arm_addressspace(cs, res.attrs), res.p= hys, - res.attrs, &txres); + *insn =3D address_space_lduw_le(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); @@ -2069,8 +2069,8 @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMM= UIdx mmu_idx, } return false; } - value =3D address_space_ldl(arm_addressspace(cs, res.attrs), res.phys, - res.attrs, &txres); + value =3D address_space_ldl(arm_addressspace(cs, res.f.attrs), + res.f.phys_addr, res.f.attrs, &txres); if (txres !=3D MEMTX_OK) { /* BusFault trying to read the data */ qemu_log_mask(CPU_LOG_INT, @@ -2817,8 +2817,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } else { mrvalid =3D true; } - r =3D res.prot & PAGE_READ; - rw =3D res.prot & PAGE_WRITE; + r =3D res.f.prot & PAGE_READ; + rw =3D res.f.prot & PAGE_WRITE; } else { r =3D false; rw =3D false; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fa76f98b04..dafbf71d00 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -256,7 +256,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, assert(!is_secure); } =20 - addr =3D s2.phys; + addr =3D s2.f.phys_addr; } return addr; } @@ -476,7 +476,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* 1Mb section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); ap =3D (desc >> 10) & 3; - result->page_size =3D 1024 * 1024; + result->f.lg_page_size =3D 20; /* 1MB */ } else { /* Lookup l2 entry. */ if (type =3D=3D 1) { @@ -497,12 +497,12 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ if (type =3D=3D 1) { @@ -510,7 +510,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, if (arm_feature(env, ARM_FEATURE_XSCALE) || arm_feature(env, ARM_FEATURE_V6)) { phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; } else { /* * UNPREDICTABLE in ARMv5; we choose to take a @@ -521,7 +521,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, } } else { phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - result->page_size =3D 0x400; + result->f.lg_page_size =3D 10; } ap =3D (desc >> 4) & 3; break; @@ -530,14 +530,14 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32= _t address, g_assert_not_reached(); } } - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - result->prot |=3D result->prot ? PAGE_EXEC : 0; - if (!(result->prot & (1 << access_type))) { + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot |=3D result->f.prot ? PAGE_EXEC : 0; + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -607,11 +607,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - result->page_size =3D 0x1000000; + result->f.lg_page_size =3D 24; /* 16MB */ } else { /* Section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - result->page_size =3D 0x100000; + result->f.lg_page_size =3D 20; /* 1MB */ } ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); @@ -636,12 +636,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); xn =3D desc & (1 << 15); - result->page_size =3D 0x10000; + result->f.lg_page_size =3D 16; break; case 2: case 3: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); xn =3D desc & 1; - result->page_size =3D 0x1000; + result->f.lg_page_size =3D 12; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -649,7 +649,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, } } if (domain_prot =3D=3D 3) { - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; @@ -667,14 +667,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, fi->type =3D ARMFault_AccessFlag; goto do_fault; } - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->f.prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot= ); } - if (result->prot && !xn) { - result->prot |=3D PAGE_EXEC; + if (result->f.prot && !xn) { + result->f.prot |=3D PAGE_EXEC; } - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -685,9 +685,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } - result->phys =3D phys_addr; + result->f.phys_addr =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -1298,16 +1298,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; xn =3D extract32(attrs, 11, 2); - result->prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { ns =3D extract32(attrs, 3, 1); xn =3D extract32(attrs, 12, 1); pxn =3D extract32(attrs, 11, 1); - result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 fault_type =3D ARMFault_Permission; - if (!(result->prot & (1 << access_type))) { + if (!(result->f.prot & (1 << access_type))) { goto do_fault; } =20 @@ -1317,11 +1317,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(&result->attrs) =3D true; + arm_tlb_bti_gp(&result->f.attrs) =3D true; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { @@ -1347,8 +1347,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->cacheattrs.shareability =3D extract32(attrs, 6, 2); } =20 - result->phys =3D descaddr; - result->page_size =3D page_size; + result->f.phys_addr =3D descaddr; + result->f.lg_page_size =3D ctz64(page_size); return false; =20 do_fault: @@ -1373,12 +1373,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } =20 - result->phys =3D address; + result->f.phys_addr =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; if ((base & 1) =3D=3D 0) { @@ -1414,16 +1414,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 2: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; if (!is_user) { - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; } break; case 3: - result->prot =3D PAGE_READ | PAGE_WRITE; + result->f.prot =3D PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1431,10 +1431,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; case 6: - result->prot =3D PAGE_READ; + result->f.prot =3D PAGE_READ; break; default: /* Bad permission. */ @@ -1442,12 +1442,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - result->prot |=3D PAGE_EXEC; + result->f.prot |=3D PAGE_EXEC; return false; } =20 static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_i= dx, - int32_t address, int *prot) + int32_t address, uint8_t *prot) { if (!arm_feature(env, ARM_FEATURE_M)) { *prot =3D PAGE_READ | PAGE_WRITE; @@ -1531,9 +1531,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, int n; bool is_user =3D regime_is_user(env, mmu_idx); =20 - result->phys =3D address; - result->page_size =3D TARGET_PAGE_SIZE; - result->prot =3D 0; + result->f.phys_addr =3D address; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.prot =3D 0; =20 if (regime_translation_disabled(env, mmu_idx, secure) || m_is_ppb_region(env, address)) { @@ -1545,7 +1545,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, * which always does a direct read using address_space_ldl(), rath= er * than going via this function, so we don't need to check that he= re. */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ @@ -1587,7 +1587,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, if (ranges_overlap(base, rmask, address & TARGET_PAGE_MASK, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } @@ -1625,7 +1625,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, continue; } if (rsize < TARGET_PAGE_BITS) { - result->page_size =3D 1 << rsize; + result->f.lg_page_size =3D rsize; } break; } @@ -1636,7 +1636,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ui= nt32_t address, fi->type =3D ARMFault_Background; return true; } - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->p= rot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, + &result->f.prot); } else { /* a MPU hit! */ uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); @@ -1653,16 +1654,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 5: break; /* no access */ case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 2: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1678,16 +1679,16 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, case 1: case 2: case 3: - result->prot |=3D PAGE_WRITE; + result->f.prot |=3D PAGE_WRITE; /* fall through */ case 5: case 6: - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; case 7: /* for v7M, same as 6; for R profile a reserved value = */ if (arm_feature(env, ARM_FEATURE_M)) { - result->prot |=3D PAGE_READ | PAGE_EXEC; + result->f.prot |=3D PAGE_READ | PAGE_EXEC; break; } /* fall through */ @@ -1700,14 +1701,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 /* execute never */ if (xn) { - result->prot &=3D ~PAGE_EXEC; + result->f.prot &=3D ~PAGE_EXEC; } } } =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, @@ -1732,9 +1733,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); =20 - result->page_size =3D TARGET_PAGE_SIZE; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D TARGET_PAGE_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; if (mregion) { *mregion =3D -1; } @@ -1784,13 +1785,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, ranges_overlap(base, limit - base + 1, addr_page_base, TARGET_PAGE_SIZE)) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } continue; } =20 if (base > addr_page_base || limit < addr_page_limit) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } =20 if (matchregion !=3D -1) { @@ -1816,7 +1817,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot); + get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); @@ -1831,9 +1832,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (result->prot && !xn && !(pxn && !is_user)) { - result->prot |=3D PAGE_EXEC; + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (result->f.prot && !xn && !(pxn && !is_user)) { + result->f.prot |=3D PAGE_EXEC; } /* * We don't need to look the attribute up in the MAIR0/MAIR1 @@ -1846,7 +1847,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->prot & (1 << access_type)); + return !(result->f.prot & (1 << access_type)); } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2010,9 +2011,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } else { fi->type =3D ARMFault_QEMU_SFault; } - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } else { @@ -2022,7 +2023,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { - result->attrs.secure =3D false; + result->f.attrs.secure =3D false; } else if (!secure) { /* * NS access to S memory must fault. @@ -2035,9 +2036,9 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ fi->type =3D ARMFault_QEMU_SFault; - result->page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZ= E; - result->phys =3D address; - result->prot =3D 0; + result->f.lg_page_size =3D sattrs.subpage ? 0 : TARGET_PAG= E_BITS; + result->f.phys_addr =3D address; + result->f.prot =3D 0; return true; } } @@ -2046,7 +2047,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { - result->page_size =3D 1; + result->f.lg_page_size =3D 0; } return ret; } @@ -2353,9 +2354,9 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, break; } =20 - result->phys =3D address; - result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.phys_addr =3D address; + result->f.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->f.lg_page_size =3D TARGET_PAGE_BITS; result->cacheattrs.is_s2_format =3D false; result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; @@ -2416,10 +2417,10 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, return ret; } =20 - ipa =3D result->phys; + ipa =3D result->f.phys_addr; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ - ipa_secure =3D !(result->attrs.secure + ipa_secure =3D !(result->f.attrs.secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW); } else { @@ -2434,7 +2435,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * Save the stage1 results so that we may merge * prot and cacheattrs later. */ - s1_prot =3D result->prot; + s1_prot =3D result->f.prot; cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 @@ -2443,7 +2444,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->prot &=3D s1_prot; + result->f.prot &=3D s1_prot; =20 /* If S2 fails, return early. */ if (ret) { @@ -2471,10 +2472,10 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, /* Check if IPA translates to secure or non-secure PA space. */ if (is_secure) { if (ipa_secure) { - result->attrs.secure =3D + result->f.attrs.secure =3D !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); } else { - result->attrs.secure =3D + result->f.attrs.secure =3D !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } @@ -2493,8 +2494,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, * cannot upgrade an non-secure translation regime's attributes * to secure. */ - result->attrs.secure =3D is_secure; - result->attrs.user =3D regime_is_user(env, mmu_idx); + result->f.attrs.secure =3D is_secure; + result->f.attrs.user =3D regime_is_user(env, mmu_idx); =20 /* * Fast Context Switch Extension. This doesn't exist at all in v8. @@ -2511,7 +2512,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, =20 if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; - result->page_size =3D TARGET_PAGE_SIZE; + result->f.lg_page_size =3D TARGET_PAGE_BITS; =20 if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ @@ -2532,9 +2533,9 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), (uint32_t)address, mmu_idx, ret ? "Miss" : "Hit", - result->prot & PAGE_READ ? 'r' : '-', - result->prot & PAGE_WRITE ? 'w' : '-', - result->prot & PAGE_EXEC ? 'x' : '-'); + result->f.prot & PAGE_READ ? 'r' : '-', + result->f.prot & PAGE_WRITE ? 'w' : '-', + result->f.prot & PAGE_EXEC ? 'x' : '-'); =20 return ret; } @@ -2609,10 +2610,10 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *= cs, vaddr addr, bool ret; =20 ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi); - *attrs =3D res.attrs; + *attrs =3D res.f.attrs; =20 if (ret) { return -1; } - return res.phys; + return res.f.phys_addr; } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index ad225b1cb2..49601394ec 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -227,17 +227,16 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, * target page size are handled specially, so for those we * pass in the exact addresses. */ - if (res.page_size >=3D TARGET_PAGE_SIZE) { - res.phys &=3D TARGET_PAGE_MASK; + if (res.f.lg_page_size >=3D TARGET_PAGE_BITS) { + res.f.phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } /* Notice and record tagged memory. */ if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { - arm_tlb_mte_tagged(&res.attrs) =3D true; + arm_tlb_mte_tagged(&res.f.attrs) =3D true; } =20 - tlb_set_page_with_attrs(cs, address, res.phys, res.attrs, - res.prot, mmu_idx, res.page_size); + tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; } else if (probe) { return false; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661192109; cv=none; d=zohomail.com; s=zohoarc; b=hLvv/WKp8qtfrUuw/sXm7mbl/ib3UwL/v3Q4gSuaieCi1J9dOmQDoAyHnp6BjbNjlssljLCtFFeFGzhAQMsXSuc2YfAPCiPrgY5DW7aH+hDRfJUnVn+qZnQ3wMOEvVFFykyAR0xoUu7hEER2sma1L/cqK72gfvsG1WaTvkgNUNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661192109; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L7q2sisR9jXPO2g1tObtbxm8Q6qrnHqWQnHO8ESVRzQ=; b=XUkQ8ge/FJ0A97JvixxTLKMGY3RyN7+6L7M4kMABXQWzoF7sD1nNYqcwgCQlbMxghAHhGAbSADsGzLOyBthEAqW+r6mTwhjAKBP9RMBokX0AIKJXBZlErQuiLkkirtfEYbmtJEDspiyUx+Y1Jg74Fil97I1/pcybmNlqci7u+vI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661192109125124.46071834709892; Mon, 22 Aug 2022 11:15:09 -0700 (PDT) Received: from localhost ([::1]:49676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBx4-0008Ce-6B for importer@patchew.org; Mon, 22 Aug 2022 14:15:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Og-0004dT-MZ for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:28 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:36355) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Od-0001bN-Q3 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:26 -0400 Received: by mail-pl1-x62d.google.com with SMTP id c2so10258108plo.3 for ; Mon, 22 Aug 2022 08:31:22 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=L7q2sisR9jXPO2g1tObtbxm8Q6qrnHqWQnHO8ESVRzQ=; b=uNxbfM1LG+tkQwT2rbn07Zh7psqGNLMvTCti+0WRgNFkXLbuSUyqETrHtr7TdfYxDe 428itT65OgxjTCHR8iZYXGSKdoyd2jq1VTnCSQJqt1+ukIF/kZG0mKfHlfus5kOPI5Ka KIOWCPZ0Oh28Tw0sYiOkklN55wi2OLAd4a1909QdcEUBsJcpg4erGyGzQi016VqRJ0Aj bHTGG0j2h9UrYGAjsCHCN/EbJYu7ekfY8zsVXeCMnmnBtkFe6NO4jduekuu9PUPG9C00 fQYHjqXTkMRiFpSZZbk8jHCKKP0LeQL8MwXnY/lAD6J6vf1NPPzGvPR/3Tl7AyusmF8L HUjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=L7q2sisR9jXPO2g1tObtbxm8Q6qrnHqWQnHO8ESVRzQ=; b=1o193EGM4oo0av5xwdMWVdUa1KcBhQ6/2ZK0kucaDLojF6vIuZFX3powOwYCZXRZYg MRw7327I/TI+zq9lQWCwBdEDvj4rpVjaplo0ahRyCPe+7Lvtt15Vodugftje3/RmAdO7 HJK0l0+plsxpj71QbWIhvq3nvp6icNB8uat2jNGlcP1rl7VKmjj9GYBnKn+wRY6/arWX YK3Zqw+LtkZLLtXfk1CpznytbYYsmlnuM66n/fmgoLOmLGowgycQU0kucDTLNImf3h1j E6gDMkJEJahe9TT2DxWqHP6vkfQZjNjd7qA9WfPysg8FPy7cO8/kARQutgHZUw5qxJXU 2+5g== X-Gm-Message-State: ACgBeo141lqlHfTWZNdB7JFWTKiyI+1McnAz1ML1gkCUcKNZnLMYA6C7 wenEpQNy4oar2+AIYw3BbV4Sghzgo4F/SQ== X-Google-Smtp-Source: AA6agR6R6WH7mCZEZ7++3k5x55U0dSRPB9mtgxVbyMqvFL6/N4BNYJ9+7KjtvkKnXeg6vTOeEJRI5g== X-Received: by 2002:a17:902:eb90:b0:172:f986:a096 with SMTP id q16-20020a170902eb9000b00172f986a096mr1681082plg.94.1661182281916; Mon, 22 Aug 2022 08:31:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 43/66] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA Date: Mon, 22 Aug 2022 08:27:18 -0700 Message-Id: <20220822152741.1617527-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661192110723100001 Content-Type: text/plain; charset="utf-8" Allow the target to cache items from the guest page tables. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 5e12cc1854..67239b4e5e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -163,6 +163,15 @@ typedef struct CPUTLBEntryFull { =20 /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ +#ifdef TARGET_PAGE_ENTRY_EXTRA + TARGET_PAGE_ENTRY_EXTRA +#endif } CPUTLBEntryFull; =20 /* --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661192977; cv=none; d=zohomail.com; s=zohoarc; b=LOes4kDhHpBpY2nHzMZvoxt88f0j8WSK2rW49hYqLXCAa0PjdYw/VBzXE0o72OFu8F2BoZvTgIU/ZUv1LtbmzLWsXYZRml0fLbk1u7Yuk3tLE03utFMeOYMVg31ozGxsJ2x4XSpJqPpVMWpFGQXLOB8ZS2a5WaoU9cLpxCj99xs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661192977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ue9Nl0D44aZHstGkTsjwRG+rtSs9n3MbvqWOGp6wdbM=; b=UvUdmxyifOkOwb300Bj6MVUUnIPoqZa0lN6HGZgTXzDJeKyFnd72ntlSZZ2X/Zp0WFdwn6OImbpn33wPVkbQUP/EsnMwbBK3e7jBI6DUqNJ0pppmAyZq+eHKcPfmJIuVFVnEhXq4AjHYCn4XBdJl8iU6m6Ca+Ibly8xjMw0Wr+k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166119297713436.56406896627675; Mon, 22 Aug 2022 11:29:37 -0700 (PDT) Received: from localhost ([::1]:59686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQCB6-0003Tg-4r for importer@patchew.org; Mon, 22 Aug 2022 14:29:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Oj-0004f2-2O for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:29 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:40958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oe-0001ba-4p for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:27 -0400 Received: by mail-pl1-x62a.google.com with SMTP id x23so10240752pll.7 for ; Mon, 22 Aug 2022 08:31:23 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Ue9Nl0D44aZHstGkTsjwRG+rtSs9n3MbvqWOGp6wdbM=; b=GP2UHDeqVxGGLUq+DQ0rv8QWikrXA3M84uvtu5h5jcN9Rq27Ret1xxxCYCsGmfYM1z HmJCmxyU0d+/c8gDhbRrm4BlnOR2YsdqTW4Taz2Ha6Y6e4NoqIa/nunD3mQWaQMCXf++ T1CRNhbq3mVZPFSGaAK7kh1Lm0xntsxldY1tmzurA7gOoYFR7npvApfscIoGDjWxGLnW pkHl2KerNDJNGtN1dYP+9nRknQa774glW1omwoIvQafkOnE+Ik2eX3JiRcrF1e9PVVjB DU1cuyq9i3EI72bLNR/PG0sdQg5+fLw8CEuIJ36Ur/WXwvDyt+Uy1oCQQZO/bU43oDGz MMgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Ue9Nl0D44aZHstGkTsjwRG+rtSs9n3MbvqWOGp6wdbM=; b=xo23dnxOzePU1Ep3Wq17JsOWEvxJA8Duhh9AWdiGTJzqFQjROzazj+TkNe8PsJrTzx HLxLMmRQLqxlRRah+z+OBlDz7/LNapGI1e6Vh6d7Bl1KMql+ENoMrDb55AeNFhibV9v9 FCSVba6yv+heDAK9rMGDIQbrETy90iMU60jw0iliQStqEu8czPvsUJpswB1Yci+sCfv4 lY1Fjw88hpW4GEyp1SHnYAfij3WosVuK1RHU0TNvSS1u5MdJGSvn0fWX/nwltKntzd7A y6y0AsdePeW7wLMcm4QFrfdmC4TUP6FeTGET0xJQdaP7y2veNPdK9D3XiJ2Kk7oY1mYm +bjw== X-Gm-Message-State: ACgBeo0Qh8hzpwr4peL4+wKrB8M6jP/+glB5ae0ESnaAeRVt/CLKwIb3 Jt6pux15AP76iwB2Ko+yT0LJN3LAQeBpPg== X-Google-Smtp-Source: AA6agR7U2B91Sd55eclKiL/4GUMq+yYTPi0I8B9Jiod+CobAewHLT50FB2INac4YYOa8zRdBmpzpVA== X-Received: by 2002:a17:902:c086:b0:172:c7cd:bab0 with SMTP id j6-20020a170902c08600b00172c7cdbab0mr14512682pld.60.1661182282774; Mon, 22 Aug 2022 08:31:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 44/66] target/arm: Enable TARGET_PAGE_ENTRY_EXTRA Date: Mon, 22 Aug 2022 08:27:19 -0700 Message-Id: <20220822152741.1617527-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661192977721100003 Content-Type: text/plain; charset="utf-8" Copy attrs and sharability, into the TLB. This will eventually be used by S1_ptw_translate to report stage1 translation failures, and by do_ats_write to fill in PAR_EL1. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 8 ++++++++ target/arm/tlb_helper.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 08681828ac..118ca0e5c0 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -30,6 +30,14 @@ */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 + +/* + * Cache the attrs and sharability fields from the page table entry. + */ +# define TARGET_PAGE_ENTRY_EXTRA \ + uint8_t pte_attrs; \ + uint8_t shareability; + #endif =20 #define NB_MMU_MODES 8 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 49601394ec..353edbeb1d 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -236,6 +236,9 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, arm_tlb_mte_tagged(&res.f.attrs) =3D true; } =20 + res.f.pte_attrs =3D res.cacheattrs.attrs; + res.f.shareability =3D res.cacheattrs.shareability; + tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; } else if (probe) { --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661187115; cv=none; d=zohomail.com; s=zohoarc; b=DBh5BdIKoaQWtfIKAJUi1CH512cJODzr2Jx9mb5tOuvcUHYyDs5Gea08XvP52pGLGeR+qVH2luybhNr9CY6/GPAzE6ho4RW2h/gvlheK/3djQpHDWXNtj3VtssNfgGmsoBwzJnnWWjky6qj/2rUWBlXZAXCCqMN7PWz3N82oZz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661187115; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rs7twGLWoouQAsExme7uECc666n3pAQTjKmWbmzEPbo=; b=lXMhpfyNLXQbBW6Pq7Bep1GmZojL+GgBqWJZIUQfUKRfEnjwBHlvULb7N+u/GZESf7Huip42Q0EH7pca197O+bvlmBE5DrY7IzmWaEbGKZMJH/FG+Rc552AusmI285utI3DymHEF5WMkJAKEiCW7hBKhm2NbphI2YfDxvBGnxi4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661187115446537.6527299861559; Mon, 22 Aug 2022 09:51:55 -0700 (PDT) Received: from localhost ([::1]:51730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAeW-0002AO-B0 for importer@patchew.org; Mon, 22 Aug 2022 12:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Op-0004h4-2x for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:39 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:53102) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oe-0001cF-WE for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:34 -0400 Received: by mail-pj1-x102e.google.com with SMTP id f21so11361897pjt.2 for ; Mon, 22 Aug 2022 08:31:24 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=rs7twGLWoouQAsExme7uECc666n3pAQTjKmWbmzEPbo=; b=rmiK+akmaasFwyBDUJ5QffZOPR7hYesgydwPivEswoOvC2UzHjbQTCSGfG3ufPnC+j WMxr4q2YBdzKU7IzXQ/f+GImJCGV8q2LNe0RptTKBCZAaIp2TJu7501LI0KjnngGyJ5B zj8224K1yNyRCYQmn9dKgKMmyP2YP7np8JdO4KELm4HAP3krhp9x9gMkIGELRL1VHcFP r6V+vtBaWsp7x8NeONPBKlnEQ+dFA/2984441NAbrfHRyE7rzTbJqxANjdRVwnEupRQZ 6N2e3KBYzIuQEu010k+Rhv2NRvqABv4j5VSMB82juBn0w9qC/kXGyDbKvmUjNsI0kPKx DDJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=rs7twGLWoouQAsExme7uECc666n3pAQTjKmWbmzEPbo=; b=06rJYl3U1cK0BaHmmWmwV9Sjl5FubJXJPjUmmLKjaVg/x0ugDj4ajRKzOsIKshePJq aevOJFMkPiNnri/xg9R9jg4OvZzi62mOJmAzpDb408oYA9W5v7jVvs3Tbx+2hWi5JWox ALeQ8ZxPqHk0JT6kKEl091xOT/BR1TOh2ygmhx8qxIA9qEigdhoHQQPfAnOEhE16Fj2l tqhJb32p2h2yi9xdaxfQAB1wOQTs5pWCjufQ/1jf5rlKHRp0T1nz0Cc6730TJsjLhkfE qc/SU59xMm5HVMCPmpIdiW8rcUEpBX1nuzw4YZz1r9DCexT/vOakzRyyVOpZICrNu6HR Zajw== X-Gm-Message-State: ACgBeo3Og97E7veMv+vusS+vSKTA36OtsEzw4ZFo/3DfpDwJFP6pQPSM HygLlSK/f7OKMu/nar1s1y2GtNzogrBq5A== X-Google-Smtp-Source: AA6agR7+myjfw8rmCTC7mR1mOe75IIJn6BWJcg4RVo64BgLlC0/tcK+Xizu6s4BWIAvR7H7ToQZpAw== X-Received: by 2002:a17:902:e5cc:b0:16f:1e31:da6c with SMTP id u12-20020a170902e5cc00b0016f1e31da6cmr20768999plf.66.1661182283447; Mon, 22 Aug 2022 08:31:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 45/66] target/arm: Use probe_access_full for MTE Date: Mon, 22 Aug 2022 08:27:20 -0700 Message-Id: <20220822152741.1617527-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661187116621100001 Content-Type: text/plain; charset="utf-8" The CPUTLBEntryFull structure now stores the original pte attributes, as well as the physical address. Therefore, we no longer need a separate bit in MemTxAttrs, nor do we need to walk the tree of memory regions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - target/arm/sve_ldst_internal.h | 1 + target/arm/mte_helper.c | 61 +++++++++------------------------- target/arm/sve_helper.c | 54 ++++++++++-------------------- target/arm/tlb_helper.c | 4 --- 5 files changed, 35 insertions(+), 86 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a08e546de4..8230a0b141 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3388,7 +3388,6 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxA= ttrs *x) * generic target bits directly. */ #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) -#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) =20 /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h index b5c473fc48..4f159ec4ad 100644 --- a/target/arm/sve_ldst_internal.h +++ b/target/arm/sve_ldst_internal.h @@ -134,6 +134,7 @@ typedef struct { void *host; int flags; MemTxAttrs attrs; + bool tagged; } SVEHostPage; =20 bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index fdd23ab3f8..a81c4a3318 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -105,10 +105,9 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; #else - uintptr_t index; CPUTLBEntryFull *full; + MemTxAttrs attrs; int in_page, flags; - ram_addr_t ptr_ra; hwaddr ptr_paddr, tag_paddr, xlat; MemoryRegion *mr; ARMASIdx tag_asi; @@ -124,30 +123,12 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, * valid. Indicate to probe_access_flags no-fault, then assert that * we received a valid page. */ - flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, - ra =3D=3D 0, &host, ra); + flags =3D probe_access_full(env, ptr, ptr_access, ptr_mmu_idx, + ra =3D=3D 0, &host, &full, ra); assert(!(flags & TLB_INVALID_MASK)); =20 - /* - * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB - * because we just found the mapping. - * TODO: Perhaps there should be a cputlb helper that returns a - * matching tlb entry + iotlb entry. - */ - index =3D tlb_index(env, ptr_mmu_idx, ptr); -# ifdef CONFIG_DEBUG_TCG - { - CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); - target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, ptr)); - } -# endif - full =3D &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index]; - /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&full->attrs)) { + if (full->pte_attrs !=3D 0xf0) { return NULL; } =20 @@ -162,6 +143,13 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, return NULL; } =20 + /* + * Remember these values across the second lookup below, + * which may invalidate this pointer via tlb resize. + */ + ptr_paddr =3D full->phys_addr; + attrs =3D full->attrs; + /* * The Normal memory access can extend to the next page. E.g. a single * 8-byte access to the last byte of a page will check only the last @@ -170,9 +158,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, */ in_page =3D -(ptr | TARGET_PAGE_MASK); if (unlikely(ptr_size > in_page)) { - void *ignore; - flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, - ptr_mmu_idx, ra =3D=3D 0, &ignore, ra); + flags |=3D probe_access_full(env, ptr + in_page, ptr_access, + ptr_mmu_idx, ra =3D=3D 0, &host, &full,= ra); assert(!(flags & TLB_INVALID_MASK)); } =20 @@ -180,33 +167,17 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, if (unlikely(flags & TLB_WATCHPOINT)) { int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); - cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - full->attrs, wp, ra); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); } =20 - /* - * Find the physical address within the normal mem space. - * The memory region lookup must succeed because TLB_MMIO was - * not set in the cputlb lookup above. - */ - mr =3D memory_region_from_host(host, &ptr_ra); - tcg_debug_assert(mr !=3D NULL); - tcg_debug_assert(memory_region_is_ram(mr)); - ptr_paddr =3D ptr_ra; - do { - ptr_paddr +=3D mr->addr; - mr =3D mr->container; - } while (mr); - /* Convert to the physical address in tag space. */ tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); =20 /* Look up the address in tag space. */ - tag_asi =3D full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_asi =3D attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, - tag_access =3D=3D MMU_DATA_STORE, - full->attrs); + tag_access =3D=3D MMU_DATA_STORE, attrs); =20 /* * Note that @mr will never be NULL. If there is nothing in the addre= ss diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9cae8fd352..3d0d2987cd 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5351,8 +5351,19 @@ bool sve_probe_page(SVEHostPage *info, bool nofault,= CPUARMState *env, */ addr =3D useronly_clean_ptr(addr); =20 +#ifdef CONFIG_USER_ONLY flags =3D probe_access_flags(env, addr, access_type, mmu_idx, nofault, &info->host, retaddr); + memset(&info->attrs, 0, sizeof(info->attrs)); + /* Require both ANON and MTE; see allocation_tag_mem(). */ + info->tagged =3D (flags & PAGE_ANON) && (flags & PAGE_MTE); +#else + CPUTLBEntryFull *full; + flags =3D probe_access_full(env, addr, access_type, mmu_idx, nofault, + &info->host, &full, retaddr); + info->attrs =3D full->attrs; + info->tagged =3D full->pte_attrs =3D=3D 0xf0; +#endif info->flags =3D flags; =20 if (flags & TLB_INVALID_MASK) { @@ -5362,33 +5373,6 @@ bool sve_probe_page(SVEHostPage *info, bool nofault,= CPUARMState *env, =20 /* Ensure that info->host[] is relative to addr, not addr + mem_off. */ info->host -=3D mem_off; - -#ifdef CONFIG_USER_ONLY - memset(&info->attrs, 0, sizeof(info->attrs)); - /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */ - arm_tlb_mte_tagged(&info->attrs) =3D - (flags & PAGE_ANON) && (flags & PAGE_MTE); -#else - /* - * Find the iotlbentry for addr and return the transaction attributes. - * This *must* be present in the TLB because we just found the mapping. - */ - { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - -# ifdef CONFIG_DEBUG_TCG - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong comparator =3D (access_type =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, addr)); -# endif - - CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - info->attrs =3D full->attrs; - } -#endif - return true; } =20 @@ -5617,7 +5601,7 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUAR= MState *env, intptr_t mem_off, reg_off, reg_last; =20 /* Process the page only if MemAttr =3D=3D Tagged. */ - if (arm_tlb_mte_tagged(&info->page[0].attrs)) { + if (info->page[0].tagged) { mem_off =3D info->mem_off_first[0]; reg_off =3D info->reg_off_first[0]; reg_last =3D info->reg_off_split; @@ -5638,7 +5622,7 @@ void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUAR= MState *env, } =20 mem_off =3D info->mem_off_first[1]; - if (mem_off >=3D 0 && arm_tlb_mte_tagged(&info->page[1].attrs)) { + if (mem_off >=3D 0 && info->page[1].tagged) { reg_off =3D info->reg_off_first[1]; reg_last =3D info->reg_off_last[1]; =20 @@ -6017,7 +6001,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, * Disable MTE checking if the Tagged bit is not set. Since TBI must * be set within MTEDESC for MTE, !mtedesc =3D> !mte_active. */ - if (!arm_tlb_mte_tagged(&info.page[0].attrs)) { + if (!info.page[0].tagged) { mtedesc =3D 0; } =20 @@ -6568,7 +6552,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_READ, reta= ddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } if (unlikely(info.flags & TLB_MMIO)) { @@ -6585,7 +6569,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, msize, info.attrs, BP_MEM_READ, retaddr); } - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } tlb_fn(env, &scratch, reg_off, addr, retaddr); @@ -6786,9 +6770,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, (env_cpu(env), addr, msize) & BP_MEM_READ)) { goto fault; } - if (mtedesc && - arm_tlb_mte_tagged(&info.attrs) && - !mte_probe(env, mtedesc, addr)) { + if (mtedesc && info.tagged && !mte_probe(env, mtedesc, add= r)) { goto fault; } =20 @@ -6974,7 +6956,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, info.attrs, BP_MEM_WRITE, retaddr= ); } =20 - if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { + if (mtedesc && info.tagged) { mte_check(env, mtedesc, addr, retaddr); } } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 353edbeb1d..3462a6ea14 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -231,10 +231,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, res.f.phys_addr &=3D TARGET_PAGE_MASK; address &=3D TARGET_PAGE_MASK; } - /* Notice and record tagged memory. */ - if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs =3D=3D= 0xf0) { - arm_tlb_mte_tagged(&res.f.attrs) =3D true; - } =20 res.f.pte_attrs =3D res.cacheattrs.attrs; res.f.shareability =3D res.cacheattrs.shareability; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186022; cv=none; d=zohomail.com; s=zohoarc; b=PQHe71dHzAtQdYMbTpxsscf9JJHVuwfuAi1Q75L2Gv4qKbdAEbb/ThJHwKinxjnTc0yKvXH1BuXu0EwVEeOn4Q3biFbHsKwjVZAjNGDblpD6QnLux7UknLe+YbKnHzRWyFfBatsfJsWAy7MF2van/sksB0954lRgxrWTDipCQ1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186022; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WBpLIBGMD5lRpOAKw5T58Wru1vUut/0oVVoO4QrpR+0=; b=RPB+FYbsgdTfWEAZhOA7bNL+PvNGXtfswvTseYR0PpYXzambNmnSFY41FphBBLx6We6Ri8GPt7v4Kuk7LP5M2Mw9TQQuadD8S5wjKLLdpbZbuJd54Uwx+cPAEopuSxXFVXInlhdK+hnDtwu5lKfKtmiGM0DtimZnrgNmGL+fPNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661186022206197.3194182758134; Mon, 22 Aug 2022 09:33:42 -0700 (PDT) Received: from localhost ([::1]:51486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAMu-0005Ki-V8 for importer@patchew.org; Mon, 22 Aug 2022 12:33:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ol-0004gT-EO for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:34 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:37775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Of-0001cQ-MJ for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:29 -0400 Received: by mail-pl1-x631.google.com with SMTP id m2so10259326pls.4 for ; Mon, 22 Aug 2022 08:31:25 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=WBpLIBGMD5lRpOAKw5T58Wru1vUut/0oVVoO4QrpR+0=; b=lsHjzrm4CQW7KopXPYEmQAr4tsCD8crnwd6/W5Phn0c8jrzJG2GYMG4w0iRCXyQnuV 0eYs8OXEqzvgvUaNfGS7DEJ6mrH/mOXZxQaWAZq6rVTQ12oZqf4rZkVIG7mcqERwChbn vUChgIsiuiHSaqb1z6tl4Deo7nBfW8O4Suzo8I8BL/C+lspSuKd6EtyT+BpHLYvXN3mR Om3BTOPowGxIjP72KkdzNJvej7SF4Waybdhv1sctkUBAMLq7UQavxxAap1pzkgIdblbk g5a+b8Vg/pYt9FiRbQvcZtSdDBnEsL/NrP+q/y1J7VjGGvQzYo4x6GKiF1Um3hLhjFkl JxEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=WBpLIBGMD5lRpOAKw5T58Wru1vUut/0oVVoO4QrpR+0=; b=ehxZeItcyxB1oqmKjpatK327TGn7uNX/GWi+szVC7vS0MGJZqpAjNigdAv8K7oFT8U 3WWdsD7LVuKTmdQb1HovNbkn214fhhF8WuJya5M0TzG2B658wo+DKBKjNDTprPK+KI8o 41ikk7gQMpKFbegixBT4nzEDr1ywSzssFkJpPYoRKWQjgWB8gEsLZG2R0xc1zS+VWTBB Z0q4ghecfT23dW9FrE0fI12YE0AU/k9rnr6m8nmeZfr10IpueczEARLVOUxseDk9lcl/ 6J72G3thU/9HL5Jkek4Dqu+9K0VA5rDVuiNzrzkUMsy5ccignGyNd7dRX2/KK3b1+EY1 LYBA== X-Gm-Message-State: ACgBeo3x8rbZiwD0gu7EsdlM7D8kfB9qinVlyYliDzfSzPEu0zRNlxBP xBTquUxgBcypFvCjgyEHzaC5XYGTNgUHZw== X-Google-Smtp-Source: AA6agR7PGvR5Rgh0lrlyvFtUyPe5vm9eDj0RBRiPx7WgkzyR71BQIaXPfFp7+8Y5NIgwL6HwIN6xRw== X-Received: by 2002:a17:902:c94a:b0:16f:81c1:255a with SMTP id i10-20020a170902c94a00b0016f81c1255amr20217323pla.35.1661182284070; Mon, 22 Aug 2022 08:31:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 46/66] target/arm: Use probe_access_full for BTI Date: Mon, 22 Aug 2022 08:27:21 -0700 Message-Id: <20220822152741.1617527-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186024217100001 Content-Type: text/plain; charset="utf-8" Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit. In is_guarded_page, use probe_access_full instead of just guessing that the tlb entry is still present. Also handles the FIXME about executing from device memory. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 8 ++++---- target/arm/cpu.h | 13 ------------- target/arm/internals.h | 1 + target/arm/ptw.c | 7 ++++--- target/arm/translate-a64.c | 22 ++++++++-------------- 5 files changed, 17 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 118ca0e5c0..689a9645dc 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,12 +32,12 @@ # define TARGET_PAGE_BITS_MIN 10 =20 /* - * Cache the attrs and sharability fields from the page table entry. + * Cache the attrs, sharability, and gp fields from the page table entry. */ # define TARGET_PAGE_ENTRY_EXTRA \ - uint8_t pte_attrs; \ - uint8_t shareability; - + uint8_t pte_attrs; \ + uint8_t shareability; \ + bool guarded; #endif =20 #define NB_MMU_MODES 8 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8230a0b141..f48dcadad6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3376,19 +3376,6 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *e= nv, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[5]; =20 -/* Helper for the macros below, validating the argument type. */ -static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) -{ - return x; -} - -/* - * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. - * Using these should be a bit more self-documenting than using the - * generic target bits directly. - */ -#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) - /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect diff --git a/target/arm/internals.h b/target/arm/internals.h index e914227e55..bab3e89227 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1067,6 +1067,7 @@ typedef struct ARMCacheAttrs { unsigned int attrs:8; unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ bool is_s2_format:1; + bool guarded:1; /* guarded bit of the v8-64 PTE */ } ARMCacheAttrs; =20 /* Fields that are valid upon success. */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index dafbf71d00..69c22c039b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1319,9 +1319,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, */ result->f.attrs.secure =3D false; } - /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ - if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(&result->f.attrs) =3D true; + + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { + result->f.guarded =3D guarded; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 305044a141..afabd77694 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14611,22 +14611,16 @@ static bool is_guarded_page(CPUARMState *env, Dis= asContext *s) #ifdef CONFIG_USER_ONLY return page_get_flags(addr) & PAGE_BTI; #else + CPUTLBEntryFull *full; + void *host; int mmu_idx =3D arm_to_core_mmu_idx(s->mmu_idx); - unsigned int index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + int flags; =20 - /* - * We test this immediately after reading an insn, which means - * that any normal page must be in the TLB. The only exception - * would be for executing from flash or device memory, which - * does not retain the TLB entry. - * - * FIXME: Assume false for those, for now. We could use - * arm_cpu_get_phys_page_attrs_debug to re-read the page - * table entry even for that case. - */ - return (tlb_hit(entry->addr_code, addr) && - arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs)= ); + flags =3D probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx, + false, &host, &full, 0); + assert(!(flags & TLB_INVALID_MASK)); + + return full->guarded; #endif } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661189111; cv=none; d=zohomail.com; s=zohoarc; b=IqVLShYKNMfYvH+lI6MmW4KiwIzaV1fAf/UZCQs7ZGqDkdlv0bMKPsKd7xeUjxu/MKjU3Vg4yeiYZNwGSNYOfA0Dn15AWjdHSTrpsHey9ikLV+2usUDRhWmM6oQIXrlU8scHCG0XvTzHyEqmeKlY7sUjFnDQT1iFgt0Ylne46F4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661189111; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mlHd+wwiv8pBaZCez3yDRMnKt1mN27booBhwkoA66eA=; b=VFfJTwMOzt+4nK8cn0Rf7NYS8sWSGMqYPxoulfLfs5MfVY/4BPgGjRfwEqT8AcjWPBLt0cHFrbY4xGp9vpNBe2z/h/R4ytdRNyX52RUMOwbC7mkvLrgFZOMoxFsQp7D9k00W8vZk1lJdu0UOV2TIZFn4CKpEWu2AyfBFZArIdME= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661189111263136.38223020741623; Mon, 22 Aug 2022 10:25:11 -0700 (PDT) Received: from localhost ([::1]:50286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBAk-0004MR-5Z for importer@patchew.org; Mon, 22 Aug 2022 13:25:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ol-0004gS-EA for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:34 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:36442) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Og-0001co-Ev for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:30 -0400 Received: by mail-pj1-x1032.google.com with SMTP id r14-20020a17090a4dce00b001faa76931beso14355830pjl.1 for ; Mon, 22 Aug 2022 08:31:26 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=mlHd+wwiv8pBaZCez3yDRMnKt1mN27booBhwkoA66eA=; b=EL0IBj80XfawSZQ7+1JraUZ4oAKZlwgsFbjXEzE4aBarpo9aqP0BUSKUbMiwo86Izz zYPo0TWIxtZAVVFycN7J7ujFIY4fknLTMMKLrmT92Ih3BAgBKfGa48rInmttqJjTqJGg wS/wohjiv4V1H9FIjG6xEJy4cdrUV+JspjRUTdXsxmc1woL6QC2QbmikW1BVdsnnfFgS eQFfbYOcsWbxy7ljUySXVf9dLIJzrM+8dPguqEG9u3tDrL8EVUldNWc6n80FohbIFfwM xFyUtWQvi2k++L5JUSWli5/UtFP4saUQ1SVkN7eI9ARqhKMlDnK0vnuJeA8XMfxrmz9n yCUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=mlHd+wwiv8pBaZCez3yDRMnKt1mN27booBhwkoA66eA=; b=T0lPjnOF8wQHGIpTBYvfkCLV7HnRHWDV2Q9NSbjlrlqelc/pNg7SzjQvW+mvvtARac OfHpSwANuuMmZY/eP8xX0wlU5RuYVn56MPSsDqK0KDer2Q5b9xPsh8jK1DdU0V6EteDk e22thTl2XB1FcQl0ziB6xHm/J8qAGW1MD7dDuaVhaj9Yd61A516MSarczi1Rrb5sk+6T CUP+3BPE2m3skOPH78UN3wBI4xek6m2aGXX5YhoeaQJgEsams0uvTtzG9Z9bkdHDsyYe fQzYjzDDio1UudP4xppmp5exxN1QNHlvA6Tsc8IYcpzLYtIEODnUfCiFC77Fp3QNmZP1 8Caw== X-Gm-Message-State: ACgBeo3dOPF3wP5MoP7eLLHgr+FEwiJKmbPf7/QJApQvRtaDDo61xEnT 45BryYWv8Cwx4Lqcq3uvp7sowlo5E3TbXw== X-Google-Smtp-Source: AA6agR735+xWBDGFW7Rqj+OSidpuFz/awuGmbmucmHnWmbKsQjl+1e0BSGIE1rn3XTv2Ld7nxY34wg== X-Received: by 2002:a17:902:e809:b0:172:eded:e879 with SMTP id u9-20020a170902e80900b00172edede879mr4863328plg.54.1661182285051; Mon, 22 Aug 2022 08:31:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 47/66] include/exec: Remove target_tlb_bitN from MemTxAttrs Date: Mon, 22 Aug 2022 08:27:22 -0700 Message-Id: <20220822152741.1617527-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189111604100003 Content-Type: text/plain; charset="utf-8" We have now moved all uses to PageEntryExtra. Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..1bd7b6c5ca 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -47,16 +47,6 @@ typedef struct MemTxAttrs { unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; - /* - * The following are target-specific page-table bits. These are not - * related to actual memory transactions at all. However, this struct= ure - * is part of the tlb_fill interface, cached in the cputlb structure, - * and has unused bits. These fields will be read by target-specific - * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bit= N. - */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; } MemTxAttrs; =20 /* Bus masters which don't specify any attributes will get this, --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661185375; cv=none; d=zohomail.com; s=zohoarc; b=gFUidKS1RjrvvgOBdEeoLyhx92dnnoZ7kVP78JZS50dxHUWK9zOQ87GyMXzU2DsQYxBbL4rtqaRrUc7bcxAKK7ipd91I5XEj5+9qfsB7XP4jPGRMn9/PWsZ/AIZR8NYqfANuJhdZGS4eHaDLSqwHsbNOK5kO1puQUcgo9B/spF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661185375; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hP5+8v+RzVZCLhdFfgMbyeBX5j55jrO26f4OY0zFxiA=; b=YkonbVSrfWx55ryUwqbYYD6m9RgXg76wgVuFJ0oq97GWG2XRL1JD/cNSHsVK32eWGRGDr0E7vKSkO+qD/9bWg06waBFBgTplqBslkVRRRk3HW7w5tS7sssQnG6L2Nu6NBbEMom386FKzcaerHrMBjachLvxr0gRl5x195RVA2DE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661185375022443.46839999081; Mon, 22 Aug 2022 09:22:55 -0700 (PDT) Received: from localhost ([::1]:53182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQACT-0006cL-RJ for importer@patchew.org; Mon, 22 Aug 2022 12:22:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Om-0004gW-Es for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:34 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:37778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oh-0001dF-0x for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:31 -0400 Received: by mail-pl1-x634.google.com with SMTP id m2so10259418pls.4 for ; Mon, 22 Aug 2022 08:31:26 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=hP5+8v+RzVZCLhdFfgMbyeBX5j55jrO26f4OY0zFxiA=; b=O8YRS71zzDOs2TnlO+clL0QYI4M5PdDtCcQBJnhIagijyKQ62eaOFfKU61/8Slu1FP anQ0+O7AKqkuEoUdZsgX99KPsmGM9+6Wwxl/v1zYNs3WlEQy5A/IPn2X99q5lYC+VeaM jY4uJDlA/M6tjhQYQUN/M5gLNi5Y5gSaMA7lN6h9H2CPqrkY/7JcKnRZP7i1FRqxGRQy pXu7UwLWuj3JrsWKqvhKB7E8eXTNHxzwWidvimTaIwJcjRS6Vlb2PnyFaJUlKunWHHkH bY6P/idNqXeQ8+TEUg+J/R5yy2Lws+i0Ns36e/z6xOI+oAubJ4rq5cXDkSQqe97KRmCx kAzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=hP5+8v+RzVZCLhdFfgMbyeBX5j55jrO26f4OY0zFxiA=; b=r4DsFGrPzQdUMh165K1ag9tpVGe3zLUjiiPe/YU+V3ZVHlvPzoVzCdW2+q4TOHvl7v AdO8fC5Icd2O0/UPaccJGtIpagk71UyqL1foEV3974VmC56AK/YwKtK+506Bvb3yd1SD 3MiWq599Fj3fKoZbEx/kzm1AKenAzoyg0JKSxN5KL34olx9hfwRI45BqiSpw3yyur5Na /eJCf12T2MwuhkHhV7YJUlgJsLJVxFajtEemR0OYs0VbxSsc+gXMLraSWASKqtRFoX2K OJNBV14kvFnizH+n3iL8Q0H0/8GD2YuTPgyczliPQwSdO/oQUlFWUojjeUZhLw3U3Gu1 dI3g== X-Gm-Message-State: ACgBeo2Sei3Ug66Cemc2DDivpPWMiQa5QnMSoJyUv2eUcleQRPx3itCz t/S6BDUGrrjts9ZKE/4iA/VHK9/jttAkqw== X-Google-Smtp-Source: AA6agR6fwBlrypbcYez3/EUNO7nApzT/CKLyh1AYNwhU3+VVTGXcNEjL7PN855u1dxxdsDLu6WKkHg== X-Received: by 2002:a17:90b:2802:b0:1fb:4efd:a1ca with SMTP id qb2-20020a17090b280200b001fb4efda1camr2300608pjb.198.1661182285730; Mon, 22 Aug 2022 08:31:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 48/66] target/arm: Add ARMMMUIdx_Phys_{S,NS} Date: Mon, 22 Aug 2022 08:27:23 -0700 Message-Id: <20220822152741.1617527-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661185376152100001 Content-Type: text/plain; charset="utf-8" Not yet used, but add mmu indexes for 1-1 mapping to physical addresses. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 4 ++++ target/arm/ptw.c | 9 +++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 689a9645dc..98bd9e435e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 10 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f48dcadad6..76391dc47d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2959,6 +2959,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 69c22c039b..e409c8034f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -179,6 +179,11 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; =20 + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: + /* No translation for physical address spaces. */ + return true; + default: g_assert_not_reached(); } @@ -2289,6 +2294,8 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: memattr =3D 0x00; /* unused, but Device, nGnRnE */ shareability =3D 0; /* unused, but non-shareable */ break; @@ -2579,6 +2586,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, is_secure =3D arm_is_secure_below_el3(env); break; case ARMMMUIdx_Stage2: + case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -2587,6 +2595,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, break; case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661186532; cv=none; d=zohomail.com; s=zohoarc; b=IsS6q6EaBimu+5qPmU7HY9yqdZa800KdEB8Pf2+Fx9GT6K6lbAwLKB1bH5ksNoFnOMYu8JCuOijQnJCvwmOdlXJlVdKYOCpmYIyogDe6oAixWmiTgSbUXw5FKE0qZZzJ6BOoUc3grzfbpbSY1N32ZQ5X0SPQt9I2+OCpwUblA50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661186532; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YLRJNbQ3E77TTRtGqNy9Q3lDjAcTISkeMsUGwY5ybLI=; b=f52AarrNA3AGdCfGTZ3Ob4a6ce0Hg1Ybjyet7qNZIwc3CM9cBEX4b5Kjn7CUVAyS/OHbb/gnqEThSuxgGTObKBMSoN+AnyZ+eV0L30hzfdKdV53Qcse4HHxCvDG4YlMvtH955W0c49UY2VC5xagvrHMC92PogJ2ZY10DC1ntiP8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661186532897186.47874317332946; Mon, 22 Aug 2022 09:42:12 -0700 (PDT) Received: from localhost ([::1]:48914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAV8-0003V1-Rw for importer@patchew.org; Mon, 22 Aug 2022 12:42:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9On-0004ga-Dd for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:34 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:38754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oi-0001dk-PS for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:33 -0400 Received: by mail-pf1-x42b.google.com with SMTP id y127so7716257pfy.5 for ; Mon, 22 Aug 2022 08:31:27 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=YLRJNbQ3E77TTRtGqNy9Q3lDjAcTISkeMsUGwY5ybLI=; b=ue4DIYW8qU+umDSf7jdtVrDafEpAJSfykiE58J0UmH57HyuSVxLxhsRwavU5cjXVtD ZAP7G8J9+EWzD7+eUg5KqWFXm2TRUNXzdYhpgliDXNqhxEaLCCAEdBknv2oODmNl0oUv 0RZGI1WGRkT4/h3q9hdnAtJJynLHY1BQaQeHDuGa+5xD3gblCk9d9Wvru0qgfvCcmJqA GH1NJaJej7Yo8W5S763WbdJ6liH716GoH9d72io2aOk7CNLqDnKQLlqKSZ3pqTl7fzsM TVkdgVyjFUfnXglR84SAvfA7CoPzQe+CNMFwRa3fgtlt3F6lzezOvYAFsmhDJZ0Npefk misA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=YLRJNbQ3E77TTRtGqNy9Q3lDjAcTISkeMsUGwY5ybLI=; b=I4InAaH5Eqfqx1rrs3HLtXfHnGY0le8Ue7II7M2MVFfNNOOcIiBsTnntfDm+MqtWnW 4xih9BJCpdzUtdCQ2klSLBYe4POMhZXfjTL6uUfFLa5+wl2OSMSXmV1vIJovWbH+ZK42 3roBoMNvy1csHcHofDsZkf+hR0i5ooznxLOY15RCaYHImSs48dOBgWkWVLftPNKbFLbz /Z80pIxTaIGUu54/pqcHqLxmxMy429OqZjL7Wnwt4nBJQTd09csgbWpMBRFKbpQjKYcT rwdpy5F+Ox1PXBh43g39d9NWXSDLz2XuYds/CcaBlKXxDqOV4OkSz2D1V0TSImWLi0g+ FqKQ== X-Gm-Message-State: ACgBeo3+Bp7rPuDmvA/+iq5YwNYUmZnz0Ox5cBJfuIR6SFvCw/nkPjkI qzqcX/LEJCD0nxkDpR8VP8d3fYdUVn4xBA== X-Google-Smtp-Source: AA6agR7cCJ2tkNOHngQ+86M9de1e9CvxfnEU4gpmxLFtNDqERDYkBdd2VteIK6dfkHLWPuDKPNatIg== X-Received: by 2002:a63:e342:0:b0:42a:411:fa34 with SMTP id o2-20020a63e342000000b0042a0411fa34mr16628730pgj.89.1661182286506; Mon, 22 Aug 2022 08:31:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 49/66] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Date: Mon, 22 Aug 2022 08:27:24 -0700 Message-Id: <20220822152741.1617527-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661186534997100001 Content-Type: text/plain; charset="utf-8" We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb. Flush the tlb when invalidating stage 1+2 translations. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 20 +++++++++++--------- target/arm/helper.c | 4 +++- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 98bd9e435e..283618f601 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 10 +#define NB_MMU_MODES 12 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 76391dc47d..4ab0cac8b6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2963,6 +2963,15 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, =20 + /* + * Used for second stage of an S12 page table walk, or for descriptor + * loads during first stage of an S1 page table walk. Note that both + * are in use simultaneously for SecureEL2: the security state for + * the S2 ptw is selected by the NS bit from the S1 ptw. + */ + ARMMMUIdx_Stage2 =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 11 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. @@ -2970,15 +2979,6 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, - /* - * Not allocated a TLB: used only for second stage of an S12 page - * table walk, or for descriptor loads during first stage of an S1 - * page table walk. Note that if we ever want to have a TLB for this - * then various TLB flush insns which currently are no-ops or flush - * only stage 1 MMU indexes will need to change to flush stage 2. - */ - ARMMMUIdx_Stage2 =3D 3 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage2_S =3D 4 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -3009,6 +3009,8 @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(E3), + TO_CORE_BIT(Stage2), + TO_CORE_BIT(Stage2_S), =20 TO_CORE_BIT(MUser), TO_CORE_BIT(MPriv), diff --git a/target/arm/helper.c b/target/arm/helper.c index 887f613b40..765638f002 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4236,7 +4236,9 @@ static int alle1_tlbmask(CPUARMState *env) */ return (ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_Stage2 | + ARMMMUIdxBit_Stage2_S); } =20 static int e2_tlbmask(CPUARMState *env) --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661189478; cv=none; d=zohomail.com; s=zohoarc; b=eoy8SAOXHcSxwzD6hVUHA40QQ+yAUIvyrSUpGK6/5e/6enhojrAzq/M1JBRZbksbC8qMm0xUXyXlF36fMgNpPjYEpCIaqFwE5ZF5vJQTHVN8LstzS8BqmuNSOjg2U1FAlh1gdagfpypKBrr/9rldXeNWyszepqAERJBVTsvDwuA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661189478; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tteklD09eTTok/Y4B7/WVi6G6xuW7zvbPGPVt7Z5GHE=; b=HOHxO6wOFqRoQfrrB6uoiL04bvr97413hNsRrzHzhvRgzHYOmj/IoECWDt4MNXHt31VAiSAPpWdbjspu9NONwx5CSOvH89XBpoAGMfEKcKndeUX4WMCVlb9hppDKBSN2BMnnF/ZG+K2/rZTjI5IxznKe2bYLgynI98xfuiu7Yas= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661189478133875.8965086079891; Mon, 22 Aug 2022 10:31:18 -0700 (PDT) Received: from localhost ([::1]:43674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBGd-00026d-6s for importer@patchew.org; Mon, 22 Aug 2022 13:31:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Op-0004hI-Ep for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:39 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:47077) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oi-0001dx-Qn for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:35 -0400 Received: by mail-pg1-x530.google.com with SMTP id d71so9671725pgc.13 for ; Mon, 22 Aug 2022 08:31:28 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=tteklD09eTTok/Y4B7/WVi6G6xuW7zvbPGPVt7Z5GHE=; b=RxBh7RdHQ563tpr5PsK8Yvqj/LdFQVpmXu7axcHNTddZygpmQMQ4Q9EDLjOQAqL63g H5yMKeKPSeaKrkumJNiFZlyCXCo7yJBj8L3DDl7F7yaTsUmOcbgDiGupvOxNcgSXNmiY RvSDi93MjJnuzkaMuuc3Zoa0agtrGeOYSa0G7yROhgVigPlaKlYbUjPvYlwE0D60eIyS 4OaCPqIm90RwosM3V5Hm3EHXcgSlmk7wpkJmOwOhSonRMZqV6fxjFtaZ6zsSVpA5SYEr tTkwo442hr9nFOp+V0rmvDZBJvAqHXpcJryYJD5ZhaAVJQbvIp9050bhX9UbM7KYCL1W y8Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=tteklD09eTTok/Y4B7/WVi6G6xuW7zvbPGPVt7Z5GHE=; b=jJhZaUImJ/ou+LFANX0mx4eeTxLfjZnWIkZdGkDX/8U3XNcQUd7MOVvFuv7xMTg0Bz zVG/0zvXaVYkaAUs3NXRwvFEf8ZERZTTA/AT+3c/xKbOH5ZIhBTLI7f5ajTmo680nmIH sr0W/iD1XNhbacQV+bfSK8F8ztpdWvchlzkp2oWLJ7ni2ZKuHWG9AB0SArGzwoxGu7TO 0FNruFk4zLLTMdQLc1tTRc27w2kc+67ffu9NtdY61zOlZsjUxcODJsTgVYDK1SrtbHbY WKYk4votEf+k2cqqSOpcuDL4oLB1Swj/Oi//fPiSuXK5HaRZZu916eRFpnXH7jMBcEVj owSw== X-Gm-Message-State: ACgBeo1tTWhBBgyTNyxf+259va7trt1kLCYLYRvyzylrTiglYEz+5aJq uQ3G3AhMzKlBN6jQAMIbOuDL/eul6gHLiw== X-Google-Smtp-Source: AA6agR5H9eNp4D37M60ejaPSlNZw+8bd54o468Qw39VSKvL3o9P+HJG/O3F4KdAREfaxoQ+kVr0Dug== X-Received: by 2002:a63:f753:0:b0:42a:bfc9:ea52 with SMTP id f19-20020a63f753000000b0042abfc9ea52mr4330403pgk.408.1661182287253; Mon, 22 Aug 2022 08:31:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 50/66] target/arm: Use softmmu tlbs for page table walking Date: Mon, 22 Aug 2022 08:27:25 -0700 Message-Id: <20220822152741.1617527-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189479966100003 Content-Type: text/plain; charset="utf-8" So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and arm_ldq_ptw. Use probe_access_full to find the host address, and if so use a host load. If the probe fails, we've got our fault info already. On the off chance that page tables are not in RAM, continue to use the address_space_ld* functions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/ptw.c | 205 +++++++++++++++++++++++----------------- target/arm/tlb_helper.c | 17 +++- 3 files changed, 138 insertions(+), 89 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ab0cac8b6..8fb4baf604 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -225,6 +225,8 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; =20 +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -715,6 +717,9 @@ typedef struct CPUArchState { struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; =20 + /* Optional fault info across tlb lookup. */ + ARMMMUFaultInfo *tlb_fi; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e409c8034f..628c046cab 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/range.h" +#include "exec/exec-all.h" #include "cpu.h" #include "internals.h" #include "idau.h" @@ -191,52 +192,57 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) -{ - /* - * For an S1 page table walk, the stage 1 attributes are always - * some form of "this is Normal memory". The combined S1+S2 - * attributes are therefore only Device if stage 2 specifies Device. - * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] are 0b= 00, - * ie when cacheattrs.attrs bits [3:2] are 0b00. - * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0, ie - * when cacheattrs.attrs bit [2] is 0. - */ - assert(cacheattrs.is_s2_format); - if (hcr & HCR_FWB) { - return (cacheattrs.attrs & 0x4) =3D=3D 0; - } else { - return (cacheattrs.attrs & 0xc) =3D=3D 0; - } -} - /* Translate a S1 pagetable walk through S2 if needed. */ -static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure_ptr, - ARMMMUFaultInfo *fi) +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr a= ddr, + bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, + ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; + CPUTLBEntryFull *full; + int flags; =20 - if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - GetPhysAddrResult s2 =3D {}; - uint64_t hcr; - int ret; + if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) + || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { + s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + } =20 - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - is_secure, false, &s2, fi); - if (ret) { - assert(fi->type !=3D ARMFault_None); - fi->s2addr =3D addr; - fi->stage2 =3D true; - fi->s1ptw =3D true; - fi->s1ns =3D !is_secure; - return ~0; + env->tlb_fi =3D fi; + flags =3D probe_access_full(env, addr, MMU_DATA_LOAD, + arm_to_core_mmu_idx(s2_mmu_idx), + true, hphys, &full, 0); + env->tlb_fi =3D NULL; + + if (unlikely(flags & TLB_INVALID_MASK)) { + assert(fi->type !=3D ARMFault_None); + fi->s2addr =3D addr; + fi->stage2 =3D true; + fi->s1ptw =3D true; + fi->s1ns =3D !is_secure; + return false; + } + + if (s2_mmu_idx =3D=3D ARMMMUIdx_Stage2 || s2_mmu_idx =3D=3D ARMMMUIdx_= Stage2_S) { + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t s2attrs =3D full->pte_attrs; + bool is_device; + + /* + * For an S1 page table walk, the stage 1 attributes are always + * some form of "this is Normal memory". The combined S1+S2 + * attributes are therefore only Device if stage 2 specifies Devic= e. + * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] ar= e 0b00, + * ie when s2attrs bits [3:2] are 0b00. + * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0,= ie + * when s2attrs bit [2] is 0. + */ + if (hcr & HCR_FWB) { + is_device =3D (s2attrs & 0x4) =3D=3D 0; + } else { + is_device =3D (s2attrs & 0xc) =3D=3D 0; } =20 - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { + if ((hcr & HCR_PTW) && is_device) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -246,24 +252,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, fi->stage2 =3D true; fi->s1ptw =3D true; fi->s1ns =3D !is_secure; - return ~0; + return false; } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (is_secure) { - is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); - } else { - is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); - } - *is_secure_ptr =3D is_secure; - } else { - assert(!is_secure); - } - - addr =3D s2.f.phys_addr; } - return addr; + + if (is_secure) { + /* Check if page table walk is to secure or non-secure PA space. */ + *is_secure_ptr =3D !(full->attrs.secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); + } + + *gphys =3D full->phys_addr; + return true; } =20 /* All loads done in the course of a page table walk go through here. */ @@ -271,56 +272,88 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint32_t data; + bool be; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldl_be(as, addr, attrs, &result); + + be =3D regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data =3D ldl_be_p(hphys); + } else { + data =3D ldl_le_p(hphys); + } } else { - data =3D address_space_ldl_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D is_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (be) { + data =3D address_space_ldl_be(as, gphys, attrs, &result); + } else { + data =3D address_space_ldl_le(as, gphys, attrs, &result); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint64_t data; + bool be; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldq_be(as, addr, attrs, &result); + + be =3D regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data =3D ldq_be_p(hphys); + } else { + data =3D ldq_le_p(hphys); + } } else { - data =3D address_space_ldq_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D is_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (be) { + data =3D address_space_ldq_be(as, gphys, attrs, &result); + } else { + data =3D address_space_ldq_le(as, gphys, attrs, &result); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3462a6ea14..69b0dc69df 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,10 +208,21 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; + ARMMMUFaultInfo local_fi, *fi; int ret; =20 + /* + * Allow S1_ptw_translate to see any fault generated here. + * Since this may recurse, read and clear. + */ + fi =3D cpu->env.tlb_fi; + if (fi) { + cpu->env.tlb_fi =3D NULL; + } else { + fi =3D memset(&local_fi, 0, sizeof(local_fi)); + } + /* * Walk the page table and (if the mapping exists) add the page * to the TLB. On success, return true. Otherwise, if probing, @@ -220,7 +231,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, */ ret =3D get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, &fi); + &res, fi); if (likely(!ret)) { /* * Map a single [sub]page. Regions smaller than our declared @@ -242,7 +253,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, } else { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } } #else --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661193366; cv=none; d=zohomail.com; s=zohoarc; b=Hg66BvuLKghk9woxYbsTGh/cu3xK2fqhA4ntTRpV89QJH2HrPz2tOgq385vYG0aFJ6hYg3UJXiQeEA79xlMuhRUGUDsfQotSOS6q/6eF/TGWu6Wnk5YkD++/vBovB/1WYrz2gnV37qbcTYEa8PKcqPyvGBTkJ0k6hkDBzNOWJg8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661193366; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tCVH1Kl59BnkmKbSQf/4G0BExsgfIMMri2yi/FRxOQo=; b=lG7oERCnnuen+RIZAFsMQOT92KbxXgLcpm8KcF4MTbM2O3RG3Jehaw4mkfYOaLz9K8WvBVnlU5tcC9hby2yHFupN7i0Vnr9WzX/0LE7u/+mTDAZAFFcKXJJ0cDb6nd6prlyaAGEDSiAYePtH9i8p3/2w1aIlrZ5XR0qreGac4x8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16611933660301018.2538323731366; Mon, 22 Aug 2022 11:36:06 -0700 (PDT) Received: from localhost ([::1]:41364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQCHM-00025u-TD for importer@patchew.org; Mon, 22 Aug 2022 14:36:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ox-0004kj-Ml for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:47 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:55829) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oj-0001e4-5T for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:35 -0400 Received: by mail-pj1-x1031.google.com with SMTP id pm13so2434571pjb.5 for ; Mon, 22 Aug 2022 08:31:28 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=tCVH1Kl59BnkmKbSQf/4G0BExsgfIMMri2yi/FRxOQo=; b=F6o0yTuF+CPWWucyTOzZen4xOlYTgXOFmhfJlkIBCB9av7gMgv3kFLemjenTVKlH3A xXth4pFoayFQP/CaJqaKOxJwst+lIhuqszvTh4aGXKis7QIh1TFZrhAtvLJLY6l43QLv ellNdKvLc1EPo3Ha+qfJWzl1MwXPmwplBogMnGTJOCbAS+mM+g4a+hb53WeOOWi5OZUC 3nFYZEUTw4D1WDScSvc1Xn4aUj5nhvu7/p2mffIi0M6vzt8lRxMRZ2lgp5Wb920W0kj/ ulqJ+JKQmyIixr5wHssiUyneGoJ3VNvIr82GJko/ZlbNvyqbFZ7uE0QzBcFqoRMV1ptA XGSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=tCVH1Kl59BnkmKbSQf/4G0BExsgfIMMri2yi/FRxOQo=; b=Th1hVyw9IANgIMSq6UDPG6f4x4NVqC2qYk6I0624iWyMyyzHVJrz+/KGttLQStCY6e oXZnPQQ5JoyE7/Mkah+uFQvrS6StujraTI/3mGo7+jFC5+HkczQjGMr03IvtX4i4Q8PE gTUo3paZC4Nfd3tupZwIsbnpdfeiDQBVmUchCSfTNq9akmDoZK1yCJqDj/R5mL363cqg GNYg8d531xVI4KZixovxauQFFmpAgVzOoHiMssjdXtXxkrXAvSEzhIc8GzE39qXjDtWA tlQwHGdabBKrPTjOTs56NUphart5x+OmK1ol0PXtnHCtWPv0aX+dUE04vFgvnza89Ahi NuXQ== X-Gm-Message-State: ACgBeo0/oljtyxQH07LvdB+ybjSFPsQ7yINFQTzx88i2yJOm3CJQcRVm ATBFtT8KumtvIr/EGO+hDZ4oszsuEv7u2g== X-Google-Smtp-Source: AA6agR5589LMp0nKI6pOfIXEuaMBO153dZmBUA5Dih9GT3vtIjBPPpvULE6H6i0JTLEoYNqr+7HdOQ== X-Received: by 2002:a17:902:f64f:b0:172:a790:320a with SMTP id m15-20020a170902f64f00b00172a790320amr20671005plg.149.1661182287920; Mon, 22 Aug 2022 08:31:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 51/66] target/arm: Hoist check for disabled stage2 translation. Date: Mon, 22 Aug 2022 08:27:26 -0700 Message-Id: <20220822152741.1617527-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661193368212100001 Content-Type: text/plain; charset="utf-8" If stage2 translation is disabled, E1&0 translation is just a single stage. Use the complete single stage path rather than breaking out of the middle of the two stage path. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 628c046cab..d9daaf7536 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2437,9 +2437,10 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, if (mmu_idx !=3D s1_mmu_idx) { /* * Call ourselves recursively to do the stage 1 and then stage 2 - * translations if mmu_idx is a two-stage regime. + * translations if mmu_idx is a two-stage regime, and stage2 enabl= ed. */ - if (arm_feature(env, ARM_FEATURE_EL2)) { + if (arm_feature(env, ARM_FEATURE_EL2) && + !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)= ) { hwaddr ipa; int s1_prot; int ret; @@ -2452,9 +2453,8 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, ret =3D get_phys_addr_with_secure(env, address, access_type, s1_mmu_idx, is_secure, result,= fi); =20 - /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, - is_secure)) { + /* If S1 fails, return early. */ + if (ret) { return ret; } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661191942; cv=none; d=zohomail.com; s=zohoarc; b=LtKNSSEngx765NKh12S0xDGrtIcKpLfObFqi7myQGyMgBNBVyXYnxHkSMFghSj3n5FSrfAIZe1Kl9QdoGphQEIaoME7SToCjPJU5Qdlen+B7s7Cyv/NKalCGvSYObm3QEsOXj3ktsuEIJlPMxWezpTdVzNVS3FJEv0xfd4uJ+HI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661191942; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WjSL4eHObvEK6R8buP8RA9WVWUFZ8A0DbOMp8emchq4=; b=KyD+rDaOOGi1KTPKsJlnP3lPSYWtIU4cv83NBXheD3M+bO3Ihc6xx+E7ViNEHZ3KRMC9AcustkJ0433ur6X12dqnyzFYAtfki54y/5e9PvLj7Xf9esJ3iD67CAhvRQscIQsRr0mb2Lw3LhbAEHpOipaFan+VrcMqoJf0HYGDgAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661191942698311.3812915539979; Mon, 22 Aug 2022 11:12:22 -0700 (PDT) Received: from localhost ([::1]:40158 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBuP-0005Zn-3L for importer@patchew.org; Mon, 22 Aug 2022 14:12:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ox-0004lS-LH for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:45 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:38852) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Ol-0001el-5f for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:39 -0400 Received: by mail-pg1-x535.google.com with SMTP id r22so9693474pgm.5 for ; Mon, 22 Aug 2022 08:31:29 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=WjSL4eHObvEK6R8buP8RA9WVWUFZ8A0DbOMp8emchq4=; b=Bys5Do7cxUe2p1MZvkRSx5TDz6e3A9lB3BRLuHwpddiXJUgB+PccQfZPX/fM905QiH 4FC6WtdVM2BWVcVTav4psv0PjwuYpD2MIe0PXhXwHH+sxdjOQApoIqZSs2Hp6HHDGGxS rUCan6tKH3w0UPI77LJV+Att8YlaeXNwwTgm99iLJD94xJKmhe3oQSBd8apF3V8n1tA4 127tNtWpEU2ykf7Uitf/hgVLVyLRuHa8N7F/nt0EsGF3pZz6p3Z24gbo9N8P11VQJNDo mp9LoNrG0RIfz1fh7SxlG0Am4tYqCvD+Y1ss9z1kNUJcfjCuWIzU1ZGMyPdgyk9+Ha7U noDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=WjSL4eHObvEK6R8buP8RA9WVWUFZ8A0DbOMp8emchq4=; b=sTXdGJyWqvviYh0m2BXkVGlEbsmhy9IfvwsGuP4+W/wDIE5VPisIgHrYdsNdTk5bSj 36uBk+WpRUsjUBCHRK4qgw0KxVCmAiquzRzqRb5y9JiQrzp5pw1Eh+56W1m9pVrXKQNJ fNHl52h1XnK3x/G53fZonUjN1YjdqAFeRKUYHS4aKp45oOgcKe9QZ0Ey/2tnsiGhLoc9 xyOe6jfUv8uxGPoQhnh9p01hx9dwl7k3ndWBmKjlptDmuBOEJgeOjSv/yWtp8TVHF2dx EF8f/flnrfWguz3gSXat/trhXTsfvv9/psfOWLSYSHNoxlsoOgsZlKdLtY6MiVt+ogBF nKXg== X-Gm-Message-State: ACgBeo3IdzDe4rUnYOmkmAc7XwAtsiuabHCi/vI+Fklca0ZAmSN5yvrm czqnV5PIi0YBh4THJHO6vxHVZfIBupcIqw== X-Google-Smtp-Source: AA6agR68PcQac6vDJ/EmHx1YduaqYkqMfn1ENsa8GFJwZ/nnkIQQHR8MVMhBX540g9IMCGQlH0eQaw== X-Received: by 2002:a63:134d:0:b0:42a:9680:29d7 with SMTP id 13-20020a63134d000000b0042a968029d7mr7109030pgt.249.1661182288660; Mon, 22 Aug 2022 08:31:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 52/66] target/arm: Split out get_phys_addr_twostage Date: Mon, 22 Aug 2022 08:27:27 -0700 Message-Id: <20220822152741.1617527-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661191944994100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/ptw.c | 182 +++++++++++++++++++++++++---------------------- 1 file changed, 96 insertions(+), 86 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d9daaf7536..e13a8442c5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2404,6 +2404,95 @@ static bool get_phys_addr_disabled(CPUARMState *env,= target_ulong address, return 0; } =20 +static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, + MMUAccessType access_type, + ARMMMUIdx s1_mmu_idx, bool is_secure, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + hwaddr ipa; + int s1_prot; + int ret; + bool ipa_secure; + ARMCacheAttrs cacheattrs1; + ARMMMUIdx s2_mmu_idx; + bool is_el0; + uint64_t hcr; + + ret =3D get_phys_addr_with_secure(env, address, access_type, s1_mmu_id= x, + is_secure, result, fi); + + /* If S1 fails, return early. */ + if (ret) { + return ret; + } + + ipa =3D result->f.phys_addr; + if (is_secure) { + /* Select TCR based on the NS bit from the S1 walk. */ + ipa_secure =3D !(result->f.attrs.secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW); + } else { + ipa_secure =3D false; + } + + s2_mmu_idx =3D (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + is_el0 =3D s1_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; + + /* + * S1 is done, now do S2 translation. + * Save the stage1 results so that we may merge + * prot and cacheattrs later. + */ + s1_prot =3D result->f.prot; + cacheattrs1 =3D result->cacheattrs; + memset(result, 0, sizeof(*result)); + + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + ipa_secure, is_el0, result, fi); + fi->s2addr =3D ipa; + + /* Combine the S1 and S2 perms. */ + result->f.prot &=3D s1_prot; + + /* If S2 fails, return early. */ + if (ret) { + return ret; + } + + /* Combine the S1 and S2 cache attributes. */ + hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + if (hcr & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. + */ + if (cacheattrs1.attrs !=3D 0xf0) { + cacheattrs1.attrs =3D 0xff; + } + cacheattrs1.shareability =3D 0; + } + result->cacheattrs =3D combine_cacheattrs(hcr, cacheattrs1, + result->cacheattrs); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (is_secure) { + if (ipa_secure) { + result->f.attrs.secure =3D + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); + } else { + result->f.attrs.secure =3D + !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); + } + } + return 0; +} + /** * get_phys_addr - get the physical address for this virtual address * @@ -2441,93 +2530,14 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, */ if (arm_feature(env, ARM_FEATURE_EL2) && !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)= ) { - hwaddr ipa; - int s1_prot; - int ret; - bool ipa_secure; - ARMCacheAttrs cacheattrs1; - ARMMMUIdx s2_mmu_idx; - bool is_el0; - uint64_t hcr; - - ret =3D get_phys_addr_with_secure(env, address, access_type, - s1_mmu_idx, is_secure, result,= fi); - - /* If S1 fails, return early. */ - if (ret) { - return ret; - } - - ipa =3D result->f.phys_addr; - if (is_secure) { - /* Select TCR based on the NS bit from the S1 walk. */ - ipa_secure =3D !(result->f.attrs.secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW); - } else { - ipa_secure =3D false; - } - - s2_mmu_idx =3D (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2); - is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0; - - /* - * S1 is done, now do S2 translation. - * Save the stage1 results so that we may merge - * prot and cacheattrs later. - */ - s1_prot =3D result->f.prot; - cacheattrs1 =3D result->cacheattrs; - memset(result, 0, sizeof(*result)); - - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, - ipa_secure, is_el0, result, fi); - fi->s2addr =3D ipa; - - /* Combine the S1 and S2 perms. */ - result->f.prot &=3D s1_prot; - - /* If S2 fails, return early. */ - if (ret) { - return ret; - } - - /* Combine the S1 and S2 cache attributes. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - if (hcr & HCR_DC) { - /* - * HCR.DC forces the first stage attributes to - * Normal Non-Shareable, - * Inner Write-Back Read-Allocate Write-Allocate, - * Outer Write-Back Read-Allocate Write-Allocate. - * Do not overwrite Tagged within attrs. - */ - if (cacheattrs1.attrs !=3D 0xf0) { - cacheattrs1.attrs =3D 0xff; - } - cacheattrs1.shareability =3D 0; - } - result->cacheattrs =3D combine_cacheattrs(hcr, cacheattrs1, - result->cacheattrs); - - /* Check if IPA translates to secure or non-secure PA space. */ - if (is_secure) { - if (ipa_secure) { - result->f.attrs.secure =3D - !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); - } else { - result->f.attrs.secure =3D - !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); - } - } - return 0; - } else { - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage = 1. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); + return get_phys_addr_twostage(env, address, access_type, + s1_mmu_idx, is_secure, + result, fi); } + /* + * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + */ + mmu_idx =3D s1_mmu_idx; } =20 /* --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661188225; cv=none; d=zohomail.com; s=zohoarc; b=Kvgc0OHhLXJhR9Uv0jku/6iT29JsAaUYZo0Ng7fzk+lJw9nJatpKIMgFqnkelU7BdqAFIq52dgTrn5+ZAJzj1VpY3qpk2uQvERmc1PNzkpTQTbmCr258d1CuNDy8AKzHu8Nk494RJ8ZEM8gsHQsypfm3n2PcNRtLONeSAvKimd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661188225; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aac6RI9qOaZKSVRWcJWmXw/3ZjmmA0PhS65KUQMelMI=; b=f/9zNQr81GU7PjxRnHi5VAKaacXsFJwWcUS0FfII+cagVX/Mx7cqRj7uCJp28VZmeWYHY9fPMTrXYym3K1RARWqMDBzTdx/6bOXyAMXBkmanMwgpraTg8qEzywFjQd7XTWjKmjIEBDpFm6aucYxb6U1oomkNOAJZe2N+KdBIjVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661188225088858.5209582358445; Mon, 22 Aug 2022 10:10:25 -0700 (PDT) Received: from localhost ([::1]:42922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAwR-0007Rx-RU for importer@patchew.org; Mon, 22 Aug 2022 13:10:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Oy-0004lK-Ia for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:48 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:33739) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Ol-0001f1-6I for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:41 -0400 Received: by mail-pj1-x102d.google.com with SMTP id ds12-20020a17090b08cc00b001fae6343d9fso6045606pjb.0 for ; Mon, 22 Aug 2022 08:31:30 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e13a8442c5..46f5178692 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2380,7 +2380,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, fi->type =3D ARMFault_AddressSize; fi->level =3D 0; fi->stage2 =3D false; - return 1; + return true; } =20 /* @@ -2401,7 +2401,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, result->cacheattrs.is_s2_format =3D false; result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; - return 0; + return false; } =20 static bool get_phys_addr_twostage(CPUARMState *env, target_ulong address, @@ -2412,7 +2412,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, { hwaddr ipa; int s1_prot; - int ret; + bool ret; bool ipa_secure; ARMCacheAttrs cacheattrs1; ARMMMUIdx s2_mmu_idx; @@ -2490,7 +2490,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } } - return 0; + return false; } =20 /** --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661191399; cv=none; d=zohomail.com; s=zohoarc; b=Ie+8RItJPOIF0r9CjBoqN1pEMjXkQpjNGnLF7dEFZpbPFSdj9gBu+xtHZ92uaCmBnCMKoehp+oQxyl4c7D0o5rO0kzeOUHMAXQdQQL1dLMM3MBMw4juF+y18xb/pdnN/ziNSxXW2idS/eVOzIgyrJMiqLkCaxHS7MRY/IOaG7qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661191399; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FF+VbrmmZnxZ1wObhTbkrmTqMO4Rm6Z3tRZAxl2tAjA=; b=dLsQout9SfsX0F6MYkuYWK5CPj5HCGrT/yPHQWbzEuuI4ffemb5k6D2Irc9zQXT+xmcC5qGsjcQpZQOk+cAYqy/tJiMe/1nY7vgomx76SrOa3NTEbm+0OGEaHI+mX1QmC+oZRGcQLXDw1jSUpPw7SsVnaqeFzgZAqf99MXiIuVk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166119139922844.90319166641996; Mon, 22 Aug 2022 11:03:19 -0700 (PDT) Received: from localhost ([::1]:35342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBle-0007PV-29 for importer@patchew.org; Mon, 22 Aug 2022 14:03:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ox-0004lV-LB for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:46 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:40700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Ol-0001fF-PE for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:36 -0400 Received: by mail-pg1-x535.google.com with SMTP id w13so4603559pgq.7 for ; Mon, 22 Aug 2022 08:31:31 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=FF+VbrmmZnxZ1wObhTbkrmTqMO4Rm6Z3tRZAxl2tAjA=; b=cmHx8rF2008OR9gqQz/utMFSfT8tvZ+l6m2k/U3Vban8t/aaqHkJUvdPCJEGCGA2Cr 7P8k/kkfjMlsFSbH3Y1/z3MLMalfLC1ebgAdrbsiFuGRP1DWk+ZiCON44lymu52rxVaN w4TgtQdD4Mz5zo84i9vTzRbeL1TVWGuNYZfJMMCipJZcyo7dp8OoIKzp8hkQxDjfEahP UwsSn5rd2lGQDG9GW5yyt7pt1ZRIp+iSNZDWAuyM/GugDgVBu0U7HSG7UV28/xpj86uJ RS87nD6cbHCRrBw5tbg/pz0YxTrRNazPaHMuhy0NyEVq75cg0R0UJU3gdrqOalg+bpev rt6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=FF+VbrmmZnxZ1wObhTbkrmTqMO4Rm6Z3tRZAxl2tAjA=; b=TRkE0fgb4Gop0TDLoBxb8tXPcx/WLIZzzoZ5MO4vuYbGMaiJKNq/NsHP+OFlhCdlci v9cC7q4Z5Y8j0NS1y0E6E54wrnM4hcK0EP5cmV/l2wSBpbzKA109FxXdfVrvJ25WKpRB mkBvXozcsKokGe64zAJVZHcwBUpFBWxpfUnjMQHdx8VVxF2c5P8PsIy8fpAc1QPpXiLO Vy6SeCs57Bkh58B2jn1WaTBE0086DNOZ1Y/XykWPAOfR+HS3o7FbG+AHMPpk5GM7Mtwm gnFRsqfRsh3rhNtOMoquSPf4TU2W5jrkrJy3ALc1H79SQoX64e6mEZg9qZOyZBw17ttZ fNeg== X-Gm-Message-State: ACgBeo01d8K1ixKKmj5dOaSI2IWsLzNRZDbvGxHNUVNk9MWv5zzKAr3c JTPAaOoqjgFYaMYTvW71l7tNBcR37lmA0A== X-Google-Smtp-Source: AA6agR7xxDsvvFFJU14S1l8/S6yNcF6fXPqXv8sd0y2AFz09I/Aje+cJSAEI1tHGXGlRWRmaNI3i8w== X-Received: by 2002:a05:6a00:804:b0:52f:43f9:b634 with SMTP id m4-20020a056a00080400b0052f43f9b634mr21450290pfk.62.1661182290529; Mon, 22 Aug 2022 08:31:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 54/66] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation Date: Mon, 22 Aug 2022 08:27:29 -0700 Message-Id: <20220822152741.1617527-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661191401224100001 Content-Type: text/plain; charset="utf-8" If stage2 is disabled, we do not need to adjust mmu_idx. Below, we'll use get_phys_addr_lpae and not recurse. Adjust regime_is_user so that it can be used for E10_0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 46f5178692..9366066ae0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -90,6 +90,7 @@ static bool regime_translation_big_endian(CPUARMState *en= v, ARMMMUIdx mmu_idx) static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { + case ARMMMUIdx_E10_0: case ARMMMUIdx_E20_0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: @@ -99,10 +100,6 @@ static bool regime_is_user(CPUARMState *env, ARMMMUIdx = mmu_idx) return true; default: return false; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - g_assert_not_reached(); } } =20 @@ -2534,10 +2531,6 @@ bool get_phys_addr_with_secure(CPUARMState *env, tar= get_ulong address, s1_mmu_idx, is_secure, result, fi); } - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. - */ - mmu_idx =3D s1_mmu_idx; } =20 /* --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661187466; cv=none; d=zohomail.com; s=zohoarc; b=WkcdHIv2WGcbekoQ37j3LPpUyv5SkQ4qWd2fak0aF5ZzSmgSkLXwHABNcj/bAFx6TtYUDyzTEwocsxCFd1iQqjI6XVk1jQ94CojSHy703tsjHitfLyBjzU/L52V6atfzNdRCIyrrDtPVSt4cOxtP+6Z9Jl1CMCjgkpPL/4pnUNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661187466; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QMHGZpV2baRUbxElNpiXVCtLXS1Q/rN0XnOdtvv92bo=; b=S9/gowoWo1obQNyNLSD+XNdt6rIpjfef6KiPijhv1rsOQR7wS9XK+AoVjxSBm1RcVuZRHdQRH/DY9kkEI2bBvwZ46HdZ+zYylM0WYyyhxM9n7X/YhKCAWAmYk3J8Yg6NqBEZKhebPyoF18a38xCXSbyuWO9CSFo4fY43vR0Ze40= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661187466964290.7661957293212; Mon, 22 Aug 2022 09:57:46 -0700 (PDT) Received: from localhost ([::1]:56874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQAkD-0008QW-Mv for importer@patchew.org; Mon, 22 Aug 2022 12:57:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ow-0004kk-P0 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:43 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:38420) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Om-0001am-73 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:38 -0400 Received: by mail-pj1-x102b.google.com with SMTP id s31-20020a17090a2f2200b001faaf9d92easo14332929pjd.3 for ; Mon, 22 Aug 2022 08:31:31 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=QMHGZpV2baRUbxElNpiXVCtLXS1Q/rN0XnOdtvv92bo=; b=rjBcar3CJBc4WUqLPUh65JqRTaRma5nzjNxKwpMnNm2p5hRtiCd0HqKk7KKP+gcg0O baJAZ7S3AZ4elZqMxk+Y9+AoEYPrK1UrKMPC2yyM6Ky2+dVeb7AIDVKK+F707t5+81iA OEhDEcubJUQ6LBWBfsbGanTXFy1FFqgYfxdhvp2th4FjMbpG/oBwKDTferps17RcjIy0 mXFAeCGG/Dh1qdkmRkGN5hU8RoDhEAPhhbdmKNbPBq00jP0qSIbUE+97ONe/hlKfb4Ee wD0WYSAipNwY2l8mCCExzl1UrFXRMu8VUDU+NQjOEX8reZ/3qEKoWR2xU8u9Ms9VBbxN VAKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=QMHGZpV2baRUbxElNpiXVCtLXS1Q/rN0XnOdtvv92bo=; b=Dz+bZuj5dkeJtXN5FS//RO15JMYmLmZJ+tbPdQcg+y6iHIMeatVpP8WHaTQ2LbuFz3 +eVJxxp3rILspqtQPhBuYWKLL6H+FIB9orvQpACXVSXlEwrugVFKEU95P5x8G968Dcb+ nylxVPpcXKe4gLgPaI5Xcx66dshOjQW/WKG0YHEIIEYZl4mZItx2RvIPLWjI32WCuC97 zW2t9ZfcXbGJTzYq7KeijdqPjLf0rEjY1wKfRVPuiM+BldGn5iG6CqkeCJFtQgqGytyb dXPrtDUM7/m7gf+rYtVktPFUvJcy/bEjbJdj/x3ULR9N2VakPjs2qcze13fS1HKKhOPH eGlA== X-Gm-Message-State: ACgBeo3rSxWagp3+0/TNfeM+3ukf/hQEyOCtx9btWnmgBQjnLK563sGP z/zaue4TSTxG24i3OPMt/3s3nYw5eR8Krg== X-Google-Smtp-Source: AA6agR6XhZ/cZKoaFjcATOw3+Upm+/FD+YipXw7Cv17e7F9KxjLYL5B8eFppDgl4T9hF0YyFCKISAA== X-Received: by 2002:a17:903:451:b0:172:ddb9:fe4e with SMTP id iw17-20020a170903045100b00172ddb9fe4emr8739315plb.130.1661182291057; Mon, 22 Aug 2022 08:31:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 55/66] target/arm: Add ptw_idx argument to S1_ptw_translate Date: Mon, 22 Aug 2022 08:27:30 -0700 Message-Id: <20220822152741.1617527-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661187469241100001 Content-Type: text/plain; charset="utf-8" Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_secure and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Pass ptw_idx through get_phys_addr_{v5,v6,lpae} and arm_{ldl,ldq}_ptw. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 100 +++++++++++++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 33 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9366066ae0..9673b97f79 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -17,7 +17,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, bool s1_is_el0, + ARMMMUIdx ptw_idx, bool is_secure, + bool s1_is_el0, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 @@ -190,20 +191,15 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, } =20 /* Translate a S1 pagetable walk through S2 if needed. */ -static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr a= ddr, +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, + ARMMMUIdx s2_mmu_idx, hwaddr addr, bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; - ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; CPUTLBEntryFull *full; int flags; =20 - if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) - || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - } - env->tlb_fi =3D fi; flags =3D probe_access_full(env, addr, MMU_DATA_LOAD, arm_to_core_mmu_idx(s2_mmu_idx), @@ -266,7 +262,8 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, hwaddr addr, =20 /* All loads done in the course of a page table walk go through here. */ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, + ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); void *hphys; @@ -274,7 +271,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, uint32_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, &hphys, &gphys, fi)) { /* Failure. */ assert(fi->s1ptw); @@ -310,7 +307,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, + ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); void *hphys; @@ -318,7 +316,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, uint64_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, &hphys, &gphys, fi)) { /* Failure. */ assert(fi->s1ptw); @@ -463,8 +461,8 @@ static int simple_ap_to_rw_prot(CPUARMState *env, ARMMM= UIdx mmu_idx, int ap) =20 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + ARMMMUIdx ptw_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { int level =3D 1; uint32_t table; @@ -483,7 +481,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -521,7 +519,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, /* Fine pagetable. */ table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -582,8 +580,8 @@ do_fault: =20 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) + ARMMMUIdx ptw_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; @@ -606,7 +604,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -659,7 +657,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, ns =3D extract32(desc, 3, 1); /* Lookup l2 entry. */ table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, fi); + desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -1014,7 +1012,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_a= a64, int level, */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool is_secure, bool s1_is_el0, + ARMMMUIdx ptw_idx, bool is_secure, + bool s1_is_el0, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1240,7 +1239,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, fi); + descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, ptw_i= dx, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -2412,7 +2411,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, bool ret; bool ipa_secure; ARMCacheAttrs cacheattrs1; - ARMMMUIdx s2_mmu_idx; + ARMMMUIdx s2_mmu_idx, s2_ptw_idx; bool is_el0; uint64_t hcr; =20 @@ -2434,7 +2433,13 @@ static bool get_phys_addr_twostage(CPUARMState *env,= target_ulong address, ipa_secure =3D false; } =20 - s2_mmu_idx =3D (ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2); + if (ipa_secure) { + s2_mmu_idx =3D ARMMMUIdx_Stage2_S; + s2_ptw_idx =3D ARMMMUIdx_Phys_S; + } else { + s2_mmu_idx =3D ARMMMUIdx_Stage2; + s2_ptw_idx =3D ARMMMUIdx_Phys_NS; + } is_el0 =3D s1_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; =20 /* @@ -2446,7 +2451,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = target_ulong address, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, s2_ptw_i= dx, ipa_secure, is_el0, result, fi); fi->s2addr =3D ipa; =20 @@ -2518,19 +2523,49 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); + ARMMMUIdx s1_mmu_idx, s2_mmu_idx, ptw_idx; =20 - if (mmu_idx !=3D s1_mmu_idx) { + switch (mmu_idx) { + case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + do_disabled: + /* Checking Phys early avoids special casing later vs regime_el. */ + return get_phys_addr_disabled(env, address, access_type, mmu_idx, + is_secure, result, fi); + + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* First stage lookup uses second stage for ptw. */ + ptw_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + break; + + case ARMMMUIdx_E10_0: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E0; + goto do_twostage; + case ARMMMUIdx_E10_1: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E1; + goto do_twostage; + case ARMMMUIdx_E10_1_PAN: + s1_mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; + do_twostage: /* * Call ourselves recursively to do the stage 1 and then stage 2 * translations if mmu_idx is a two-stage regime, and stage2 enabl= ed. */ + s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; if (arm_feature(env, ARM_FEATURE_EL2) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)= ) { + !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { return get_phys_addr_twostage(env, address, access_type, s1_mmu_idx, is_secure, result, fi); } + /* fall through */ + + default: + /* Single stage and second stage uses physical for ptw. */ + ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + break; } =20 /* @@ -2587,18 +2622,17 @@ bool get_phys_addr_with_secure(CPUARMState *env, ta= rget_ulong address, /* Definitely a real MMU, not an MPU */ =20 if (regime_translation_disabled(env, mmu_idx, is_secure)) { - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + goto do_disabled; } if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, - is_secure, false, result, fi); + ptw_idx, is_secure, false, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - is_secure, result, fi); + ptw_idx, is_secure, result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, - is_secure, result, fi); + ptw_idx, is_secure, result, fi); } } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661190505; cv=none; d=zohomail.com; s=zohoarc; b=ZjfRqWAz/8UAEzvaNDnS9wX8KkaZXRChk2Z/588ZkDeIveU+5HS/qVXbtdjGVZMnMOA8mJc0sH7FO7Rp2So+M2anTVfi7rqBjpcBVadsWYmDMsqU0XpdMvoE9KYUOwLU+5qFnE2JWJBJCR41jYgg48RYwDgFdduMEvGfISfey3o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661190505; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iTCmXn4zbNmqsU+EjRI1sB7Q7oTW2VW8cDEmCqjn7r0=; b=R8ecdoBNhfNhJ8WD5jIct2/i9aFZcmnF5m2YitrHs8v5/7X1ZxNP4ZAEHL3quKPPDz9MslFiTYcKA/h9iE6xEYGXRTYvE87Zz2NB/T5geg7mxeCn0nV/G2uWC6UCqIaoWB+3iwbBCnpyhtwSIXii03Na7ikemt//biZjjPMiVFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661190505481148.162407230447; Mon, 22 Aug 2022 10:48:25 -0700 (PDT) Received: from localhost ([::1]:60618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBXD-0002EM-NA for importer@patchew.org; Mon, 22 Aug 2022 13:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ox-0004lO-Ki for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:43 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:47077) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9On-0001g5-R7 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:39 -0400 Received: by mail-pg1-x52f.google.com with SMTP id d71so9671941pgc.13 for ; Mon, 22 Aug 2022 08:31:32 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=iTCmXn4zbNmqsU+EjRI1sB7Q7oTW2VW8cDEmCqjn7r0=; b=gmhb5D62NZ02NLF9hoI4VJ+2R15BL+HlllsDEsFan9cYG1NgmzjrppTHnBPH88aBxB ZqhbRBGQKPM7srEQ8+EOjmyjBek1fl6c2TbX/ACuyce0thUf7sxquvUjU2Y+JqekrVJL WjoBVdZE5vZluFDFa4GYZ/bw3dkMVLpxU6PH5FC7gmmGIutFl7sxYZO7SlLx1feD8/kn iWblGzxupaDKSERA0g3ZZo2/CWA+Z5qFo1peX+ej9h+skO0mkpmwTbPjFxCT8IRNfW0H tZaJxoEN6zIkPwRaxyKvl2Knw0RtvmG3Z7DIyFd4gdVKiHBNFmFoTpv2gvScqDmaJKay cAFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=iTCmXn4zbNmqsU+EjRI1sB7Q7oTW2VW8cDEmCqjn7r0=; b=q3rC/7Vx3+5o234WV9fbsol4oUKhu3IoRxON9PsoEVk04ikJzOt4aL7gpUZA5CN22Y lS1IQM2ULKN/kqZf9Xm7GeS5zDLOrGPWgYDG+7EUT8KXW/3p7nm3PyiUHb0amaCLZtUi T6AmNoB8i+7wqP0A8tazBqrD98Ch14Nl28fSAruNTLPz1HWOTayvYrXEvktZn3D3Kdlj 8lj6F9RPVfm5mDDYtpgxSH8n2Lyzty1ir36CehBpbZ3Eztm/ABl0W5wBwMGUVqUFdwMO ZEqGVsXX15cFJ9uBhf8N8dqyN/Sv7hY2pmz+RnYrE3MqkQs9T+5wtBcezTRJD34IrDyD t0Ng== X-Gm-Message-State: ACgBeo2QMr96Ru0+gBrM9RaIy80RczItsNfnopLTWYglfPv/nD8Y57On VyBrVwa14CSFQ5JuL20D7LxIzrTjNc8K0w== X-Google-Smtp-Source: AA6agR46epjri+93dACeTktDrD0p40SmnIjx1RAvR0ZTxDMvoD3vSmdLJ4WM41H0onakZAn4EbKNQg== X-Received: by 2002:a05:6a00:1a:b0:536:d522:dbf1 with SMTP id h26-20020a056a00001a00b00536d522dbf1mr2283516pfk.42.1661182291838; Mon, 22 Aug 2022 08:31:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 56/66] target/arm: Add isar predicates for FEAT_HAFDBS Date: Mon, 22 Aug 2022 08:27:31 -0700 Message-Id: <20220822152741.1617527-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661190507610100001 Content-Type: text/plain; charset="utf-8" The MMFR1 field may indicate support for hardware update of access flag alone, or access flag and dirty bit. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8fb4baf604..4a1a45d424 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4079,6 +4079,16 @@ static inline bool isar_feature_aa64_lva(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 +static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) !=3D 0; +} + +static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >=3D 2; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661190987; cv=none; d=zohomail.com; s=zohoarc; b=VO+qxFvAEdLPOlPhTuK79yaVskcdnUfacGjIqIxSLFLwvfkgvcI9DxEG8kJIt2q7Td5k/kLXKQN7JXyZEEu/XkcH9Cw39YI82AKThdXU5dCSjdMtDKrQNui0W52saddRgSf4chxue7ftyMdAUYAuoN7N7Zu1cg5HNmNMBYr0QsI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661190987; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zmm5wl5wUr/T1I9FyVRhCcaj7lDWNVq0kdn79O03klA=; b=dSPlomIP1foyxXzkhOjj4cDcgzBObD8QEH4codzWdDEGyB7fWltIgJDd296GXkHVRlOqsQJJTVolsSbnjgE4ggX1A9Vij/rkWLhDVbbsuImQd/GHVe3htgOoQaBaMpyvNm3uGJ10P5lVJB6i2PqdSxqFgUh136uoOm3DOW8WagE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661190987402918.7226490490306; Mon, 22 Aug 2022 10:56:27 -0700 (PDT) Received: from localhost ([::1]:45214 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQBez-0000EF-S8 for importer@patchew.org; Mon, 22 Aug 2022 13:56:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9Ox-0004lR-LE for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:46 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:38847) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Oo-0001gI-NL for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:41 -0400 Received: by mail-pg1-x52f.google.com with SMTP id r22so9693650pgm.5 for ; Mon, 22 Aug 2022 08:31:33 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=zmm5wl5wUr/T1I9FyVRhCcaj7lDWNVq0kdn79O03klA=; b=PVG96sQEAFM9Eep1MvLNTFmcZaWKFU5pYi/deeJAON9VRAbaRGGr6Vi2mZ5LTsoI2D plpUeaqsOoLvrC1uEDfNzL2l1MSNiW+GVgbA5UICuN0/hKqYx4JNpr4/CrMyqYptWG5Q mG3fsT+EHBc/NJroE5+FQlDA9OY/N+hwEDe4D+rx4TSDh65Dj3wIREzWdPN6Kd2I1J/t 5n1ICUIdpFuF2rUcWnXS8n3F6r04udOdai9Tejl9qiCi5KUb3eOvgk96d0VVgRMXfa7w vXJjg0bdMZpnestAhb4Ga+N/GloJfzcAFSp67KvAdNhJzEjVuFsiQYJnjPsvgHV5lY2C jTWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661190988609100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index bab3e89227..de8b3392a8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1014,6 +1014,8 @@ typedef struct ARMVAParameters { bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + bool ha : 1; + bool hd : 1; } ARMVAParameters; =20 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 765638f002..9f24940d20 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10109,7 +10109,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, using16k, using64k, tsz_oob, ds; + bool epd, hpd, using16k, using64k, tsz_oob, ds, ha, hd; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu =3D env_archcpu(env); =20 @@ -10127,6 +10127,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, epd =3D false; sh =3D extract32(tcr, 12, 2); ps =3D extract32(tcr, 16, 3); + ha =3D extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 32, 1); } else { /* @@ -10151,6 +10153,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, hpd =3D extract64(tcr, 42, 1); } ps =3D extract64(tcr, 32, 3); + ha =3D extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 59, 1); } =20 @@ -10222,6 +10226,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, .using64k =3D using64k, .tsz_oob =3D tsz_oob, .ds =3D ds, + .ha =3D ha, + .hd =3D ha & hd, }; } =20 --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661189125; cv=none; d=zohomail.com; s=zohoarc; b=HSpAo1YInFWVmEgnkmDobNxQ/NIbjfCBbDaG04Ih2OlwHBWR3VxmwzzEvjQrbssxPSa/qoIQnm47BeVV7cEcISbCCT/0bXa0jtLA77npWcwa+mXjyYrb6LqWCCkgbRIqE48E0QT1FxmLXAo4pJC6OqnQ26XgKf0V5s7OOFRLyL4= ARC-Message-Signature: i=1; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=it7B1eMCFXglWpcmLLb+ZPWhWwKZWNZeFgdZdEg2+GA=; b=F1m54Fy9FU3KoBB2AO7LQxtORNYxvfXlcPYSv50/6HN00CJC/pUjPdfAzKGWZlT7Sr JRqosNtSWOSP6715H8RKCszcpYpOzz2oVtsp4+i6sWUkrWgYkZVG6QKPvKesh2iyfEQ9 NOywRpvytKasdQG0F0xB46Ez0ROs0gZZKmp8rGZm31Exu2ILOCknF1sfgmkHXLsmFAtP CvGL3Y0WLIpnnIhdAG/8AowTs+kU9fb8vSbtEVfathmslpzd9Euo1pt0aWTfneQh+SyG 3JHkJFG39rT72E44A0Tl/zfxyc/BWH9WsBwtgBWl7uSbyIp1x/nbYYZGpdSODyVtyDbO Zc7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=it7B1eMCFXglWpcmLLb+ZPWhWwKZWNZeFgdZdEg2+GA=; b=JbokmpiSSRmana7Bz6+acb3FoipDaMphd30RDkcuRbjrWSpk/4jo9UM+zZV7yhuno+ 5c5LSrIcAyDYOXXCKUV1+bI5f51RlKcR/2YpZ3S5uz0ajHO3GLluubifqA2X0E+gvEEY 4F1qVFw283WPbpICqPEMX+92pTTxOpfbzhetPq3PyXkwL6DIOIWXd07JQY2J46uHzn8R 5RTFZLd5VHfxO9wT+t7nsXsgoPVBAZG7uRCI1Ax0Jo9fi2vFumRIzN1i9oxPyInKtMsz nieGcrz3IVP1TnZOgvFuPSRxrEesGX6ff4zBl0N4sceFgV4bIYSGmOn2YIX4s3D53wb3 Zweg== X-Gm-Message-State: ACgBeo2AvGevXhkKN8oOC6cTJfZzMHD8tbIT5Iu3qqWNSAJ7QTuLCKoF 7sAEWiHu2gW45Wb1KD/WqOPaSZU1G0L6XA== X-Google-Smtp-Source: AA6agR43xic6tMOcGzIrsIqne5EuXWjG+MZ8lfRTRo1FO18cp4+ANs08IT/9/z+coSyxPi4CzXTITQ== X-Received: by 2002:a17:902:694a:b0:16e:e270:1f84 with SMTP id k10-20020a170902694a00b0016ee2701f84mr20838465plt.89.1661182293413; Mon, 22 Aug 2022 08:31:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 58/66] target/arm: Split out S1TranslateResult type Date: Mon, 22 Aug 2022 08:27:33 -0700 Message-Id: <20220822152741.1617527-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189125741100001 Content-Type: text/plain; charset="utf-8" Consolidate the results of S1_ptw_translate in one struct. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 60 ++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9673b97f79..7c44e7eadd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -190,20 +190,25 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 +typedef struct { + bool is_secure; + void *hphys; + hwaddr gphys; +} S1TranslateResult; + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ARMMMUIdx s2_mmu_idx, hwaddr addr, - bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, + bool is_secure, S1TranslateResult *res, ARMMMUFaultInfo *fi) { - bool is_secure =3D *is_secure_ptr; CPUTLBEntryFull *full; int flags; =20 env->tlb_fi =3D fi; flags =3D probe_access_full(env, addr, MMU_DATA_LOAD, arm_to_core_mmu_idx(s2_mmu_idx), - true, hphys, &full, 0); + true, &res->hphys, &full, 0); env->tlb_fi =3D NULL; =20 if (unlikely(flags & TLB_INVALID_MASK)) { @@ -249,14 +254,13 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, } } =20 - if (is_secure) { - /* Check if page table walk is to secure or non-secure PA space. */ - *is_secure_ptr =3D !(full->attrs.secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW); - } + /* Check if page table walk is to secure or non-secure PA space. */ + res->is_secure =3D (is_secure && + !(full->attrs.secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW)); =20 - *gphys =3D full->phys_addr; + res->gphys =3D full->phys_addr; return true; } =20 @@ -266,36 +270,34 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint32_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)= ) { /* Failure. */ assert(fi->s1ptw); return 0; } =20 be =3D regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data =3D ldl_be_p(hphys); + data =3D ldl_be_p(s1.hphys); } else { - data =3D ldl_le_p(hphys); + data =3D ldl_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 if (be) { - data =3D address_space_ldl_be(as, gphys, attrs, &result); + data =3D address_space_ldl_be(as, s1.gphys, attrs, &result); } else { - data =3D address_space_ldl_le(as, gphys, attrs, &result); + data =3D address_space_ldl_le(as, s1.gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; @@ -311,36 +313,34 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint64_t data; bool be; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)= ) { /* Failure. */ assert(fi->s1ptw); return 0; } =20 be =3D regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data =3D ldq_be_p(hphys); + data =3D ldq_be_p(s1.hphys); } else { - data =3D ldq_le_p(hphys); + data =3D ldq_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 if (be) { - data =3D address_space_ldq_be(as, gphys, attrs, &result); + data =3D address_space_ldq_be(as, s1.gphys, attrs, &result); } else { - data =3D address_space_ldq_le(as, gphys, attrs, &result); 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=dgGRXfqBRyRwvYaWW/xMoQ57AfJT2+cy/LziIxT5Jyk=; b=rEKsOcEbdGRtMJ/BQTJu4uv9iKaJuJxmXD7CJZBG2trWvgMc38DNYnE5p7KWyhyJ4J HfcKVlUkIpvUaHAv4L/gnntO6tN0WrUaBUl8Eu87QdT1USNHo5P8WZ5HjV96RMJNLXbJ UORpSX1giweIfqByBpJKRC3XpDwrIxvHDFfHes8GQrSxppXs0My4tu++93gZnE+n79LY F15F41/5HOzDFKhSOVGzN+pWpuYfjl+8FZume5L1HxIpOk6OAas16LfBV+SHwxxUqDS+ XGo6lm8Copc5leuRYtIpsvff9uKmkRUb7IHA3iQ5+aiNHislx9QuKXLdhKbGgYcqQFpZ EX4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=dgGRXfqBRyRwvYaWW/xMoQ57AfJT2+cy/LziIxT5Jyk=; b=WBptkAoJqqgmcoBrf+F7iFe0gxpEWtR7gRGZZp974WZaKM0Jm0tn7NNErH76jICf3b oh4C5/b0SWljs1h6d2Uo9TcXtUu9RKa2TEbOMESPt2vpOlBYi6VuOMQuTajMWdvJ0J0v yh/3iYO+FjxAyzr2tq/rttBcvVk4TFBQtN0afYfcnlcqfQEtkuCrUPMVvi441IXCIbME reyC2fww4oT/ozzTtWy4ECWAZLNClIyY71yS/vmw20SNOdtm6btHl2U8kkFG8yUvMqP4 4wd1FIev51s6jgbHWZHZZwqeZ+vejAH3ZZIAdo/bKJ3jMb06Xwo9+ENO2mRRvJXJm3oO hYIQ== X-Gm-Message-State: ACgBeo0UCC+diCVx0COTf2fOF5F7sdMjRj5dYO4auoutKclhh62rC00k NR+oqWN5hxpRJFKjbMwvd+H2zJuosHjZWg== X-Google-Smtp-Source: AA6agR4p8+0XNlDufwW8YhobldYP5cBi/49IFwYrd1NregONi/Y98FWNxHSF4GFZNyAAQV/jx/s7Fg== X-Received: by 2002:a17:902:c411:b0:170:91ff:884b with SMTP id k17-20020a170902c41100b0017091ff884bmr20767560plk.58.1661182294248; Mon, 22 Aug 2022 08:31:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 59/66] target/arm: Move be test for regime into S1TranslateResult Date: Mon, 22 Aug 2022 08:27:34 -0700 Message-Id: <20220822152741.1617527-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661193747057100001 Content-Type: text/plain; charset="utf-8" Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7c44e7eadd..e898db8765 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -192,6 +192,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, =20 typedef struct { bool is_secure; + bool be; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -261,6 +262,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, : env->cp15.vtcr_el2 & VTCR_NSW)); =20 res->gphys =3D full->phys_addr; + res->be =3D regime_translation_big_endian(env, mmu_idx); return true; } =20 @@ -272,7 +274,6 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, CPUState *cs =3D env_cpu(env); S1TranslateResult s1; uint32_t data; - bool be; =20 if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)= ) { /* Failure. */ @@ -280,10 +281,9 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr a= ddr, bool is_secure, return 0; } =20 - be =3D regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data =3D ldl_be_p(s1.hphys); } else { data =3D ldl_le_p(s1.hphys); @@ -294,7 +294,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (be) { + if (s1.be) { data =3D address_space_ldl_be(as, s1.gphys, attrs, &result); } else { data =3D address_space_ldl_le(as, s1.gphys, attrs, &result); @@ -315,7 +315,6 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, CPUState *cs =3D env_cpu(env); S1TranslateResult s1; uint64_t data; - bool be; =20 if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)= ) { /* Failure. */ @@ -323,10 +322,9 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr a= ddr, bool is_secure, return 0; } =20 - be =3D regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data =3D ldq_be_p(s1.hphys); } else { data =3D ldq_le_p(s1.hphys); @@ -337,7 +335,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr ad= dr, bool is_secure, AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (be) { + if (s1.be) { data =3D address_space_ldq_be(as, s1.gphys, attrs, &result); } else { data =3D address_space_ldq_le(as, s1.gphys, attrs, &result); --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661193295; cv=none; d=zohomail.com; s=zohoarc; b=g8fq6RyaYAAyktVWMZzZwQGzLn+MZtvp+an7iU8iqBAfRpgjv4q9Fb8bqNr1Fb6Dvk4LIDtUXdr3PYrSh2S78L9PB3X9qaO/vfebnRUwQ7olpc943zHSKIFx13boS01Ha3hmTOrbwjcqBycrxBzjQOSPPc0Jwt2WzMnjc27fRW0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661193295; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/MKMIebQa16txYgeu/nYxxKn3UXY1gtLHITpx3nLDs0=; b=m8G8ZmE+mA5iTAnn7m81Q/oMJTN8TydpILK8JztN0adIrqbBZIP25fAFkdYUP53CeJ//ZGBL+o+qcyoILL3EPfWg54DlZ6v9Gv8pRfes4lFzzTy7CgYq1qzvxoX6SBKPnuGFWR1n/88xl+PtQgtMuiW5rEuUa4VZVYmVgPYq5Mw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661193294819338.52839250912893; Mon, 22 Aug 2022 11:34:54 -0700 (PDT) Received: from localhost ([::1]:33770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQCG9-0000sa-Kp for importer@patchew.org; Mon, 22 Aug 2022 14:34:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9PD-0004xD-C0 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:59 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:45911) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9P0-0001hH-5l for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:59 -0400 Received: by mail-pg1-x52d.google.com with SMTP id f4so7850447pgc.12 for ; Mon, 22 Aug 2022 08:31:35 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=/MKMIebQa16txYgeu/nYxxKn3UXY1gtLHITpx3nLDs0=; b=SbFbWKYCTKD7u0+pleQnrxC3QgGNlzsHrrw6XHewc/uVgJBhtoxAEwb49KAPLxb5fQ rM77hDiA96cK88J0P95nz0ML8lQ1L3HbMOz8iUjszgMtC41faueumI4blOr6zpev3I82 7+Y3ZGN6JnZA/+ve7xUHx6hAdUurIhNVx3frqPT0Zrm4aQitADOrrvWrr80bQmEhdqui 2C3yUprVh9J1nl3KTVqktuTbz7AKflcJ9BCZq73Y4qagELIbeeABH+1xCEizp1PbAkOm 29PL+/Z9yhhbiDkvfnIhQuwJwqu0D7cjJLzF6ilvvWA3TIQ3SW+BQ23V3HuGl9tkDDoU 1keQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=/MKMIebQa16txYgeu/nYxxKn3UXY1gtLHITpx3nLDs0=; b=0XWnzceysmHMcVBJ1ct7xFu9I1hWBaxw1nG06dd2k06yYF8cGmnMu8vkB1bp3N4YGY rFJVmH5IqqPg3+lSTUI42kBM6Khbvz/bC6aAcxR78vsGdb5SYqUIacKgJo7/pLW2RwoF cYrVkrUNasnnpbjDGsde+ueyXEVE/vr6omfoZZEuFkaDS3Fb1mFEx3gpI40rA9ptUe/l 5/pGQDDl1xkRWWaV7cb9xyYcWsQM1s7ioo9FZb/Pe+xuqvbYG6zpVqQuXwbP2gmOVhOj WELhTJyk++3JJ95z6OlxhtNloQW6Xntpwdwwi4OyGT7wbq4mRkVqmqSGsO35hpfi9ZYb Kjlg== X-Gm-Message-State: ACgBeo3rpOmQLf5ajiQOpS4EARomnvEBb3wapqKeaLh4TNtMtwxl8kI2 TCNQ8mZnIQz2bd6IT7s8vgP9Tg+c6VRmEg== X-Google-Smtp-Source: AA6agR5EYu4+i4bENaGnu5mwa9ILuX+PfTBp/AXKjiFcrmmOIXy75mybrSW241MoYt/MVTXdtm4X3g== X-Received: by 2002:a63:c141:0:b0:429:fadb:7138 with SMTP id p1-20020a63c141000000b00429fadb7138mr17126964pgi.563.1661182294791; Mon, 22 Aug 2022 08:31:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 60/66] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Date: Mon, 22 Aug 2022 08:27:35 -0700 Message-Id: <20220822152741.1617527-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661193297624100001 Content-Type: text/plain; charset="utf-8" Separate S1 translation from the actual lookup. Will enable lpae hardware updates. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 83 +++++++++++++++++++++++++----------------------- 1 file changed, 44 insertions(+), 39 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e898db8765..9ccbc9bd2b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -267,37 +267,29 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, } =20 /* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, +static uint32_t arm_ldl_ptw(CPUARMState *env, const S1TranslateResult *s1, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - S1TranslateResult s1; uint32_t data; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)= ) { - /* Failure. */ - assert(fi->s1ptw); - return 0; - } - - if (likely(s1.hphys)) { + if (likely(s1->hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (s1.be) { - data =3D ldl_be_p(s1.hphys); + if (s1->be) { + data =3D ldl_be_p(s1->hphys); } else { - data =3D ldl_le_p(s1.hphys); + data =3D ldl_le_p(s1->hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1->is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (s1.be) { - data =3D address_space_ldl_be(as, s1.gphys, attrs, &result); + if (s1->be) { + data =3D address_space_ldl_be(as, s1->gphys, attrs, &result); } else { - data =3D address_space_ldl_le(as, s1.gphys, attrs, &result); + data =3D address_space_ldl_le(as, s1->gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; @@ -308,37 +300,29 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, return data; } =20 -static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUIdx ptw_idx, +static uint64_t arm_ldq_ptw(CPUARMState *env, const S1TranslateResult *s1, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - S1TranslateResult s1; uint64_t data; =20 - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, &s1, fi)= ) { - /* Failure. */ - assert(fi->s1ptw); - return 0; - } - - if (likely(s1.hphys)) { + if (likely(s1->hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (s1.be) { - data =3D ldq_be_p(s1.hphys); + if (s1->be) { + data =3D ldq_be_p(s1->hphys); } else { - data =3D ldq_le_p(s1.hphys); + data =3D ldq_le_p(s1->hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D s1.is_secure }; + MemTxAttrs attrs =3D { .secure =3D s1->is_secure }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 - if (s1.be) { - data =3D address_space_ldq_be(as, s1.gphys, attrs, &result); + if (s1->be) { + data =3D address_space_ldq_be(as, s1->gphys, attrs, &result); } else { - data =3D address_space_ldq_le(as, s1.gphys, attrs, &result); + data =3D address_space_ldq_le(as, s1->gphys, attrs, &result); } if (unlikely(result !=3D MEMTX_OK)) { fi->type =3D ARMFault_SyncExternalOnWalk; @@ -470,6 +454,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t= address, int domain =3D 0; int domain_prot; hwaddr phys_addr; + S1TranslateResult s1; uint32_t dacr; =20 /* Pagetable walk. */ @@ -479,7 +464,10 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_= t address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, is_secure, &s1, fi= )) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -517,7 +505,11 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_= t address, /* Fine pagetable. */ table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, &s1, fi)) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -593,6 +585,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, int domain_prot; hwaddr phys_addr; uint32_t dacr; + S1TranslateResult s1; bool ns; =20 /* Pagetable walk. */ @@ -602,7 +595,10 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_= t address, fi->type =3D ARMFault_Translation; goto do_fault; } - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, is_secure, &s1, fi= )) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -655,7 +651,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_= t address, ns =3D extract32(desc, 3, 1); /* Lookup l2 entry. */ table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(env, table, is_secure, mmu_idx, ptw_idx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, table, + is_secure, &s1, fi)) { + goto do_fault; + } + desc =3D arm_ldl_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } @@ -1231,13 +1231,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, */ tableattrs =3D is_secure ? 0 : (1 << 4); for (;;) { + S1TranslateResult s1; uint64_t descriptor; bool nstable; =20 descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - descriptor =3D arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, ptw_i= dx, fi); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, + !nstable, &s1, fi)) { + goto do_fault; + } + descriptor =3D arm_ldq_ptw(env, &s1, fi); if (fi->type !=3D ARMFault_None) { goto do_fault; } --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=xOAKE939prezp00RTq/5i5dmdsj8gga6ARA2/sjO9wc=; b=aEUlWy3UoR7d+JIoPwO0XW8pQ3zIAH5rPvxXw/p8Y6AVOQqt6VrkcneDRnWb5YbPH6 h/M4gSWKD6EVLRL7j6MiMNcjdLmw/EklPOTSgi5rsJvLFUaSvPAaxjkDpZjh+Nni0leT 0DQ3n1gG1OEHI+TwAzM3CzKYp3GYsK9wXaggQlj2hv1jQSjF1Ra5fpsVM7W4feIBR+qN V8QIFKLe+fre52IGb8PP5wjXpgrNvoudilOFNwBiDPgZYyr4dhkLWfoHwftpdVeuzm5S wfqkAj1Xk6qTaQSgl6zBap7fUY6LVVcGa2kpEKZ51BiC5AeMI1jGBEBVHHmZzSy399a2 u4MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=xOAKE939prezp00RTq/5i5dmdsj8gga6ARA2/sjO9wc=; b=PsA9rSMHTHAoj2tERxddx+bCVv5WgCGDUrL9vwT/hMed24JYhBxQ+gIkHIK7syBh2q CoJNae1zG1qjLdGew4RLA6BZISQMl4wy8aDZKmrqwr7SuVapOI0y3GTnSkLlyaKJsajp H0lwG4FhnC3YrvSuCRn7F+3CQgV42YQNDzhSptiJ8AkBM9N2eST3yy5S0Gt4c56TLUdO o8XFotvz3PL9vfZJlPpK5rXWBT620oK53KWzI8CnWq15gKcCZ1I7zc39eRLGcBCEE1hi GQJ/pOXIYc2v9DgUZDPFw3AWr+ioMyffNT3uT+5+sL/qLuMr6jkKkNhrOyBGJ0wPjouI 0G0A== X-Gm-Message-State: ACgBeo3rNHGSrtTbL/9nhs0UU6UJFIRBMdbbkaZr3x8MfjPsk2bFSP5P Rpwo+OK/eDFnf41+YAgsTB/FF76IVr4AiA== X-Google-Smtp-Source: AA6agR51iiSdsWShyljGQPwYpGknEzoy+EYr3M25RyepeI81nAvo43d+QVPog90NDIN4bo3yR6sbXg== X-Received: by 2002:a17:90b:4f91:b0:1cd:3a73:3a5d with SMTP id qe17-20020a17090b4f9100b001cd3a733a5dmr23543343pjb.98.1661182295513; Mon, 22 Aug 2022 08:31:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 61/66] target/arm: Add ARMFault_UnsuppAtomicUpdate Date: Mon, 22 Aug 2022 08:27:36 -0700 Message-Id: <20220822152741.1617527-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189477951100001 Content-Type: text/plain; charset="utf-8" This fault type is to be used with FEAT_HAFDBS when the guest enables hw updates, but places the tables in memory where atomic updates are unsupported. Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index de8b3392a8..46012a349b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -338,6 +338,7 @@ typedef enum ARMFaultType { ARMFault_AsyncExternal, ARMFault_Debug, ARMFault_TLBConflict, + ARMFault_UnsuppAtomicUpdate, ARMFault_Lockdown, ARMFault_Exclusive, ARMFault_ICacheMaint, @@ -524,6 +525,9 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *= fi) case ARMFault_TLBConflict: fsc =3D 0x30; break; + case ARMFault_UnsuppAtomicUpdate: + fsc =3D 0x31; + break; case ARMFault_Lockdown: fsc =3D 0x34; break; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661193679; cv=none; d=zohomail.com; s=zohoarc; b=O6lRdILUI7v5CoWNWPe8XFWucRHhUPtKh2x0/A0+6MV4cJ7J94dBSmvpClEUNHnDD0X1jNhef37NVqRJf+cGe2UWYj6x2Hjx0wJVPCJTuNq4SdJVQyMBoNQHXoN5HjjqTd7LNfYa64RZMbXWvl6akyjCZvSKru6Anx33wE3ukgs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661193679; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ytgICZSLAKF7RSSydO7buGS+w8FoXAg2T8FlAnkcjhg=; b=HCFURV+7KVIERm3P0Z7yLOJEVSpQtpBgooUZzPXrC3TVApfRweMUAhc/klb5nAazlCPI44F947IVxfajPrOVv6lk+ifqLQU7jcKCh4/LuAvx2gfYXp/K2igwRjyUocktLW9q6HWEfrDpH5tE7GzAMw/PnH5q+OuNXCo/MzgMaZE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661193679550124.49017895695624; Mon, 22 Aug 2022 11:41:19 -0700 (PDT) Received: from localhost ([::1]:38922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQCMQ-0006yG-8X for importer@patchew.org; Mon, 22 Aug 2022 14:41:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9PE-0004yV-Co for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:32:00 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:55830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9P0-0001hn-6O for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:32:00 -0400 Received: by mail-pj1-x1031.google.com with SMTP id pm13so2434936pjb.5 for ; Mon, 22 Aug 2022 08:31:37 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=ytgICZSLAKF7RSSydO7buGS+w8FoXAg2T8FlAnkcjhg=; b=E0Hf//zePpG0BPKGWJamzh4q+uszOju1qBe/XZyGS3bfXWC7c2oM5jF7dPXyj6nzhN P9O1iNU7cRO7rBH0DvoF5wd90noO7+u9sOhzo/vcV45bJfUZSD21BUKuu6Si0H1rLOXG VQO60v/V1cMHPTqD9EaWJN9pmswzinkc5Ta+D3CgfeTqH9Ra6ZbCpM5iPKCQTstLDRv5 798EeNH3865CZlakXGr8iUswJ/9Lw1aLa61tUa9xZIJvnj5wsEDla02BSbrz8rPT4rKR YKb8cVLTG/x2P5EPptMewWjnvMidBToYKRGd0tlaxJXwGGdwf8ijCox3R2DuGdx/REei gkSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=ytgICZSLAKF7RSSydO7buGS+w8FoXAg2T8FlAnkcjhg=; b=QFDw3mrFReGVIW0OsM+zWyaprTjE1tTd919+zfcHJX1P7f0mbdWiraz1Vz7tpGosHQ Raww62kUHWbdROkzy8EhlBql42fNBJ1mhXcJaJcDyu2Ui7H2FhRQA0gzszPVOpQ0N/Zq JDcz3B1J+D2PxNGc69CXCxmJGTlkhyUd7NVqkEGRVHYRrVBbmuo9QEO/n8+A0EwB69jD Zi3AWp+wa+3r3alhpn4HtBJgYIycpTYdloSZcRCpNgXdp1x6c07hvqkDC8LpiBO6U11K vpbe8Lkdr0jvwhfJGAa0UnKVbouOetQZMj1GmWZlb+cSHsPx5tvMpPMo9Ctpzap2/eFf qAtQ== X-Gm-Message-State: ACgBeo34vy727VvcBNxG23XKdyvuWUzrK5wWl3Y5gulNnaCPclPjuUXv cbNtRCOsYME6tqmFxTRHrubQCnwxJd9T4A== X-Google-Smtp-Source: AA6agR4TgvaPxufnqd5c3nwOm6aOkv5BzVDHEgiRTWajXo34JksPxhIn1/OZrbSnSTuxZBpzukOZiQ== X-Received: by 2002:a17:903:2049:b0:172:eb95:c61e with SMTP id q9-20020a170903204900b00172eb95c61emr5447482pla.74.1661182296209; Mon, 22 Aug 2022 08:31:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 62/66] target/arm: Remove loop from get_phys_addr_lpae Date: Mon, 22 Aug 2022 08:27:37 -0700 Message-Id: <20220822152741.1617527-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661193680665100001 Content-Type: text/plain; charset="utf-8" The unconditional loop was used both to iterate over levels and to control parsing of attributes. Use an explicit goto in both cases. While this appears less clean for iterating over levels, we will need to jump back into the middle of this loop for atomic updates, which is even uglier. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 176 +++++++++++++++++++++++------------------------ 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9ccbc9bd2b..d0981d94d1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1032,6 +1032,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); bool guarded =3D false; + S1TranslateResult s1; + uint64_t descriptor; + bool nstable; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1230,96 +1233,93 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * bits at each step. */ tableattrs =3D is_secure ? 0 : (1 << 4); - for (;;) { - S1TranslateResult s1; - uint64_t descriptor; - bool nstable; =20 - descaddr |=3D (address >> (stride * (4 - level))) & indexmask; - descaddr &=3D ~7ULL; - nstable =3D extract32(tableattrs, 4, 1); - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, - !nstable, &s1, fi)) { - goto do_fault; - } - descriptor =3D arm_ldq_ptw(env, &s1, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - - if (!(descriptor & 1) || - (!(descriptor & 2) && (level =3D=3D 3))) { - /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; - } - - descaddr =3D descriptor & descaddrmask; - - /* - * For FEAT_LPA and PS=3D6, bits [51:48] of descaddr are in [15:12] - * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of - * descaddr are in [9:8]. Otherwise, if descaddr is out of range, - * raise AddressSizeFault. - */ - if (outputsize > 48) { - if (param.ds) { - descaddr |=3D extract64(descriptor, 8, 2) << 50; - } else { - descaddr |=3D extract64(descriptor, 12, 4) << 48; - } - } else if (descaddr >> outputsize) { - fault_type =3D ARMFault_AddressSize; - goto do_fault; - } - - if ((descriptor & 2) && (level < 3)) { - /* - * Table entry. The top five bits are attributes which may - * propagate down through lower levels of the table (and - * which are all arranged so that 0 means "no effect", so - * we can gather them up by ORing in the bits at each level). - */ - tableattrs |=3D extract64(descriptor, 59, 5); - level++; - indexmask =3D indexmask_grainsize; - continue; - } - /* - * Block entry at level 1 or 2, or page entry at level 3. - * These are basically the same thing, although the number - * of bits we pull in from the vaddr varies. Note that although - * descaddrmask masks enough of the low bits of the descriptor - * to give a correct page or table address, the address field - * in a block descriptor is smaller; so we need to explicitly - * clear the lower bits here before ORing in the low vaddr bits. - */ - page_size =3D (1ULL << ((stride * (4 - level)) + 3)); - descaddr &=3D ~(hwaddr)(page_size - 1); - descaddr |=3D (address & (page_size - 1)); - /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { - /* Stage 2 table descriptors do not include any attribute fiel= ds */ - break; - } - /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ - guarded =3D extract64(descriptor, 50, 1); /* GP */ - if (param.hpd) { - /* HPD disables all the table attributes except NSTable. */ - break; - } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - /* - * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 - * means "force PL1 access only", which means forcing AP[1] to 0. - */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> = AP[1] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A= P[2] */ - break; + next_level: + descaddr |=3D (address >> (stride * (4 - level))) & indexmask; + descaddr &=3D ~7ULL; + nstable =3D extract32(tableattrs, 4, 1); + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, descaddr, + !nstable, &s1, fi)) { + goto do_fault; } + descriptor =3D arm_ldq_ptw(env, &s1, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + + if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { + /* Invalid, or the Reserved level 3 encoding */ + goto do_fault; + } + + descaddr =3D descriptor & descaddrmask; + + /* + * For FEAT_LPA and PS=3D6, bits [51:48] of descaddr are in [15:12] + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. + */ + if (outputsize > 48) { + if (param.ds) { + descaddr |=3D extract64(descriptor, 8, 2) << 50; + } else { + descaddr |=3D extract64(descriptor, 12, 4) << 48; + } + } else if (descaddr >> outputsize) { + fault_type =3D ARMFault_AddressSize; + goto do_fault; + } + + if ((descriptor & 2) && (level < 3)) { + /* + * Table entry. The top five bits are attributes which may + * propagate down through lower levels of the table (and + * which are all arranged so that 0 means "no effect", so + * we can gather them up by ORing in the bits at each level). + */ + tableattrs |=3D extract64(descriptor, 59, 5); + level++; + indexmask =3D indexmask_grainsize; + goto next_level; + } + + /* + * Block entry at level 1 or 2, or page entry at level 3. + * These are basically the same thing, although the number + * of bits we pull in from the vaddr varies. Note that although + * descaddrmask masks enough of the low bits of the descriptor + * to give a correct page or table address, the address field + * in a block descriptor is smaller; so we need to explicitly + * clear the lower bits here before ORing in the low vaddr bits. + */ + page_size =3D (1ULL << ((stride * (4 - level)) + 3)); + descaddr &=3D ~(page_size - 1); + descaddr |=3D (address & (page_size - 1)); + /* Extract attributes from the descriptor */ + attrs =3D extract64(descriptor, 2, 10) + | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + /* Stage 2 table descriptors do not include any attribute fields */ + goto skip_attrs; + } + /* Merge in attributes from table descriptors */ + attrs |=3D nstable << 3; /* NS */ + guarded =3D extract64(descriptor, 50, 1); /* GP */ + if (param.hpd) { + /* HPD disables all the table attributes except NSTable. */ + goto skip_attrs; + } + attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=3D 1 + * means "force PL1 access only", which means forcing AP[1] to 0. + */ + attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> AP[1= ] */ + attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> AP[2]= */ + skip_attrs: + /* * Here descaddr is the final physical address, and attributes * are all in attrs. --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661188783; cv=none; d=zohomail.com; s=zohoarc; b=mI5FsbDx5geQl7MWEL3rMb5O1FTV4rNYm+KpZ+Yrhz+BMPMj7fdO9hg1HIoC1BV2jTOvwFJRkgm1IFOZNtt77hz6vCeSmAC2rzYTXR8lKvKSZ05pY9xtTUyN+zam0KpEcd4k0eWsWdDyrdYmmhhH9iWd4BiWt+ZjHYg9qOLNOVo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661188783; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=85RaASzLJRUjYB2qlDOH84qmiuMV9YHjafoqZXxUOdU=; b=RQx+XWwehFzWFHLlK9gcttX2cjNzfOlbeNqhGmzmDH5pR2zAfI1UPpo8j5mkQ4br+L/4++U/DLgRYIRDh+/rHzi9jplcjkSrqBTAk0DFrlcPkDIuOw5skuS6N6zVHpnZjiCR+OvRL0PQRa4tpIjkdJ7wdsgVxza8Zzq6Tdp2Hv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661188783294596.5359812759353; Mon, 22 Aug 2022 10:19:43 -0700 (PDT) Received: from localhost ([::1]:42850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQB5R-0006SN-7o for importer@patchew.org; Mon, 22 Aug 2022 13:19:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9PC-0004v1-Fs for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:58 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:36386) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Ov-0001hw-BS for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:58 -0400 Received: by mail-pf1-x433.google.com with SMTP id w29so5121499pfj.3 for ; Mon, 22 Aug 2022 08:31:39 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=85RaASzLJRUjYB2qlDOH84qmiuMV9YHjafoqZXxUOdU=; b=MxYK43xoqwGL/CXWmMqzDSBIbQLaX9W2NsN3UHIBRH4DnjD8MuvRi2KrB+V/VsUEqI vBDwA1G+JXUnQgQFWBFBgt0ts1n1pVsq0Wzh517Ilg1aY9TqztBqHs1lCRuYsCT5lJ98 MluMV914+p6At911sebK3aMozAjUV4EXwHeJy47JnxInQ//0BQZKj/DOXwF6F3sT4crv kIySKgyKsWDoYipbtQOsLBca3Qc6n74Af96d5jt3rKQrMY6oAB9JBLjs56XDeWQuAufm tqj1wh1+szapDXdd/weTyCbjN8kXv4pynqPXi252eQDiMQbr6C2/Pw7DmHr+mLwdngTL rIdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=85RaASzLJRUjYB2qlDOH84qmiuMV9YHjafoqZXxUOdU=; b=ZNbhElg7heeP/nrslcH7MCO0V3NrA1rEAH/4s2lMNRweLUMc3LP8SkNH3Z7zLUQAV7 ClbBnauTbNU8MGjKKSKWOH7wwXAxpAHQGTebli/R9mzipNFz+xtN9wupKiEYsTsJCf46 jYtqt7GuHEylkKws45AroP3n2C5QL/PD/uVpdBK0efqdsx3XKI05b+qx2VIW3WszrmES 11ZXUjhVqh512hAyYAE2Gj1OXB6IYFRKjuu+L8bOy5KNEjC3ykk0byCIkaSY0ppfSban NfH1Stkytge2ynqOQx9YA4X5NQspnWjLVMw9dByJ9TQNmNR1uYrKNV0eb6Z1RVx9l1EM q0dQ== X-Gm-Message-State: ACgBeo3QNOaC052CPjSCGlqDVEbU8B8WsnfEGvKhzALRZOx1B0Whs2Z7 48a8gTYAM2Debf+Q3X+5m3ZXd1E8gxTDzQ== X-Google-Smtp-Source: AA6agR7YdU83dgsioDJnOJfdAKvHGrEeyxt3KkG9b6ZmTetxDFnl5fzghzF71Xhwyvdd2601SxDZ0Q== X-Received: by 2002:a63:89c6:0:b0:429:a28d:7b4 with SMTP id v189-20020a6389c6000000b00429a28d07b4mr17261788pgd.42.1661182297019; Mon, 22 Aug 2022 08:31:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 63/66] target/arm: Fix fault reporting in get_phys_addr_lpae Date: Mon, 22 Aug 2022 08:27:38 -0700 Message-Id: <20220822152741.1617527-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661188783828100001 Content-Type: text/plain; charset="utf-8" Always overriding fi->type was incorrect, as we would not properly propagate the fault type from S1_ptw_translate, or arm_ldq_ptw. Simplify things by providing a new label for a translation fault. For other faults, store into fi directly. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d0981d94d1..5f3841b466 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1015,8 +1015,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); - /* Read an LPAE long-descriptor translation table. */ - ARMFaultType fault_type =3D ARMFault_Translation; uint32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1054,8 +1052,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * so our choice is to always raise the fault. */ if (param.tsz_oob) { - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } =20 addrsize =3D 64 - 8 * param.tbi; @@ -1092,8 +1089,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, addrsize - inputsize); if (-top_bits !=3D param.select) { /* The gap between the two regions is a Translation fault */ - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } } =20 @@ -1125,7 +1121,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * Translation table walk disabled =3D> Translation fault on TLB m= iss * Note: This is always 0 on 64-bit EL2 and EL3. */ - goto do_fault; + goto do_translation_fault; } =20 if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { @@ -1156,8 +1152,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, if (param.ds && stride =3D=3D 9 && sl2) { if (sl0 !=3D 0) { level =3D 0; - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } startlevel =3D -1; } else if (!aarch64 || stride =3D=3D 9) { @@ -1176,8 +1171,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride, outputsize); if (!ok) { - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } level =3D startlevel; } @@ -1199,7 +1193,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D extract64(ttbr, 2, 4) << 48; } else if (descaddr >> outputsize) { level =3D 0; - fault_type =3D ARMFault_AddressSize; + fi->type =3D ARMFault_AddressSize; goto do_fault; } =20 @@ -1249,7 +1243,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, =20 if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; + goto do_translation_fault; } =20 descaddr =3D descriptor & descaddrmask; @@ -1267,7 +1261,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D extract64(descriptor, 12, 4) << 48; } } else if (descaddr >> outputsize) { - fault_type =3D ARMFault_AddressSize; + fi->type =3D ARMFault_AddressSize; goto do_fault; } =20 @@ -1324,9 +1318,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type =3D ARMFault_AccessFlag; if ((attrs & (1 << 8)) =3D=3D 0) { /* Access flag */ + fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 @@ -1343,8 +1337,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 - fault_type =3D ARMFault_Permission; if (!(result->f.prot & (1 << access_type))) { + fi->type =3D ARMFault_Permission; goto do_fault; } =20 @@ -1389,8 +1383,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->f.lg_page_size =3D ctz64(page_size); return false; =20 -do_fault: - fi->type =3D fault_type; + do_translation_fault: + fi->type =3D ARMFault_Translation; + do_fault: fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=AjfIQKU/myD5+QYQH5XxFY0Vc0OPmbgLDaWoxfP3y8A=; b=BSfrUysRXDtXKaltD3RZK88blSKhEuGYVURM07qbgl8axOLf6mZyPqqlXVYsbLvjHQ sdE6snePuY1mRbYhrERigGxMjJuoD2uM+cDa4ePnl3IWxpwFLigjD7P5nfXL92cRoIGZ etMRbSBf13Pw6Ox4jmqC7vKtWOO7sPrE/PxLpbrQ5/yXDuun8xajjq6PZ1hztqey/gLX HIZTeDaGtwthhsPwSxswJwnA+dNnhoYWN3sBPM/HvxKQYEG1e9oGhqjCc5KbC4JgreRQ 1nrwCpw5aZw37XkLUKN99ZSaKwiDAllpOD92nSGaqjCF1ziySn9s6BD/9y6MbvQwH40u zLhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=AjfIQKU/myD5+QYQH5XxFY0Vc0OPmbgLDaWoxfP3y8A=; b=3G1KOFAL2etpKG93XpGFA1vdAnhwmK78btPlo5sMblwgo3ERlTOYIsLBQMNkjrwAxb c4N9lD1Jl3THHd4rqQ8qCN0zaJ00zxekmELVnypEGlYooVfQ6rbzvTbbBveu63wpjFps w03Bw1lum0i9wgDFTJbtGJP7FCQhythQXu9dQ8VXGNplJ//2LeZsFySpDWfEXK4y9xKp +30Qw198EkPj4VF3wOSE2ehieKI7NwMa3fsX6QhE3srJSW8YVn9FJt4utIEolTniMXOL OApR2gMCo/RTkGGtHNWypvQkcBzc0XRLFpU+dgrldsEQE9oqEbZKWPiGXEXpW3HWhlD/ Nn1w== X-Gm-Message-State: ACgBeo0YwMZL9BB4FbrG9QhLdnu3zgeV/ZljgvYSIwJsvAr5O/KpY8c3 BpW7lHf9+BHv7aY3ddYyAOKLcc6XLuIu8A== X-Google-Smtp-Source: AA6agR5pc65/g/jWu8i1wHryifRONHCmmAd7+u7FgUwl4ix6plRJ37BWWak1EEWwlT8PYg1ObUQh2w== X-Received: by 2002:a17:90b:3c04:b0:1fb:2220:ad7f with SMTP id pb4-20020a17090b3c0400b001fb2220ad7fmr7390535pjb.182.1661182297673; Mon, 22 Aug 2022 08:31:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 64/66] target/arm: Don't shift attrs in get_phys_addr_lpae Date: Mon, 22 Aug 2022 08:27:39 -0700 Message-Id: <20220822152741.1617527-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661189109800100001 Content-Type: text/plain; charset="utf-8" Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5f3841b466..068ff2025a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1021,7 +1021,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; target_ulong page_size; - uint32_t attrs; + uint64_t attrs; int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); @@ -1291,49 +1291,48 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, descaddr &=3D ~(page_size - 1); descaddr |=3D (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); + attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 1= 2)); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { /* Stage 2 table descriptors do not include any attribute fields */ goto skip_attrs; } /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ + attrs |=3D nstable << 5; /* NS */ guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D=3D 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> AP[1= ] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> AP[2]= */ + attrs &=3D ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] =3D> AP[1= ] */ + attrs |=3D extract32(tableattrs, 3, 1) << 7; /* APT[1] =3D> AP[2]= */ skip_attrs: =20 /* * Here descaddr is the final physical address, and attributes * are all in attrs. */ - if ((attrs & (1 << 8)) =3D=3D 0) { + if ((attrs & (1 << 10)) =3D=3D 0) { /* Access flag */ fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 - ap =3D extract32(attrs, 4, 2); + ap =3D extract32(attrs, 6, 2); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; - xn =3D extract32(attrs, 11, 2); + xn =3D extract64(attrs, 54, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 3, 1); - xn =3D extract32(attrs, 12, 1); - pxn =3D extract32(attrs, 11, 1); + ns =3D extract32(attrs, 5, 1); + xn =3D extract64(attrs, 54, 1); + pxn =3D extract64(attrs, 53, 1); result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); } =20 @@ -1358,10 +1357,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { result->cacheattrs.is_s2_format =3D true; - result->cacheattrs.attrs =3D extract32(attrs, 0, 4); + result->cacheattrs.attrs =3D extract32(attrs, 2, 4); } else { /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); + uint8_t attrindx =3D extract32(attrs, 2, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); result->cacheattrs.is_s2_format =3D false; @@ -1376,7 +1375,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, if (param.ds) { result->cacheattrs.shareability =3D param.sh; } else { - result->cacheattrs.shareability =3D extract32(attrs, 6, 2); + result->cacheattrs.shareability =3D extract32(attrs, 8, 2); } =20 result->f.phys_addr =3D descaddr; --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661192943; cv=none; d=zohomail.com; s=zohoarc; b=QnTQWsfyvxfz/kk1J5O/fjQ08Euv5eeRTTveoqDrpcH3Q65zjOzv9VP0iP1nYx5zH8GcvYOeCfUdgxKJMdj06XW4nVCCfsDHNjyDoZvfVdMCDSiXMjJ68GYBh+g7k8b6poADg5ycC//bEVXeKwCMlNQY6yS8BIvNTHR8mthq5DE= ARC-Message-Signature: i=1; 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([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=717fzziULIfrv0GZaFcKnjtRk3XAFj/8qM7MoF3/+do=; b=omKxley/3yr+rIUu3wY3+x6pT4C8/r5M8W9+CWcEKcyyHXLzXQ/sldfdbDwZNMIK0w 21GK5i3RpQAoIsW48nVITOfAV8KvybMdcEGAeQ2GBQwjcGA40AzYISbGZH0DAHuqzjKQ VrgPM6e/p+Q/5liy6TalDUYfR6x/0lbK3bC2eNP/8mmdClT3CN54PWbxrFIXxtsIMhF+ IjmoDmnC20FKc7pC0LzGTzbFMgqMhHkXQee5tNcEgXBNkKDw1BkySmX16hdgYQXCLfQA PaMT7iDNqsZK7439Diu8NBAa6KUISJPiHjsUipvMABPh9B5JrmcwfaDpEze87FXwaYtf aqlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=717fzziULIfrv0GZaFcKnjtRk3XAFj/8qM7MoF3/+do=; b=Fw9R0dMucraWSHSTRMv03TFIy4HEazQ43LgF6l0whU3KwMhRrtSCQNasCXcGoo0rPc c2XxJthy7+8EgfLiv/uaY1LqHoyJS0HarGL1g0NtEEj69OTm72JCnZr/heOo4p9MQTuF Q18oct6aCKBaaXh3JyfQ8x6HLnk+nP1WSQaaD/PdNl8Ph8JPd6z1T3MWBR8pjVY3+guu 7zj0sMOlEOFia0tlOlE+Z3pikLdXYmOfgapIu936tZejMDy+uocMP/oilhL3gIJp/oGj aauYqx1VD+UCeRLDkA2c6pzxqHCG6rrXu6Au8FfPyUcB/FSRf1tQ0NB93iN7iAKp8BG7 k/Rg== X-Gm-Message-State: ACgBeo2biM5sJ4ztGPwfEQFE00MIZ+9pot8fzKGyhMi573J37HckhNii KoRc7E+atAzlWmnRanRk1h8syFMsTHNYvA== X-Google-Smtp-Source: AA6agR45WyMGyfjpGzXOhyJJhwf5G20qNOe1hrNEueg7r/KH6IYZ3xjztL2hkad+Nxsch0txxYX1BA== X-Received: by 2002:a17:90a:f88:b0:1fa:da0f:5e6 with SMTP id 8-20020a17090a0f8800b001fada0f05e6mr20236534pjz.102.1661182298340; Mon, 22 Aug 2022 08:31:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 65/66] target/arm: Consider GP an attribute in get_phys_addr_lpae Date: Mon, 22 Aug 2022 08:27:40 -0700 Message-Id: <20220822152741.1617527-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661192945511100001 Content-Type: text/plain; charset="utf-8" Both GP and DBM are in the upper attribute block. Extend the computation of attrs to include them, then simplify the setting of guarded. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 068ff2025a..c38c7d2a65 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1029,7 +1029,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); - bool guarded =3D false; S1TranslateResult s1; uint64_t descriptor; bool nstable; @@ -1291,7 +1290,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr &=3D ~(page_size - 1); descaddr |=3D (address & (page_size - 1)); /* Extract attributes from the descriptor */ - attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 1= 2)); + attrs =3D descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 1= 4)); =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { /* Stage 2 table descriptors do not include any attribute fields */ @@ -1299,7 +1298,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, } /* Merge in attributes from table descriptors */ attrs |=3D nstable << 5; /* NS */ - guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ goto skip_attrs; @@ -1352,7 +1350,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.guarded =3D guarded; + result->f.guarded =3D extract64(attrs, 50, 1); /* GP */ } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { --=20 2.34.1 From nobody Tue May 14 09:55:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661192576; cv=none; d=zohomail.com; s=zohoarc; b=KxPCArWIHW3sVVHuSBpawsD2kyA2MypPbmfGdGbbpTy5lCaEhARWy+K7GuV5Owe1TMIkiFk1TsjeWDNy6HDnuLPXPSqxd6YAeytO7G1KR+mRQxkKYgnFrufDy0BSzJWBK+nkgRfuYjeXHVzoE6hfmttlaJG8hggziafnNmGjswg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661192576; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=izCCuU3gf6AuQLDLTtnxcsJhF9AvhqthHQ21e7M+uSM=; b=V47hJxGD8pYaJNP9flptjoy9cP7YV2pf84DXe3yZ4MQdoe7RcLMsLamZn9jNqh7yPzGLr8hvjlZpsEmR7ZAGIOvV/pLNm0bg3rjDKy+JLfm0WTnACHnjQYiD20/1SegLvG4OQe1MAd7dQfErAy1iwghnrnJUrElaM6n6YYuNK60= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166119257612853.12889627010179; Mon, 22 Aug 2022 11:22:56 -0700 (PDT) Received: from localhost ([::1]:52392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQC4c-00051Q-Lm for importer@patchew.org; Mon, 22 Aug 2022 14:22:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ9P5-0004og-9D for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:52 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:44801) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ9Ox-0001iT-Eu for qemu-devel@nongnu.org; Mon, 22 Aug 2022 11:31:50 -0400 Received: by mail-pj1-x1034.google.com with SMTP id r15-20020a17090a1bcf00b001fabf42a11cso11662061pjr.3 for ; Mon, 22 Aug 2022 08:31:40 -0700 (PDT) Received: from stoup.. ([71.212.157.236]) by smtp.gmail.com with ESMTPSA id i6-20020a17090a3d8600b001f262f6f717sm10353835pjc.3.2022.08.22.08.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 08:31:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=izCCuU3gf6AuQLDLTtnxcsJhF9AvhqthHQ21e7M+uSM=; b=SaO8ygmGMmeUluxN38vfjTiItjvH1m0NHI0Lb/kUEb+KQnzN/Z7U7RQXJe+6NOPMlz 3UwlxziREax1bZfyRoA09D/pluLkOeviYUuHHl0JjhzCpvoLEdL3YM0KFnPXwkUhR8th WitbLrgAa6Yl+oX+OQ80yv4ApjJ567niBY5J7+4vFj961ewKAL8QwirEwoF0TqAsG8op buC2nUTDFdxmiq/GmPOTOIuJKXxjjVqZrCmoiw8A9k9jMLrWj7Y2t5SQU4c3AFtGkTMl GWp6mRdM9I8s6qLLOHwSH5yJl8MygyogUKBtQseldEfDFSfSmgQ8reJlt0CFUB0vMxjY TuBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=izCCuU3gf6AuQLDLTtnxcsJhF9AvhqthHQ21e7M+uSM=; b=F9/HYlndFYJ9DpIGRXqtZUppL+u3xzjaX7hz0iwY2bYH/Y/HG+ZlvxongLF3Jm6dcd yBqEp6kOAZBAdm2eE1PgvKM7OzOxghkUJLeFfRzvFOAt7Dxts1Y1pzRR+R8uvTTcxtR1 FimH5GziaqXbGc9geOId4xrBZlBKPbJBnaYYN3QxvGfdaitdS9I2OHACifpd4qwiFpE0 wXt0KJB++/njuVbeIkmJxI+36fx7nFBxWdSThciIyohGnjTTjW0da+LTvlA4gGbqTSWi 4+3nKAyU62zzYiRnZZQPoKyY1boVu8mRmzaokX2xCrfcUYZWQBv4xeuygAAP+sn7oFhB mSRQ== X-Gm-Message-State: ACgBeo0RM3gmaLKhWNv9A8tmFr9tPNIE3WcV61cx5nAINjXALhvg+kO9 Czkn1JSZGQvRoAHBrXgwYlaK8Bl6s+GHDQ== X-Google-Smtp-Source: AA6agR4xJpsTWopP+HoYubWpJnKp9MZNRqJQv7kMFXaLeM8kRhk4yA3jZY46fB0d94AnrFubzbt0uQ== X-Received: by 2002:a17:902:f606:b0:172:9c81:d788 with SMTP id n6-20020a170902f60600b001729c81d788mr20446546plg.42.1661182299220; Mon, 22 Aug 2022 08:31:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 66/66] target/arm: Implement FEAT_HAFDBS Date: Mon, 22 Aug 2022 08:27:41 -0700 Message-Id: <20220822152741.1617527-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220822152741.1617527-1-richard.henderson@linaro.org> References: <20220822152741.1617527-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661192577743100001 Content-Type: text/plain; charset="utf-8" Perform the atomic update for hardware management of the access flag and the dirty bit. A limitation of the implementation so far is that the page table itself must already be writable, i.e. the dirty bit for the stage2 page table must already be set, i.e. we cannot set both dirty bits at the same time. This is allowed because it is CONSTRAINED UNPREDICTABLE whether any atomic update happens at all. The implementation is allowed to simply fall back on software update at any time. Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/ptw.c | 115 ++++++++++++++++++++++++++++++++-- 3 files changed, 113 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8e494c8bea..3eee95c39b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -30,6 +30,7 @@ the following architecture extensions: - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) +- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 78e27f778a..98771918c2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1037,6 +1037,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c38c7d2a65..c81c51f60c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -193,6 +193,7 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx, typedef struct { bool is_secure; bool be; + bool rw; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -221,6 +222,8 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUId= x mmu_idx, return false; } =20 + res->rw =3D full->prot & PAGE_WRITE; + if (s2_mmu_idx =3D=3D ARMMMUIdx_Stage2 || s2_mmu_idx =3D=3D ARMMMUIdx_= Stage2_S) { uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); uint8_t s2attrs =3D full->pte_attrs; @@ -333,6 +336,56 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, const S1= TranslateResult *s1, return data; } =20 +static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, + uint64_t new_val, const S1TranslateResult *s1, + ARMMMUFaultInfo *fi) +{ + uint64_t cur_val; + + if (unlikely(!s1->hphys)) { + fi->type =3D ARMFault_UnsuppAtomicUpdate; + fi->s1ptw =3D true; + return 0; + } + +#ifndef CONFIG_ATOMIC64 + /* + * We can't support the atomic operation on the host. We should be + * running in round-robin mode though, which means that we would only + * race with dma i/o. + */ + qemu_mutex_lock_iothread(); + if (s1->be) { + cur_val =3D ldq_be_p(s1->hphys); + if (cur_val =3D=3D old_val) { + stq_be_p(s1->hphys, new_val); + } + } else { + cur_val =3D ldq_le_p(s1->hphys); + if (cur_val =3D=3D old_val) { + stq_le_p(s1->hphys, new_val); + } + } + qemu_mutex_unlock_iothread(); +#else + if (s1->be) { + old_val =3D cpu_to_be64(old_val); + new_val =3D cpu_to_be64(new_val); + cur_val =3D qatomic_cmpxchg__nocheck((uint64_t *)s1->hphys, + old_val, new_val); + cur_val =3D be64_to_cpu(cur_val); + } else { + old_val =3D cpu_to_le64(old_val); + new_val =3D cpu_to_le64(new_val); + cur_val =3D qatomic_cmpxchg__nocheck((uint64_t *)s1->hphys, + old_val, new_val); + cur_val =3D le64_to_cpu(cur_val); + } +#endif + + return cur_val; +} + static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { @@ -1240,6 +1293,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, goto do_fault; } =20 + restart_atomic_update: if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { /* Invalid, or the Reserved level 3 encoding */ goto do_translation_fault; @@ -1317,8 +1371,26 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, */ if ((attrs & (1 << 10)) =3D=3D 0) { /* Access flag */ - fi->type =3D ARMFault_AccessFlag; - goto do_fault; + uint64_t new_des, old_des; + + /* + * If HA is disabled, or if the pte is not writable, + * pass on the access fault to software. + */ + if (!param.ha || !s1.rw) { + fi->type =3D ARMFault_AccessFlag; + goto do_fault; + } + + old_des =3D descriptor; + new_des =3D descriptor | (1 << 10); /* AF */ + descriptor =3D arm_casq_ptw(env, old_des, new_des, &s1, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + if (old_des !=3D descriptor) { + goto restart_atomic_update; + } } =20 ap =3D extract32(attrs, 6, 2); @@ -1335,8 +1407,43 @@ static bool get_phys_addr_lpae(CPUARMState *env, uin= t64_t address, } =20 if (!(result->f.prot & (1 << access_type))) { - fi->type =3D ARMFault_Permission; - goto do_fault; + uint64_t new_des, old_des; + + /* Writes may set dirty if DBM attribute is set. */ + if (!param.hd + || access_type !=3D MMU_DATA_STORE + || !extract64(attrs, 51, 1) /* DBM */ + || !s1.rw) { + fi->type =3D ARMFault_Permission; + goto do_fault; + } + + old_des =3D descriptor; + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { + new_des =3D descriptor | (1ull << 7); /* S2AP[1] */ + } else { + new_des =3D descriptor & ~(1ull << 7); /* AP[2] */ + } + + /* + * If the descriptor didn't change, then attributes weren't the + * reason for the permission fault, so deliver it. + */ + if (old_des =3D=3D new_des) { + fi->type =3D ARMFault_Permission; + goto do_fault; + } + + descriptor =3D arm_casq_ptw(env, old_des, new_des, &s1, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + if (old_des !=3D descriptor) { + goto restart_atomic_update; + } + + /* Success: the page is now writable. */ + result->f.prot |=3D 1 << MMU_DATA_STORE; } =20 if (ns) { --=20 2.34.1