From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661175002; cv=none; d=zohomail.com; s=zohoarc; b=jUaosy7LrQNhKXNxGWepW1Lg1s+vA9oNy8yc9Q4GM5Rg5OB8PtMP+sy4QdyD6yfLhf4P0b+XQgIWKrBLoDFkchJ1pAdkjA9be7TK1qtFKDRh/XT+eUlrBosEH64Z8N8zHgBMBR0dvn1KPy1wYAxWbgkKsZMHwK/Tqo9xgihCPXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661175002; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fYJRGJbHqfyzGRsSKt0/Tu4Z570kNymq2RC3ejv5XA8=; b=Cdx6zLTTSl75iaYAJW4Og07CwCpJOFVwfgdlDYf2fSHYAhOm2aLwaEBvLTQiKmkl272+8fgX1qkcfoYKD0TTw7fTPRxplb7o7m2PcKr7+XZlfJqRu5Ma7EqAZICpVuEHoBfjwFarM9IxNU9A8kfEuVRJ4M2nw3N0t42Iy8ohLqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661175002971953.7679017998887; Mon, 22 Aug 2022 06:30:02 -0700 (PDT) Received: from localhost ([::1]:38802 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7VA-0006l4-Qy for importer@patchew.org; Mon, 22 Aug 2022 09:30:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PS-0005s8-4i for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:06 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41717) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PQ-0001di-0k for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:05 -0400 Received: by mail-wr1-x42a.google.com with SMTP id h24so13201125wrb.8 for ; Mon, 22 Aug 2022 06:24:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=fYJRGJbHqfyzGRsSKt0/Tu4Z570kNymq2RC3ejv5XA8=; b=MQDLFPdiGKea+u64F0TyqoyISPHhSQtA1tHINcj2Q/HOxEX5f/QIt22vzWa+YZXrwM kCdf4d1evxnE4JEp0B+vkPrIV2kMA3WMwR28F2toIOdj8dtEMOhl6rNhY4pSlEA2Isq+ H2xNh/y7pvqcTDtF30E10DfYoUx6oR/+7Yk3cwkRq9D2YC9tlGnP675GQFfq80di/zQM fJ7Ni8lhTZJ2oan6pJY6QNs3lt3oaOqle8cvARkbhFpsIEgjxIGca9QR/6PCQ/NbyY4E JltVFEGl+HtrIjYewmMHSgQPl7ZSgltJyS0cUHre4QnN/Av781Ty+omKM/5wFNx2mwpu b5zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=fYJRGJbHqfyzGRsSKt0/Tu4Z570kNymq2RC3ejv5XA8=; b=o8m0droPTTmDzc8O+U7xxyWtQzAQI3C4Dp+R8HSPHX32/1pWB5M+cqUi/dXwu3+eC9 VU0aLTVIWU0kJ83H97xFm8gZPkYE/JeQLrPkAtubchwHuhOXwQRlkaQT4IdmFfuDGiAc 8l4RfhWyv5U444TlUd/1nBeU6u7CH7e0GrkaW4tvsHXI13gtWumVy2VFrYasi7e3wiJS PAriAsTbcqlnmZpJaHWtzrrVNorGNSQreqXtzIjzOxrQ2LLi3zsPSTRwfa6faO445v9O LsSwM4/4GnKMiCBc3FXCwYCSszXkDulvexq73QHAoJDdPRtXj84l8DGLRMc3MSOi/VJ7 s4/g== X-Gm-Message-State: ACgBeo0Na4wT/68ZTbRHbzMwg1YqgUv9kFHC/TJHiDY5mM0WoeibSEX3 ki2FLUOut0yMIW8cerrr5ShDYLdiCYTRnA== X-Google-Smtp-Source: AA6agR7Mm3R780kpiDrq1nGQY2A0RcuAQxS8PemB/ZF+ILQoW3HQ3jMo12cNj3x3B5kXZR29UUgizw== X-Received: by 2002:adf:fb4c:0:b0:225:2033:b745 with SMTP id c12-20020adffb4c000000b002252033b745mr10272553wrs.447.1661174641624; Mon, 22 Aug 2022 06:24:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 01/10] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows Date: Mon, 22 Aug 2022 14:23:49 +0100 Message-Id: <20220822132358.3524971-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661175004446100001 Content-Type: text/plain; charset="utf-8" When the cycle counter overflows, we are intended to set bit 31 in PMOVSR to indicate this. However a missing ULL suffix means that we end up setting all of bits 63-31. Fix the bug. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d7bc467a2a5..87c89748954 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1186,7 +1186,7 @@ static void pmccntr_op_start(CPUARMState *env) uint64_t overflow_mask =3D env->cp15.c9_pmcr & PMCRLC ? \ 1ull << 63 : 1ull << 31; if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { - env->cp15.c9_pmovsr |=3D (1 << 31); + env->cp15.c9_pmovsr |=3D (1ULL << 31); pmu_update_irq(env); } =20 --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661178480; cv=none; d=zohomail.com; s=zohoarc; b=AdeeJi2S00h6RugeEWUx9RFkmFfTZZnen0SN749fhGL5SQ2EA291PgTPSuYaAV20SlWNfAINawYcN30U0Dzhk7rCa5j2Do5eUW1WvRZxOcB+cnkP1DFqwl8B+HtkV5Lxwdnunv+JI++7mG4//inJiyQarp8koXvzXquGjcl/2PM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661178480; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6876aucf7V//qP9FMCQSiTLY5Lo8nlXr95EXwywYwmM=; b=if8XNpTV7foUkxYcC+hX7q5+dZs2FMJHvY/R5WKB4pxAACD2Nh3+UyX7j1GqgI5wb2p0Wr8oGqVjjWakHZzIz0o43i5DazuYnn9pYucrqG8pC+t7q55j6e46VDrbq44LPcWdyyeNKQ0byc4rvTAg574rCwzryhWkdC0l0q2rXVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661178480723964.4801919342659; Mon, 22 Aug 2022 07:28:00 -0700 (PDT) Received: from localhost ([::1]:55348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ8PF-00025K-Ss for importer@patchew.org; Mon, 22 Aug 2022 10:27:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PS-0005s7-4Q for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:06 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:37851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PQ-0001e1-GY for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:05 -0400 Received: by mail-wr1-x42c.google.com with SMTP id n7so13207099wrv.4 for ; Mon, 22 Aug 2022 06:24:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=6876aucf7V//qP9FMCQSiTLY5Lo8nlXr95EXwywYwmM=; b=hmp1kUo1DEBShuQMVFNeOqYPCUGGpHyJ4O5vqoau1rHR1XqfL3Lo1cZbkhFmPP4Ief w9mWytI8QPceKENwe6qRHLok5zw1QRvA3iDR1Tw1NnpGtN6qm43EdLPmQ7ZXQdu3T8ez 95t5XZ72Os4DuGPqpv07SJFtmiIWH/SacE6pKY71pfY3SwR5TyWyaUCLmBPTgAf+I8bg T7sSY5mSMJZsqddTxTTQLSp3AT0Jq0tyEgvM/VbAV175lLco9jHczsvU65VBn7IwelYf 7dOeo4Nq8sNa0dWmOfdgTlJ+MCTlVNAxd1FuEStFQ9GwuhWmZVvjspA+6CipL7WMYwTf 24SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=6876aucf7V//qP9FMCQSiTLY5Lo8nlXr95EXwywYwmM=; b=dI8Mk9oMCeEs6mEPOPhtNhiBL4TgrvgLMyajkEi2uofxd/rT+rfaiKddKtyjLWTZoz ElOmmEgGAGyaxyj+Qoc0wivKjYuHn4Ocp0iPN93kBR6sIhYzF2bl8ywCk/z3YQoBjmQX /YefiV41jXN/JrK3UHhe2gk5aLaDF3Lo3TyTE830GL9GK9Q466Jfsumee/ZccIx7SWal +EBnwPzknlbdmG+ogSz2q2UFhRZo12HyeJxN6ZL6IAq1RkE0RH0XWVK0qCQWqvIVNpQZ I3LdMcTS33uDvfvcZ/hePZJB0Ky+jJv/PHGps9QZZjDYFHxH1tvyiJLXqEE1LP9xe68l HVzg== X-Gm-Message-State: ACgBeo2PGuG6GpYQ6fiNB0E6BQD9qXo202YkAoROsRDwaCp6Vep/WFxF CvjB9+VRbMs3FT9vhomtefzMhQ== X-Google-Smtp-Source: AA6agR4yFQbzq9Yobh06cW9LEigRWphpYIdXxoaOBhHVKytZYnlSmW7t84vcnRAc2DnPjfPs0lxQtw== X-Received: by 2002:a5d:4ad2:0:b0:225:285e:3ec1 with SMTP id y18-20020a5d4ad2000000b00225285e3ec1mr10865744wrs.24.1661174642608; Mon, 22 Aug 2022 06:24:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 02/10] target/arm: Correct value returned by pmu_counter_mask() Date: Mon, 22 Aug 2022 14:23:50 +0100 Message-Id: <20220822132358.3524971-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661178482111100001 Content-Type: text/plain; charset="utf-8" pmu_counter_mask() accidentally returns a value with bits [63:32] set, because the expression it returns is evaluated as a signed value that gets sign-extended to 64 bits. Force the whole expression to be evaluated with 64-bit arithmetic with ULL suffixes. The main effect of this bug was that a guest could write to the bits in the high half of registers like PMCNTENSET_EL0 that are supposed to be RES0. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b8fefdff675..83526166de0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1296,7 +1296,7 @@ static inline uint32_t pmu_num_counters(CPUARMState *= env) /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ static inline uint64_t pmu_counter_mask(CPUARMState *env) { - return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); + return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); } =20 #ifdef TARGET_AARCH64 --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661174829; cv=none; d=zohomail.com; s=zohoarc; b=exOpXcPh9TcllWjVowHkrqkapMrzUTweCxSjgs2ZNRnsG8ycRQ9EvuQ5OlNv7dqBRRIQ/thHroyydIym5qQ6m+3zrcgClm8Eqh636J/g0gQB+2ux5dqjbNzA9Q8l3+tJ9+QisWCsmlOEQ+5GXsOlNdI8vwLRNOp30jJ1u6O9sMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661174829; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z3HMTNdAubSdARHZ1TYHyaaRh8yZaKl7eKMF8WGzqZY=; b=ADIGUn7+EVSAMTS8+WEhORD+AaNS3lBPmGiXMnC0sdVv9IAq0YJbcPffmCnfQ0aJ8S/y9EER3EeCwDAs18FdwJjdUxbHwb5CYWwgMmnH7C3n83/PD7yuakllxWxn9tZARCu0p6BojPszg9xaAgM5fOTgo5kSlz1J1Y0p1/mCUPE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661174829441979.0731526552835; Mon, 22 Aug 2022 06:27:09 -0700 (PDT) Received: from localhost ([::1]:40708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7SO-0001gz-BL for importer@patchew.org; Mon, 22 Aug 2022 09:27:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PW-00063u-9o for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:10 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:40813) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PQ-0001dP-Ie for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:09 -0400 Received: by mail-wr1-x429.google.com with SMTP id h5so12400142wru.7 for ; Mon, 22 Aug 2022 06:24:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=z3HMTNdAubSdARHZ1TYHyaaRh8yZaKl7eKMF8WGzqZY=; b=MQ9ppO9Ms9TeebGs/EekuZ2lsw2d6OfTduf681AxJpve90Ynzgl4CBdNnrZKe042kH 49aJehOGKUK6/23dbUFkV7ziChCrFISIVCsiOsw4Bcwb889DYGSFl5WmyeDO2ZC6D6Cy yJkPNTFLjn2J2FYgfKhPs/P7zOczgHT9lx9HFqp/cZUjnqIdBovP7zRKo4iJEajH2pp8 TP7lNbuZsAIOQzCQmhkSLtza/bOD+W2pFHBlX67DKicbd/fXla0Ltk1XAwGmUTj7MUZQ ItGWV2zxgyeu8hyqfabbaw2AaiDv2Saew8NPHiX2KZPokU8WAmFcdT0qCT7qM0ZfszoZ DwkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=z3HMTNdAubSdARHZ1TYHyaaRh8yZaKl7eKMF8WGzqZY=; b=ta4GZ/xtOLjKcc/vDqw1DhSi5uHveS9wEiPn09N3kEnJiGo1kdzwDxjgH89/4Vprti i+lYHt+HR/2oRR5Nbex5t+iGJd7XMwV58IbHHk8y/GIOy3lwmAh03ikZSXvrWwWptohI JNWwb9Zl9e+BVkml9Hpg1gsaDcGLjDC4/TDbPI+4jwFt/zhIsuS8CwDs72FAwPwOCaYb oa2TjW1c3KUaAaIZcc8bK8IY6tLSGs6zqevbKD6GSax7JafzSPNKeGkkmZDPrBO3yoin M74LtAl8eWR2dXSbukElIKGEUznN9pAebv42aK/SjFFmxEEV20leLXyXzOwh+P9bQl4k Csbg== X-Gm-Message-State: ACgBeo2YAUQgIfPzuHNchgioBYelYbvaUZTwr5/5RS91bQkaT8OcDnqN j5BCJvB+2s4yRIogE93ufHAsUUnrRWzYtA== X-Google-Smtp-Source: AA6agR5zqhqBYA3nevWMR4REEuNpv9LFfYWBxZKnpqxMdMaWoEF7N7wIzbX6tHtTaucDvJY9Ehp5SQ== X-Received: by 2002:adf:d4c6:0:b0:225:2eeb:fe8e with SMTP id w6-20020adfd4c6000000b002252eebfe8emr10544266wrk.429.1661174643880; Mon, 22 Aug 2022 06:24:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 03/10] target/arm: Don't mishandle count when enabling or disabling PMU counters Date: Mon, 22 Aug 2022 14:23:51 +0100 Message-Id: <20220822132358.3524971-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661174830830100001 Content-Type: text/plain; charset="utf-8" The PMU cycle and event counter infrastructure design requires that operations on the PMU register fields are wrapped in pmu_op_start() and pmu_op_finish() calls (or their more specific pmmcntr and pmevcntr equivalents). This includes any changes to registers which affect whether the counter should be enabled or disabled, but we forgot to do this. The effect of this bug is that in sequences like: * disable the cycle counter (PMCCNTR) using the PMCNTEN register * write a value such as 0xfffff000 to the PMCCNTR * restart the counter by writing to PMCNTEN the value written to the cycle counter is corrupted, and it starts counting from the wrong place. (Essentially, we fail to record that the QEMU_CLOCK_VIRTUAL timestamp when the counter should be considered to have started counting is the point when PMCNTEN is written to enable the counter.) Add the necessary bracketing calls, so that updates to the various registers which affect whether the PMU is counting are handled correctly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: fixed comment typo --- target/arm/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 87c89748954..59e1280a9cd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1079,6 +1079,14 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState= *env, return pmreg_access(env, ri, isread); } =20 +/* + * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at. + * We use these to decide whether we need to wrap a write to MDCR_EL2 + * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. + */ +#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN) +#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME) + /* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing * the current EL, security state, and register configuration. */ @@ -1432,15 +1440,19 @@ static uint64_t pmccfiltr_read_a32(CPUARMState *env= , const ARMCPRegInfo *ri) static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + pmu_op_start(env); value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten |=3D value; + pmu_op_finish(env); } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + pmu_op_start(env); value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten &=3D ~value; + pmu_op_finish(env); } =20 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4681,7 +4693,39 @@ static void sctlr_write(CPUARMState *env, const ARMC= PRegInfo *ri, static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + /* + * Some MDCR_EL3 bits affect whether PMU counters are running: + * if we are trying to change any of those then we must + * bracket this update with PMU start/finish calls. + */ + bool pmu_op =3D (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BIT= S; + + if (pmu_op) { + pmu_op_start(env); + } env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; + if (pmu_op) { + pmu_op_finish(env); + } +} + +static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Some MDCR_EL2 bits affect whether PMU counters are running: + * if we are trying to change any of those then we must + * bracket this update with PMU start/finish calls. + */ + bool pmu_op =3D (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BIT= S; + + if (pmu_op) { + pmu_op_start(env); + } + env->cp15.mdcr_el2 =3D value; + if (pmu_op) { + pmu_op_finish(env); + } } =20 static const ARMCPRegInfo v8_cp_reginfo[] =3D { @@ -7669,6 +7713,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo mdcr_el2 =3D { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .writefn =3D mdcr_el2_write, .access =3D PL2_RW, .resetvalue =3D pmu_num_counters(env), .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }; --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661175254; cv=none; d=zohomail.com; s=zohoarc; b=dH3OWpa9qc5A0Xuj05hOUwQHbtqHKogcShKr79TDpRFyeifFZ7HKWnD0eQVaLBfl6cQhZolYdaSrpP1DkwchX/yxBKGd7jD/lJGrykDh9D4hlmJmdl0ZLx0WRoGnebTxOzaBPQugCSXZfqCYHs8p1ATn6RLYNVrrNOV6rMnGyzU= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=aFjhTAogUKZHPlT633nMjBBSLixPxUKktQV7BA0xzwY=; b=SZEbkUyO8ke8oO6QGqEB8mbtGeHhXYHlX1SlPwJZYpKl20hS48Wd7D/+bnMdP/wyq/ ro52b0f0Nz+G/UdiUYK/29aM6ZDzcCOeyKSJhQ4hKo4bvSxI/rbJvxAGGJWl3MFA7qvA +8YJWUW5mSGRUyZom9VcUsBr+mvz9IWKIB+Cq274ysjRQIbQE+N7jPxLIUHU+SFPI23y pwm7n3x8XR4/LJo3ikPlEZ/tkZelw3OQz2q2g4FXdXzgTaMUu59d8wiSBcJXMMOgwXW6 k6mcOdyFmWXb+Dy8rw0ng8uLEE2l3S5NMO0DnBYaVTepAKxaD1oiPpyRY+Hpu1ZY/f1r FxAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=aFjhTAogUKZHPlT633nMjBBSLixPxUKktQV7BA0xzwY=; b=CvzOXq01LTEYpiFCx68r18AM8nkM0MTlrIhW8ASSqyeqNQVOEOYutbNWnnvev1rnBg 7c6vgYml+fkbvVr3Kl1JD5ysEbcdXvVpKzI65epy1+7Hwivr8BqULDGU6b0s0EgHyhiT nbqEOktwD6f/mdmPMAgHpJ/5K0dXERBmA57/Q4Em9QfBNuzMk68jDhHNHfkq0L7x/HTG o4ubV1QoLqXRcnmcL57Awek+mkhqXtagS6KOy7dJl08kCJ9ck8yWsM/vPoDrnX+EXKHj bGzigRYtMVZdBxac1d1CEmBu8m1P6dh5hKErHeqe+kuvqrUMIfXqxEI3O53NMFEXm8Vd jneg== X-Gm-Message-State: ACgBeo360N2R91v5fOUuoY+p/dPmdBZMLL9Uz3lljbvtCq1v21X1PcWn fT4hChFHiAYw5Oclg02w8ezKFg== X-Google-Smtp-Source: AA6agR51n+pWd9Jtp8SMbmp5JywGVBTcTwQvX+ilJsde/TL8pR6THFT1ZjPto/67ufRLAnI2GFpBqA== X-Received: by 2002:a5d:59ad:0:b0:225:5b64:8c6a with SMTP id p13-20020a5d59ad000000b002255b648c6amr2091290wrr.558.1661174644731; Mon, 22 Aug 2022 06:24:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 04/10] target/arm: Ignore PMCR.D when PMCR.LC is set Date: Mon, 22 Aug 2022 14:23:52 +0100 Message-Id: <20220822132358.3524971-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661175255959100001 Content-Type: text/plain; charset="utf-8" The architecture requires that if PMCR.LC is set (for a 64-bit cycle counter) then PMCR.D (which enables the clock divider so the counter ticks every 64 cycles rather than every cycle) should be ignored. We were always honouring PMCR.D; fix the bug so we correctly ignore it in this situation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 59e1280a9cd..f2bf1c52eb2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1172,6 +1172,17 @@ static void pmu_update_irq(CPUARMState *env) (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } =20 +static bool pmccntr_clockdiv_enabled(CPUARMState *env) +{ + /* + * Return true if the clock divider is enabled and the cycle counter + * is supposed to tick only once every 64 clock cycles. This is + * controlled by PMCR.D, but if PMCR.LC is set to enable the long + * (64-bit) cycle counter PMCR.D has no effect. + */ + return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) =3D=3D PMCRD; +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1184,8 +1195,7 @@ static void pmccntr_op_start(CPUARMState *env) =20 if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles =3D cycles; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ + if (pmccntr_clockdiv_enabled(env)) { eff_cycles /=3D 64; } =20 @@ -1228,8 +1238,7 @@ static void pmccntr_op_finish(CPUARMState *env) #endif =20 uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ + if (pmccntr_clockdiv_enabled(env)) { prev_cycles /=3D 64; } env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661174872; cv=none; d=zohomail.com; s=zohoarc; b=bZFXA2RC0xsJOZxl9RRAgIDqyEnqqK+lEs+mRcC2jGRYon7bwNoWU8nUtuNo1Sx/baJgEEi1k0WnbNb9jhJmfqPx2+WjzmXA7aX61bp4dSZjUDZO7lfu2oAH2BLGtGlov/us2j1K/asISILkBqCckNM/t54GdTXrHD80HI6rehM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661174872; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6yc2QQJRiauV/rnVG5qIFbv8E5zW00rmH8bNkLiSwRQ=; b=hC2/2/2taF0L2H5zer+Doo8Kpn87qmcpuB0XBEoG7nBMVx35fAYGLZJpvTgI+u+mD8JKC61BtdB7mr2Kx705c4tSxb7KK1JZjENCTPxgGknFNsthXLImckupJLA0vIyp2Zq146Ygait1p9m8PsMBQkDyrxl85Ay1ZKPZ5gG2MZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661174872732589.579713328604; Mon, 22 Aug 2022 06:27:52 -0700 (PDT) Received: from localhost ([::1]:38928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7T5-00039N-N1 for importer@patchew.org; Mon, 22 Aug 2022 09:27:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PV-000614-HP for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:09 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:36385) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PT-0001f3-Rc for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:09 -0400 Received: by mail-wr1-x431.google.com with SMTP id d16so7913202wrr.3 for ; Mon, 22 Aug 2022 06:24:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=6yc2QQJRiauV/rnVG5qIFbv8E5zW00rmH8bNkLiSwRQ=; b=MxIIKoA/j+fJRx+GtFl6JLVbi7+dfJsozau6SY54wFuUAT7u5HeCEVv4A1TFwPtJ5R p+aLiodJyPvQxzOgtfK24idpeopiJVlUHlerP5M0tDkHEaXzXAYXHG/oRqKTk8wWvEhO 7RU6XCij5i6OFlg0WDxu6sdEvdau3OpdPozzsK1OnfgNj5az8V05shoKom5d70/At2f7 hX7l1+CVE1kKvj/QXSv3E7WiCVQcWiBrPbchTEagnNsIFfWBw+7+cYxq8M4Eqz+7NCyl B3KxviNsmC+ljhSFpIn7clmXVvhHeZTJVmx/wI4yxh/kBfIqcaxK8yblJYBCcrOcnCl7 fHdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=6yc2QQJRiauV/rnVG5qIFbv8E5zW00rmH8bNkLiSwRQ=; b=Is1n3eAS3q5T+WqT0aitbJ5uTxquqoIj4l2QSJeV1NDkTtfnmiEeaWaPVTJKyJPYaP luJtiD8cNkW1maONGAvB3jvl0v7jqpEZlHYZVDnxaJUIsKRUYGf2ezy0NGYByJDnlZm+ SooIihSgStRZLo9xv59ObyIhdkziDyMEP8scSh1IDXjdajJgG8On3TNK05Pa+OVDsFd2 G39hYzfSm6OD2MGqiM6QQ68dbRO/aiBAH3K2bbE4YpY/4xKqHsNd8JNPcumWXash5vW3 kbQVxBg7a/Q76m1sMtF/TkIhcj8doM4bs1BUE1U9gUmPS0ebSrxj0wWwntb5sjewb0t1 VGQg== X-Gm-Message-State: ACgBeo2vUx4bgCO8BWiyNSHLn6VXyZv78SF4Qs9DJnXX4+o/JS6zdPXY vFDGFMxeQGCkRpCltYk1VHVp6Q== X-Google-Smtp-Source: AA6agR47VtGv1dSNacXxsyOw46Sr/giwX87+RC5YMwtSi/11pNwWfzw4UK8l5ONtM4NeALyZ0fJSNg== X-Received: by 2002:adf:fe04:0:b0:225:1c8e:9027 with SMTP id n4-20020adffe04000000b002251c8e9027mr10608630wrr.155.1661174645742; Mon, 22 Aug 2022 06:24:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 05/10] target/arm: Honour MDCR_EL2.HPMD in Secure EL2 Date: Mon, 22 Aug 2022 14:23:53 +0100 Message-Id: <20220822132358.3524971-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661174874782100001 Content-Type: text/plain; charset="utf-8" The logic in pmu_counter_enabled() for handling the 'prohibit event counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way that assumes that EL2 is never Secure. This used to be true, but the architecture now permits Secure EL2, and QEMU can emulate this. Refactor the prohibit logic so that we effectively OR together the various prohibit bits when they apply, rather than trying to construct an if-else ladder where any particular state of the CPU ends up in exactly one branch of the ladder. This fixes the Secure EL2 case and also is a better structure for adding the PMUv8.5 bits MDCR_EL2.HCCD and MDCR_EL3.SCCD. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I opted not to use bitwise |=3D for boolean operations. --- target/arm/helper.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f2bf1c52eb2..7d4127a1573 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1094,7 +1094,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uin= t8_t counter) { uint64_t filter; bool e, p, u, nsk, nsu, nsh, m; - bool enabled, prohibited, filtered; + bool enabled, prohibited =3D false, filtered; bool secure =3D arm_is_secure(env); int el =3D arm_current_el(env); uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); @@ -1112,15 +1112,12 @@ static bool pmu_counter_enabled(CPUARMState *env, u= int8_t counter) } enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); =20 - if (!secure) { - if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { - prohibited =3D mdcr_el2 & MDCR_HPMD; - } else { - prohibited =3D false; - } - } else { - prohibited =3D arm_feature(env, ARM_FEATURE_EL3) && - !(env->cp15.mdcr_el3 & MDCR_SPME); + /* Is event counting prohibited? */ + if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { + prohibited =3D mdcr_el2 & MDCR_HPMD; + } + if (secure) { + prohibited =3D prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); } =20 if (prohibited && counter =3D=3D 31) { --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661175007; cv=none; d=zohomail.com; s=zohoarc; b=cikLg4E9uGf0dtxFE2I9JpKt5JNgQQMnHEmUgkOODdqX6kc6X8Yf4wsRy6JO0/cwaVZp2hPBGdSplUgQeafNOzsORgX62eDsvTHxAyXtJD3p0RyfjukT5GLp95AE8XnKEj2L73hVpZCpS3EgBOIC4DovXhMLmnqL2NArgbdyk7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661175007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gAJToUGMZxgV0d4Q4X3oKY4UbjuKkCvUr3anhNbi7Gw=; b=A4VdajuXFjIOScwKfQT3XAJu13RrUx/fuuXkegSwYl24zoFY0Ztk7dEntsvIQRZu0kf/o7tehQi2ySoETRN9xlyg6AAYla765zN0sQCSTtgtuv8pMl9vlZ3bCbK/8AE3PDy3BHfEgJNUVqZ39dBkaaWjOCt6cjjtL7GiLgKGL7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661175007957297.69881885744894; Mon, 22 Aug 2022 06:30:07 -0700 (PDT) Received: from localhost ([::1]:48464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7VG-00070g-RD for importer@patchew.org; Mon, 22 Aug 2022 09:30:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PW-00065D-O1 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:10 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38731) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PU-0001fL-Vi for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:10 -0400 Received: by mail-wr1-x429.google.com with SMTP id b5so8926148wrr.5 for ; Mon, 22 Aug 2022 06:24:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gAJToUGMZxgV0d4Q4X3oKY4UbjuKkCvUr3anhNbi7Gw=; b=mp+4Cvc2B2WVUm2VMs2TIKnUWypi5GuYqJehgRpGcGyztzYwY2ExisP+c7HQZnloeL 9DXonw24UVUI/opfwc3UrMKXistkpbxPpA3p2mvDmJyVM/Tzrx5bt4WpD+GJCp5IPyRg 00h7GN7aDZfzJSPsSFxtANOEExTX2D5wRz2Jhmhlgh/ncIARqVQOaTt2g+7aJGx4qsei oRVW9Pwu6EqFZEot/omyUqfo4+y8GqAMIS8a397RMt/NxnogXWs7hBdzSUnw0wbJsGpb 8qTBr351CJU44LRsLYaanf+VcErpWsxaTEAmj/jS+cxFDN7QSX/6IrH9hYdsAAYH/Vl+ ERYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gAJToUGMZxgV0d4Q4X3oKY4UbjuKkCvUr3anhNbi7Gw=; b=KnGx6FvWb142ofxNeByhcLXleniY/j2uKVKbf9spcdldGQzStdJSNxI5O1yFgXA8Tz 3qDrdlnqeX2FelNtV2tKOMN4C/IlZulJA/g5oAlOeeXL/SoHpwAk0mNt4o00htGYIsAo DVXq0QxRPvivQW2LDmIjrwYtqSYVPfmhJAO046Vox8MTkMSdkd+ox7jlJhRxNbD2QET6 5TeS4SgzM+vAo/KEE7qjaO4FkPaTbVDo5++VHB2dABayNv84tZ/BNwmW9LG37gXJ89Lb VjaPddjVlKHNcCRFe3DIWt8GRrPeO4goglyd/r0JA9iY8m3TodmgeXoHcfef58Pgc5Jn xbog== X-Gm-Message-State: ACgBeo3KZI8AwkfddhzfO7/wCGdHWYs/BJ5NS3p66t/8T28156GChBWA DH5k1bO4UouDmNNSUJyzbLgZj4SUmaskbA== X-Google-Smtp-Source: AA6agR7K2geqNcCLKUGVOIP4MmWZYqM5CmvVNNgE1A7yfOFEJduAaWgLG11RcPLaxyL/pDLH+QIkvQ== X-Received: by 2002:adf:de08:0:b0:225:426d:480 with SMTP id b8-20020adfde08000000b00225426d0480mr6492941wrm.636.1661174646739; Mon, 22 Aug 2022 06:24:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 06/10] target/arm: Detect overflow when calculating next PMU interrupt Date: Mon, 22 Aug 2022 14:23:54 +0100 Message-Id: <20220822132358.3524971-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661175008424100001 Content-Type: text/plain; charset="utf-8" In pmccntr_op_finish() and pmevcntr_op_finish() we calculate the next point at which we will get an overflow and need to fire the PMU interrupt or set the overflow flag. We do this by calculating the number of nanoseconds to the overflow event and then adding it to qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL). However, we don't check whether that signed addition overflows, which can happen if the next PMU interrupt would happen massively far in the future (250 years or more). Since QEMU assumes that "when the QEMU_CLOCK_VIRTUAL rolls over" is "never", the sensible behaviour in this situation is simply to not try to set the timer if it would be beyond that point. Detect the overflow, and skip setting the timer in that case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: fixed bogus indentation --- target/arm/helper.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d4127a1573..94307a6c417 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1227,10 +1227,13 @@ static void pmccntr_op_finish(CPUARMState *env) int64_t overflow_in =3D cycles_ns_per(remaining_cycles); =20 if (overflow_in > 0) { - int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - overflow_in; - ARMCPU *cpu =3D env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + int64_t overflow_at; + + if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + overflow_in, &overflow_at)) { + ARMCPU *cpu =3D env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } } #endif =20 @@ -1275,10 +1278,13 @@ static void pmevcntr_op_finish(CPUARMState *env, ui= nt8_t counter) int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); =20 if (overflow_in > 0) { - int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - overflow_in; - ARMCPU *cpu =3D env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + int64_t overflow_at; + + if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + overflow_in, &overflow_at)) { + ARMCPU *cpu =3D env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } } #endif =20 --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661178550; cv=none; d=zohomail.com; s=zohoarc; b=IW0BRyQ4oer0fPyOAmW+HuUYQNkV77sNA0+twBBnGY+U1R23AKTZ7a/hhipGRktdvh9xMt4To9pnj1+ch+jLUmDOR/EOya0heZT97VclYdl0UguV6Y3uifGXrxupAtgPcPeKyuuIfWf6LdanHSsptdkb2n1StA5dCMS3Y65vaOo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661178550; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2fxzttXpNNgLe45+/J1iHDaTona/8trrZi4UUTNeBEw=; b=Xw8h8RAuP31UBJBIoJMVTiOFWROozn294LDhtY3gM2U3QVw6KdHmmFxwGoq4LvNLIrSb+CrOtXiv+1ZNLPWSzxxv5BtglCKknXM874G55C9i+LLi3UY8Fyp7oenbvN0IjJVGwxO8xwqDDU46O15FdpTto457tOmgvtHZIIdxoSA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661178550487251.41020806120605; Mon, 22 Aug 2022 07:29:10 -0700 (PDT) Received: from localhost ([::1]:42716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ8QP-0003QV-H7 for importer@patchew.org; Mon, 22 Aug 2022 10:29:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PX-00068b-Ar for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:11 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:44864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PV-0001fX-DY for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:11 -0400 Received: by mail-wm1-x331.google.com with SMTP id k18-20020a05600c0b5200b003a5dab49d0bso6002857wmr.3 for ; Mon, 22 Aug 2022 06:24:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=2fxzttXpNNgLe45+/J1iHDaTona/8trrZi4UUTNeBEw=; b=ymXq/t4+CxC7iLNQjPnrRutYPX9C0BXYGDSodwm/nS95FjrkTWPxWipFUl8V4L8a/B RO3za+0yxfvjqRGur21FDoXSw3Slz7uqjLRtY1MoNVftRy248XzVeTVGY0spLtSRxc0m Gq6n4ZaHV0ybD3/GOxejejJGWKjocgSvkjx+Zrj2Hm+U/tOrHqGKL66XMHuh118jppSB J25okUlIVC5ttLmsMsHXKcSmpg+On4asVQ8lrdYiHmauxobViiHHojIZtGPQwk3EhQTx s2l3WV6faKQ+S4UCtaKJKzHXIvvjEM4TIZlTJaQhYzGqde66TCa5HYNavXJLdhfXVmC4 na0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=2fxzttXpNNgLe45+/J1iHDaTona/8trrZi4UUTNeBEw=; b=1NlkpkdOcTpmxgZCLcAZe2YlB6m0RkoB9nyXqc4aaofGShKiEUK45l8ZPi02AwnYyz gYozcK/XcEd2LvTBUGX8Q4AYJAIFme2AxJBRIxmiUOKez6uxsmjPtljqIISC2ogOYeCV LcAAfPVRYBBrwtwrg1ZdaWVwXmxmGlBJawlOOmibqhZcHu0MgTyL0QPkU9OKH3iYPRQl 7HZBlvTauakQVvfNNQ4IEQUM155BFvfM3XGGGJjo1DFsOV14nIWLDxx8Lu8y3t3LHLWH WMoNcVOwipfGxgW0Xjb5G+tdsClWUPIPHqbcYA/+zS4Y2RcSuKeC74qWXCIoneonihM/ E4dA== X-Gm-Message-State: ACgBeo25EdcVVu4xERJiyftqwhhYQjeaZNS0/5x3VTTB874JxDBOyb37 A2Rc5fGqy8esquGkKdvPcDGPe+5p/fnGGQ== X-Google-Smtp-Source: AA6agR6JD98izczqkbVeTbsEjTXrs62dQlj1+hVgi/cKymIHygyaVra8x3nBoO4lwY1j6YBb0F0pVw== X-Received: by 2002:a05:600c:2909:b0:3a6:2ef5:772e with SMTP id i9-20020a05600c290900b003a62ef5772emr10160010wmd.16.1661174647726; Mon, 22 Aug 2022 06:24:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 07/10] target/arm: Rename pmu_8_n feature test functions Date: Mon, 22 Aug 2022 14:23:55 +0100 Message-Id: <20220822132358.3524971-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661178551783100001 Content-Type: text/plain; charset="utf-8" Our feature test functions that check the PMU version are named isar_feature_{aa32,aa64,any}_pmu_8_{1,4}. This doesn't match the current Arm ARM official feature names, which are FEAT_PMUv3p1 and FEAT_PMUv3p4. Rename these functions to _pmuv3p1 and _pmuv3p4. This commit was created with: sed -i -e 's/pmu_8_/pmuv3p/g' target/arm/*.[ch] Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 16 ++++++++-------- target/arm/helper.c | 18 +++++++++--------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5168e3d837e..122ec8a47ec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3710,14 +3710,14 @@ static inline bool isar_feature_aa32_ats1e1(const A= RMISARegisters *id) return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; } =20 -static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) +static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 -static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) +static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && @@ -4036,13 +4036,13 @@ static inline bool isar_feature_aa64_sme(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; } =20 -static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) +static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 -static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) +static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; @@ -4211,14 +4211,14 @@ static inline bool isar_feature_any_predinv(const A= RMISARegisters *id) return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); } =20 -static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) +static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) { - return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); + return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); } =20 -static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) +static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) { - return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); + return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); } =20 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) diff --git a/target/arm/helper.c b/target/arm/helper.c index 94307a6c417..5212750b378 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -879,16 +879,16 @@ static int64_t instructions_ns_per(uint64_t icount) } #endif =20 -static bool pmu_8_1_events_supported(CPUARMState *env) +static bool pmuv3p1_events_supported(CPUARMState *env) { /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); + return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); } =20 -static bool pmu_8_4_events_supported(CPUARMState *env) +static bool pmuv3p4_events_supported(CPUARMState *env) { /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); + return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); } =20 static uint64_t zero_event_get_count(CPUARMState *env) @@ -922,17 +922,17 @@ static const pm_event pm_events[] =3D { }, #endif { .number =3D 0x023, /* STALL_FRONTEND */ - .supported =3D pmu_8_1_events_supported, + .supported =3D pmuv3p1_events_supported, .get_count =3D zero_event_get_count, .ns_per_count =3D zero_event_ns_per, }, { .number =3D 0x024, /* STALL_BACKEND */ - .supported =3D pmu_8_1_events_supported, + .supported =3D pmuv3p1_events_supported, .get_count =3D zero_event_get_count, .ns_per_count =3D zero_event_ns_per, }, { .number =3D 0x03c, /* STALL */ - .supported =3D pmu_8_4_events_supported, + .supported =3D pmuv3p4_events_supported, .get_count =3D zero_event_get_count, .ns_per_count =3D zero_event_ns_per, }, @@ -6400,7 +6400,7 @@ static void define_pmu_regs(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } - if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { + if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { ARMCPRegInfo v81_pmu_regs[] =3D { { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, @@ -6413,7 +6413,7 @@ static void define_pmu_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v81_pmu_regs); } - if (cpu_isar_feature(any_pmu_8_4, cpu)) { + if (cpu_isar_feature(any_pmuv3p4, cpu)) { static const ARMCPRegInfo v84_pmmir =3D { .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661175109; cv=none; d=zohomail.com; s=zohoarc; b=VbcWr4iF0Obkh4/Uei4WQO46/q9I8rqb94nPZFKvM0AFYre6zuUlFQYW1fkS2uQ9AUdahKCwazJGIx+pv/yRx9HkZLEJaol8SLfvn2+Q3Wa9gEKz7FbkilsjbNi7pwca52OO6c8riSxIgaiQyaixRU0/KmCTI4af7g61L9QcSas= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661175109; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=rApZciN4LfzjQtxbWJQ3PAJs2Z/3UIZwNKUKuZ8hIWY=; b=yn9FlDbtUEcwW2JlMo1uLjPzsumfLANIp57s2SO1LCsUTuKEZ5/hvZG+VPmP3c4X4a qPwcW9Wcky3+m44iUKTJbEG+chRiqw2pLK5OzzV4sRY+MXGWzdLkuv2gPeceeWoIeP5n 0mDgUgRHuiZfLVlncRZiOCMggdTzLmMvF9efHrS/ZTSrUGnVjKI30ptVX9HWecxhJJ5p G23cHIf5vIXJx/XA/k/OMDNlyHNXuY3c8qgursi24b4MD6GqZQjxI13PJdbWri3TgHlX jJedmp7W3bCFETeG0qS2N4QL4Rvf0mYDqaVK+eqDievUj97Tye0Lu259vUvvkJwbWYLL O3bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=rApZciN4LfzjQtxbWJQ3PAJs2Z/3UIZwNKUKuZ8hIWY=; b=mhOPXr1M7DrMijFN//aN+LfH23WEL+vG/vTgghjfZPDHRpPCq0opZ7Sc6Qg5gTytYn onqagb//Dfs18B3l/jpfhSuaXTseiM6PncMV85jyfyIV+gDOjCmDbk2wNPjyVwrxZEPs Ua0ovgpTQOGWmdMSZhhbJbtKNvAE7XSX5V2nCNHoB/LeCwXeHrKvrkdAacCKMhQQJ3QM 8M0Ok+PPUmiHADcWyWKppeu1MISTzVRVODmHWvZJZwNjk27BX9dovY3fkpUhDvfLz1qr xIxV0RW/8v24M3JIfm1+xqeDedNHNvbKDS/SFjZnAB5rqFZE7r0qjYWK4XRrJbrR4NWM xapA== X-Gm-Message-State: ACgBeo0yI/ocxWljegRN2aJLbkAExNcDOCQYsoBcVt1IUPP1Ga8Rfl0n ILdCV2pb59aWAHa5cn65VcHXpzwy6UDwNA== X-Google-Smtp-Source: AA6agR4wO3CbDPjogRuiPToymeFLszMpKe6NMv+aWPMxVmTY9J5+yNcSYsXWEgUVMW1e9O/faPihFg== X-Received: by 2002:a05:600c:1551:b0:3a6:2f4d:aeca with SMTP id f17-20020a05600c155100b003a62f4daecamr10031495wmg.100.1661174648816; Mon, 22 Aug 2022 06:24:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits Date: Mon, 22 Aug 2022 14:23:56 +0100 Message-Id: <20220822132358.3524971-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661175111056100001 Content-Type: text/plain; charset="utf-8" FEAT_PMUv3p5 introduces new bits which disable the cycle counter from counting: * MDCR_EL2.HCCD disables the counter when in EL2 * MDCR_EL3.SCCD disables the counter when Secure Add the code to support these bits. (Note that there is a third documented counter-disable bit, MDCR_EL3.MCCD, which disables the counter when in EL3. This is not present until FEAT_PMUv3p7, so is out of scope for now.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: Get the MDCR_EL3 bit right; v1 implemented something more like MDCR_EL3.MCCD. --- target/arm/cpu.h | 20 ++++++++++++++++++++ target/arm/helper.c | 21 +++++++++++++++++---- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 122ec8a47ec..1f6ccc6f217 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1332,6 +1332,8 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) =20 +#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ +#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ @@ -3724,6 +3726,13 @@ static inline bool isar_feature_aa32_pmuv3p4(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 6 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; @@ -4048,6 +4057,12 @@ static inline bool isar_feature_aa64_pmuv3p4(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; @@ -4221,6 +4236,11 @@ static inline bool isar_feature_any_pmuv3p4(const AR= MISARegisters *id) return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); } =20 +static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); +} + static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) { return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); diff --git a/target/arm/helper.c b/target/arm/helper.c index 5212750b378..d22debcd57b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1084,8 +1084,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, * We use these to decide whether we need to wrap a write to MDCR_EL2 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. */ -#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN) -#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME) +#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR= _HCCD) +#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) =20 /* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing * the current EL, security state, and register configuration. @@ -1120,8 +1120,21 @@ static bool pmu_counter_enabled(CPUARMState *env, ui= nt8_t counter) prohibited =3D prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); } =20 - if (prohibited && counter =3D=3D 31) { - prohibited =3D env->cp15.c9_pmcr & PMCRDP; + if (counter =3D=3D 31) { + /* + * The cycle counter defaults to running. PMCR.DP says "disable + * the cycle counter when event counting is prohibited". + * Some MDCR bits disable the cycle counter specifically. + */ + prohibited =3D prohibited && env->cp15.c9_pmcr & PMCRDP; + if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + if (secure) { + prohibited =3D prohibited || (env->cp15.mdcr_el3 & MDCR_SC= CD); + } + if (el =3D=3D 2) { + prohibited =3D prohibited || (mdcr_el2 & MDCR_HCCD); + } + } } =20 if (counter =3D=3D 31) { --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661175436; cv=none; d=zohomail.com; s=zohoarc; b=FombffeRSEaeSvviYmD5Yr0Vbh730WAmyQNKYVelNWfT55hykSx8V0Y2V+Lxg9aCQloT5ezzcyU86RQiEPDN4Ug2J97fZaPfwW3QWznLUelEo+pP2t41obm06dtueCapwsQ1AUkNi8gdpJ7gKKogl/xPGZWX37LIAgJr6jTgb/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661175436; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vD+of0yf04XIK3wSlDEJY0alv64T6b7yHWK7FZo8BaI=; b=eEkjD9v/dlYESlMVyKrqWkeDmydUfjtE0/xBfFVABqkphwQCCi5umqUbTOghyyKqhrsdwZkalfm0ct9Pc1roqrEAsnzB38B7IsnHlkYSOanTJ7HuKIz/gArGk/6kUvesYLk0j7OijhSqnzknIc/0kHvyl8RLgFCikHelfnk1XpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661175436684296.10199438045686; Mon, 22 Aug 2022 06:37:16 -0700 (PDT) Received: from localhost ([::1]:36844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7c9-0004hU-2Z for importer@patchew.org; Mon, 22 Aug 2022 09:37:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7Pa-0006H4-DZ for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:14 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:33601) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PX-0001gY-DU for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:14 -0400 Received: by mail-wm1-x329.google.com with SMTP id m3-20020a05600c3b0300b003a5e0557150so5842956wms.0 for ; Mon, 22 Aug 2022 06:24:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vD+of0yf04XIK3wSlDEJY0alv64T6b7yHWK7FZo8BaI=; b=tfLW+4yBtFeAnedxTh1SZ1u4El1droQQ7cxOdJUdrrxFG3dEUEi4Rwxdr3PDspX5dB eK8TcdfHcLi10mYg0Sj4hJfMvTNs3jajaBzhLc7aLHNXBDcWHIaj/Fcm9aniyBMD0KIc BJI6fQMdgUerIKBuU/b+JMuUPnFu2cATjvLlVVI9tP4JGHcoTN/TK5BOnzz6k2kOtegm v4TRsMnIqzW7mTEcLuCCFhtHNm6Ppy1+i8u/EBDHTDEZZAL6/Bw2SZC++rd5MBf8aPx3 /VqAb6M4Cd+Q19EU71VAn3Pmik1Ow3rKbbSZWRbCWAstkZufaTNycG5CViRUgJ+lx2lR 8tqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vD+of0yf04XIK3wSlDEJY0alv64T6b7yHWK7FZo8BaI=; b=J9zOKqO3lxqKqA0/9Y8dfXNMzTvcMmPn3kisqkx0Z/js78yGZpSJt4n1kdKrGE0adw rmwsthRrSNcskgDWFlNN0ExLfG23RV6BFjE2GNIp2kIoMRHzYuQawbF+oQGBWQJYlQg1 s02zQL5Ksdr8bYlXRBFDN8uixIxOSyAdbf3JBEhl7bBjo6HhJgkT6jM6VXBFeY40ObYm 5X8SVmCkjVi/HhJX5z8CU6rjew/o9dYkGLYsoYvMN7e7DofZS0EZ0idj0tHRHv/5C/Dg DwgVVGhLDpag+AqncGvEbt/hw9PVDEKU7m3okmGn1meYUnr7CNWIMjDoX1SIb2/INJ5Y Tl/w== X-Gm-Message-State: ACgBeo1lS1DBYAALJy2TbKQqlnP89dFbll6tHI9FwkvvjExTS3Eev85R 3Mw3ywsvcHmu10rR6pfhQ6HtI4fJAuDhdg== X-Google-Smtp-Source: AA6agR5qGhI58DuHFcuUgX//K+XPMcPF41fNAomnXMhQjyfnvcGLLdSGrCv7VfroaYII0nO3jwK8dg== X-Received: by 2002:a05:600c:3d91:b0:3a5:4132:b6a0 with SMTP id bi17-20020a05600c3d9100b003a54132b6a0mr11515151wmb.126.1661174650005; Mon, 22 Aug 2022 06:24:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 09/10] target/arm: Support 64-bit event counters for FEAT_PMUv3p5 Date: Mon, 22 Aug 2022 14:23:57 +0100 Message-Id: <20220822132358.3524971-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661175437144100001 Content-Type: text/plain; charset="utf-8" With FEAT_PMUv3p5, the event counters are now 64 bit, rather than 32 bit. (Previously, only the cycle counter could be 64 bit, and other event counters were always 32 bits). For any given event counter, whether the overflow event is noted for overflow from bit 31 or from bit 63 is controlled by a combination of PMCR.LP, MDCR_EL2.HLP and MDCR_EL2.HPMN. Implement the 64-bit event counter handling. We choose to make our counters always 64 bits, and mask out the top 32 bits on read or write of PMXEVCNTR for CPUs which don't have FEAT_PMUv3p5. (Note that the changes to pmenvcntr_op_start() and pmenvcntr_op_finish() bring their logic closer into line with that of pmccntr_op_start() and pmccntr_op_finish(), which already had to cope with the overflow being either at 32 or 64 bits.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 +- target/arm/helper.c | 62 ++++++++++++++++++++++++++++++++++++------ 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f6ccc6f217..be79394dcc7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1332,6 +1332,7 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) =20 +#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) diff --git a/target/arm/internals.h b/target/arm/internals.h index 83526166de0..bf60cd5f845 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1256,6 +1256,7 @@ enum MVEECIState { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRLP 0x80 #define PMCRLC 0x40 #define PMCRDP 0x20 #define PMCRX 0x10 @@ -1267,7 +1268,7 @@ enum MVEECIState { * Mask of PMCR bits writable by guest (not including WO bits like C, P, * which can be written as 1 to trigger behaviour but which stay RAZ). */ -#define PMCR_WRITABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) +#define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMC= RE) =20 #define PMXEVTYPER_P 0x80000000 #define PMXEVTYPER_U 0x40000000 diff --git a/target/arm/helper.c b/target/arm/helper.c index d22debcd57b..133ca39700f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1084,7 +1084,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, * We use these to decide whether we need to wrap a write to MDCR_EL2 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. */ -#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR= _HCCD) +#define MDCR_EL2_PMU_ENABLE_BITS \ + (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) =20 /* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing @@ -1193,6 +1194,32 @@ static bool pmccntr_clockdiv_enabled(CPUARMState *en= v) return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) =3D=3D PMCRD; } =20 +static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) +{ + /* Return true if the specified event counter is configured to be 64 b= it */ + + /* This isn't intended to be used with the cycle counter */ + assert(counter < 31); + + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + return false; + } + + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* + * MDCR_EL2.HLP still applies even when EL2 is disabled in the + * current security state, so we don't use arm_mdcr_el2_eff() here. + */ + bool hlp =3D env->cp15.mdcr_el2 & MDCR_HLP; + int hpmn =3D env->cp15.mdcr_el2 & MDCR_HPMN; + + if (hpmn !=3D 0 && counter >=3D hpmn) { + return hlp; + } + } + return env->cp15.c9_pmcr & PMCRLP; +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1269,9 +1296,11 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) } =20 if (pmu_counter_enabled(env, counter)) { - uint32_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + uint64_t overflow_mask =3D pmevcntr_is_64_bit(env, counter) ? + 1ULL << 63 : 1ULL << 31; =20 - if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { + if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mas= k) { env->cp15.c9_pmovsr |=3D (1 << counter); pmu_update_irq(env); } @@ -1286,9 +1315,13 @@ static void pmevcntr_op_finish(CPUARMState *env, uin= t8_t counter) #ifndef CONFIG_USER_ONLY uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; uint16_t event_idx =3D supported_event_map[event]; - uint64_t delta =3D UINT32_MAX - - (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; - int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); + uint64_t delta =3D -(env->cp15.c14_pmevcntr[counter] + 1); + int64_t overflow_in; + + if (!pmevcntr_is_64_bit(env, counter)) { + delta =3D (uint32_t)delta; + } + overflow_in =3D pm_events[event_idx].ns_per_count(delta); =20 if (overflow_in > 0) { int64_t overflow_at; @@ -1375,6 +1408,8 @@ static void pmswinc_write(CPUARMState *env, const ARM= CPRegInfo *ri, uint64_t value) { unsigned int i; + uint64_t overflow_mask, new_pmswinc; + for (i =3D 0; i < pmu_num_counters(env); i++) { /* Increment a counter's count iff: */ if ((value & (1 << i)) && /* counter's bit is set */ @@ -1388,9 +1423,12 @@ static void pmswinc_write(CPUARMState *env, const AR= MCPRegInfo *ri, * Detect if this write causes an overflow since we can't pred= ict * PMSWINC overflows like we can for other events */ - uint32_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; =20 - if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { + overflow_mask =3D pmevcntr_is_64_bit(env, i) ? + 1ULL << 63 : 1ULL << 31; + + if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { env->cp15.c9_pmovsr |=3D (1 << i); pmu_update_irq(env); } @@ -1597,6 +1635,10 @@ static uint64_t pmxevtyper_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value, uint8_t counter) { + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ + value &=3D MAKE_64BIT_MASK(0, 32); + } if (counter < pmu_num_counters(env)) { pmevcntr_op_start(env, counter); env->cp15.c14_pmevcntr[counter] =3D value; @@ -1616,6 +1658,10 @@ static uint64_t pmevcntr_read(CPUARMState *env, cons= t ARMCPRegInfo *ri, pmevcntr_op_start(env, counter); ret =3D env->cp15.c14_pmevcntr[counter]; pmevcntr_op_finish(env, counter); + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0= */ + ret &=3D MAKE_64BIT_MASK(0, 32); + } return ret; } else { /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR --=20 2.25.1 From nobody Mon May 13 02:15:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1661174826; cv=none; d=zohomail.com; s=zohoarc; b=m9Nc1WyQFsEC1+6tz9xg30Kx7DfTZ0lbeSahH14e0amKeIuayQjNGOKYJCaae+0TpxDiVHYbpdqXs+vjZ78pL9Vu3ljgFwinBrpUuqWYVn6/79sS3UbXlF8gCYZKuTzt1wcCGKH4A3JloV4EjS9tf3SssxXGrOFQ61TGwZnjXg4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661174826; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WKtyI8kjRNlnCB4JM27i0afmEKH1KHPL+DE/obbLKuA=; b=UkKAJOU+sZ/tZTjBpcDwnCwGcnNbMkWzfrKa2hNrrIQVPC26TPImSQ1gcmp04+bW3oU6EEgZPfYB/SS7OLZjAgcx1+BTtv60V+dfEpcASoWgExrkbM1+lQJifA+9noYuDE325vJ1vSM5PFqvy8AlrQC92ROgVdIT14uL6a5Wlj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1661174826052362.83943023812026; Mon, 22 Aug 2022 06:27:06 -0700 (PDT) Received: from localhost ([::1]:40706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7SK-0001gI-Hj for importer@patchew.org; Mon, 22 Aug 2022 09:27:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PZ-0006FO-Ss for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:13 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:33351) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PY-0001hH-93 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:13 -0400 Received: by mail-wr1-x435.google.com with SMTP id k9so13229741wri.0 for ; Mon, 22 Aug 2022 06:24:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=WKtyI8kjRNlnCB4JM27i0afmEKH1KHPL+DE/obbLKuA=; b=XIvLYfSWLsrWUnIX93zfq1Lp2LaVw/gKwEh7tArs9eWFgs4MsoJkikWAArcb2Kp0ic Pc1yJlszmCAS0J6hmGIh5JKv4ClP8nF3QfwqzHdZ24RITh2uMR5cfqTIYsVLwgTVMWnr bYSJ3IYHXsg9KUzO0Dn62IA8BOYvB0sLoPFvOVoFKVnd670fJ+sS6VWBBtk6XevP1OiS /6gUw5x6YmpuX3DVvmPhMaPWb9mVBiYiu8P5w1bHPSYyX52/4Vsd/HUioZyCCpOrerWy 8CNBbWQa8Wvau23gL8wTNcVHsamH4j1OEz/JqVafdTKP2QcGesgGeYYlTsaaS86nMevd FU4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=WKtyI8kjRNlnCB4JM27i0afmEKH1KHPL+DE/obbLKuA=; b=tEdHAeVuu6NXf0uJ1hAeiE52uQ3w/peknSCC/tFSq5gC4vOxo0xv+uVYn1hzedsP7s 4fr2AZRQHItdIJHc4IcoTHHvO9ZyozZWhuGAdvqLQydO1AoxLilxGRNgVYr+8LXFQHz3 azBxQR6xp+yc5LeFyyReHrE0fCOnsIdZEO3YFWiMuyknFyJFGu1Rt2UxAiIaUexNumkX gxQwV2tx4WussTzLyPGbHmcEBndCVk8TYKyjpRqTP1t6YjE6+C3+E23Q+L3pF6uxATVk 6WXCXffPegNWW+0N5LeKz8vmQkTL5BX3MJnxed0vFhF6GRT71OOIULkjvMc228zJ0kkS RSvw== X-Gm-Message-State: ACgBeo1xzzSDK/5zkqAOH7O1Ugn0N74ZGfDakoC91m+crDKxtqGROQfw oco9MA3+xYiVoXWLNeya2OF07g== X-Google-Smtp-Source: AA6agR6MbjTLB2g+4pzt1iTgE9KUhvfeKAyq0U4pLMJG5+sr52IIoNPabf+iB+gucZopk5Y+JkihGg== X-Received: by 2002:a5d:5269:0:b0:225:4fa6:6b03 with SMTP id l9-20020a5d5269000000b002254fa66b03mr4257352wrc.163.1661174651046; Mon, 22 Aug 2022 06:24:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' Date: Mon, 22 Aug 2022 14:23:58 +0100 Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1661174826866100001 Content-Type: text/plain; charset="utf-8" Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 compliant PMU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: update emulation.rst too --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8e494c8bea5..e36a60a4da6 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -52,6 +52,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_PMUv3p5 (PMU Extensions v3.5) - FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RASv1p1 (RAS Extension v1.1) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 78e27f778ac..fa4b0152706 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1072,7 +1072,7 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_aa64dfr0 =3D t; =20 t =3D cpu->isar.id_aa64smfr0; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3099b38e32b..4c71a0b612d 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -81,7 +81,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D cpu->isar.id_dfr0; t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 =3D t; } =20 --=20 2.25.1