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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH] hw/acpi: set ATS capability explicitly per pcie root port Date: Mon, 22 Aug 2022 14:34:35 +0530 Message-Id: <20220822090438.426748-3-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090438.426748-1-ani@anisinha.ca> References: <20220822090438.426748-1-ani@anisinha.ca> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1029; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1029.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @anisinha-ca.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661159299613100001 Currently the bit 0 of the flags field of Root Port ATS capability reporting structure sub-table under the DMAR table is set to 1. This indicates ALL_PO= RTS, thus enabling ATS capability for all pcie roots without the ability to turn= off ATS for some ports and leaving ATS on for others. This change clears the bit 0 of the flags field of the above structure and explicitly adds scopes for every pcie root port in the structure so that ATS is enabled for all of them. In future, we might add new attribite to the ro= ot ports so that we can selectively enable ATS for some and leave ATS off for others. Signed-off-by: Ani Sinha --- hw/i386/acpi-build.c | 74 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 0355bd3dda..9c5a555536 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -60,6 +60,7 @@ #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pcie_port.h" #include "hw/pci-host/q35.h" #include "hw/i386/x86-iommu.h" =20 @@ -2118,6 +2119,60 @@ dmar_host_bridges(Object *obj, void *opaque) return 0; } =20 +/* + * Insert DMAR scope for PCIE root ports + */ +static void +insert_pcie_root_port_scope(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + const size_t device_scope_size =3D 6 + 2; + /* device scope structure + 1 path entr= y */ + GArray *scope_blob =3D opaque; + + /* + * We are only interested in PCIE root ports. We can extend + * this to check for specific properties of PCIE root ports and based + * on that remove some ports from having ATS capability. + */ + if (!object_dynamic_cast(OBJECT(dev), TYPE_PCIE_ROOT_PORT)) { + return; + } + + /* Dmar Scope Type: 0x02 for all PCIE root ports */ + build_append_int_noprefix(scope_blob, 0x02, 1); + + /* length */ + build_append_int_noprefix(scope_blob, device_scope_size, 1); + /* reserved */ + build_append_int_noprefix(scope_blob, 0, 2); + /* enumeration_id */ + build_append_int_noprefix(scope_blob, 0, 1); + /* bus */ + build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); + /* device */ + build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); + /* function */ + build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); +} + +/* For a given PCI host bridge, walk and insert DMAR scope */ +static int +dmar_pcie_root_ports(Object *obj, void *opaque) +{ + GArray *scope_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + pci_for_each_device_under_bus(bus, insert_pcie_root_port_scope, + scope_blob); + } + } + + return 0; +} + /* * Intel =C2=AE Virtualization Technology for Directed I/O * Architecture Specification. Revision 3.3 @@ -2190,11 +2245,26 @@ build_dmar_q35(GArray *table_data, BIOSLinker *link= er, const char *oem_id, =20 if (iommu->dt_supported) { /* 8.5 Root Port ATS Capability Reporting Structure */ + /* + * A PCI bus walk, for each PCIE root port. + * Since we did not enable ALL_PORTS bit in the flags above, we + * need to add the scope for each pcie root port explicitly + * that are attached to bus0 with iommu enabled. + */ + scope_blob =3D g_array_new(false, true, 1); + object_child_foreach_recursive(object_get_root(), + dmar_pcie_root_ports, scope_blob); + build_append_int_noprefix(table_data, 2, 2); /* Type */ - build_append_int_noprefix(table_data, 8, 2); /* Length */ - build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Fl= ags */ + build_append_int_noprefix(table_data, + 8 + scope_blob->len, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Flags */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ + + /* now add the scope to the sub-table */ + g_array_append_vals(table_data, scope_blob->data, scope_blob->len); + g_array_free(scope_blob, true); } =20 acpi_table_end(linker, &table); --=20 2.25.1