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Tsirkin" , Igor Mammedov , Ani Sinha Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 1/4] hw/acpi: allow changes to DSDT and DMAR tables Date: Mon, 22 Aug 2022 14:34:34 +0530 Message-Id: <20220822090438.426748-2-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090438.426748-1-ani@anisinha.ca> References: <20220822090438.426748-1-ani@anisinha.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102b; envelope-from=ani@anisinha.ca; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @anisinha-ca.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661159337861100001 Content-Type: text/plain; charset="utf-8" Our next change modifies DMAR and DSDT tables. Make sure we whitelist those changes so that bios-table-test does not break. Signed-off-by: Ani Sinha --- tests/data/acpi/q35/DSDT.dmar | 0 tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 2 files changed, 2 insertions(+) create mode 100644 tests/data/acpi/q35/DSDT.dmar diff --git a/tests/data/acpi/q35/DSDT.dmar b/tests/data/acpi/q35/DSDT.dmar new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..4efed12b59 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/DSDT.dmar", +"tests/data/acpi/q35/DMAR.dmar", --=20 2.25.1 From nobody Sun May 19 02:06:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661159508; cv=none; d=zohomail.com; s=zohoarc; b=CNOBEwbOYYofI1Ld87mgnA97etC7H8FaJ+BVyeAaMPwuRRjqOd36b05UY+JBZh6uyztDWyFX5nGSIloDVqlOKC53aRsf6IVXn6VuGyGV/BA2bG9DH7nz2AK7RfY6AI2Qsmqo5Zonh/fNe3bOnmmwBUQ3x/A5AFT8sugh1XnSIM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661159508; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Uq7rnkz9r0R8TaOt9qWOib8IZqgaXtBX++KjATGxClI=; b=Sx0zQ1/wdCv1p291M7RdOtBK/wi23k2S0+7IvD3FAf7Sx+pP7Z1OnbmZUlE2eu6zgmHVMltXEG8IYk/N7CHs3qlG5rUZkx1HfvSNrdKJePMqcrjZYVBjS5RT+mqXKfC/+q0oFeunUQj1RHvleWdgEWjCaCjO6nUkmaJ1JbWLdSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166115950890458.366313542368516; Mon, 22 Aug 2022 02:11:48 -0700 (PDT) Received: from localhost ([::1]:36150 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ3TH-0005PI-PX for importer@patchew.org; Mon, 22 Aug 2022 05:11:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ3N8-0005W9-Tk for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:05:30 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:47012) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ3N4-0006sl-5y for qemu-devel@nongnu.org; Mon, 22 Aug 2022 05:05:24 -0400 Received: by mail-pj1-x1031.google.com with SMTP id o14-20020a17090a0a0e00b001fabfd3369cso10571995pjo.5 for ; Mon, 22 Aug 2022 02:05:21 -0700 (PDT) Received: from anisinha-lenovo.ba.nuagenetworks.net ([116.73.134.198]) by smtp.googlemail.com with ESMTPSA id n34-20020a635c62000000b0041c3ab14ca1sm7015428pgm.0.2022.08.22.02.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 02:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anisinha-ca.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Uq7rnkz9r0R8TaOt9qWOib8IZqgaXtBX++KjATGxClI=; b=wHuDOgNfPvPqwYwOK3VgjK8WEMDO+JvApGMnLSVsB3CknYQbHKMNWrZS4cQZx3DqUA bzdToblmpM6rf9bALQOKXe5OIL8DFKzWsydNzsZsTs1XgReldt30P4pZSAgUt7Afn+/9 mdolXMkv2sXGmayxcFLyKRkj2BRoJw8398YXN965Zt6vje7rLqiKaWGRnPcs+cOzMbnh BC+EWOgsHyEXnF8QczV/r3iVL1Kpb5ugJ/wAhfV+0vAAyX+LLuqpuihCfPxjqpyh5Ywp UTHCBViPF6R6Qfbw9zboeb7lfErv+BKdIhtZXommJf32RUHqPVpFh9m7kOjhyDjsgaXO 5MHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Uq7rnkz9r0R8TaOt9qWOib8IZqgaXtBX++KjATGxClI=; b=7mrLtnit764Qhja00l3Gp8cTh1wmtInSWyvqUQLxNtBDNpgFvVv5SfCZGZNfEjRW0b TNLNGL9Jb5zoCfSHwVOlyBqabPA4su2r2Nxfsuo9ozIOZUFU+6M1LEQD8h2PEVkQtow7 v7cyxpnH8PJyyypat7Z9aOyIxSDwSEjGzqbIarUEzuUSRhw7uj7JRf6Y/Bp0NJeaTKJs lUuhwZOx32hOeallUaEj3rZtIo0+ncZ8GcAND4FCEPzfSKAzdcdXDbM6gf2r7qEsTWyy sLawB41z6mF6d/JiLtlsRpEt3Fu6l50WzcHSMi5KzvFZ9Du5/OxZXsraoK+e7XXjENbg IYFA== X-Gm-Message-State: ACgBeo1d37vONq8GywObeZoZTkVvAvBhfxomohAkIoX4IqgiM3Mz3lAc J292Zb/5oEFddvgFBAlywLjCoeteq6TSbw== X-Google-Smtp-Source: AA6agR7WAXg7UHjILh8UQkSYm6OfmeHWMx3NTFoCBoieF0weqF3/nTgcIkhFi3fnar6HrVY8rBmH8w== X-Received: by 2002:a17:90a:ce05:b0:1fb:226c:d6b2 with SMTP id f5-20020a17090ace0500b001fb226cd6b2mr5857769pju.124.1661159120536; Mon, 22 Aug 2022 02:05:20 -0700 (PDT) From: Ani Sinha To: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 2/4] hw/acpi: set ATS capability explicitly per pcie root port Date: Mon, 22 Aug 2022 14:34:36 +0530 Message-Id: <20220822090438.426748-4-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090438.426748-1-ani@anisinha.ca> References: <20220822090438.426748-1-ani@anisinha.ca> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @anisinha-ca.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661159510717100001 Currently the bit 0 of the flags field of Root Port ATS capability reporting structure sub-table under the DMAR table is set to 1. This indicates ALL_PO= RTS, thus enabling ATS capability for all pcie roots without the ability to turn= off ATS for some ports and leaving ATS on for others. This change clears the bit 0 of the flags field of the above structure and explicitly adds scopes for every pcie root port in the structure so that ATS is enabled for all of them. In future, we might add new attribite to the ro= ot ports so that we can selectively enable ATS for some and leave ATS off for others. Signed-off-by: Ani Sinha Suggested-by: Michael Tsirkin --- hw/i386/acpi-build.c | 74 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 0355bd3dda..9c5a555536 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -60,6 +60,7 @@ #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pcie_port.h" #include "hw/pci-host/q35.h" #include "hw/i386/x86-iommu.h" =20 @@ -2118,6 +2119,60 @@ dmar_host_bridges(Object *obj, void *opaque) return 0; } =20 +/* + * Insert DMAR scope for PCIE root ports + */ +static void +insert_pcie_root_port_scope(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + const size_t device_scope_size =3D 6 + 2; + /* device scope structure + 1 path entr= y */ + GArray *scope_blob =3D opaque; + + /* + * We are only interested in PCIE root ports. We can extend + * this to check for specific properties of PCIE root ports and based + * on that remove some ports from having ATS capability. + */ + if (!object_dynamic_cast(OBJECT(dev), TYPE_PCIE_ROOT_PORT)) { + return; + } + + /* Dmar Scope Type: 0x02 for all PCIE root ports */ + build_append_int_noprefix(scope_blob, 0x02, 1); + + /* length */ + build_append_int_noprefix(scope_blob, device_scope_size, 1); + /* reserved */ + build_append_int_noprefix(scope_blob, 0, 2); + /* enumeration_id */ + build_append_int_noprefix(scope_blob, 0, 1); + /* bus */ + build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); + /* device */ + build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); + /* function */ + build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); +} + +/* For a given PCI host bridge, walk and insert DMAR scope */ +static int +dmar_pcie_root_ports(Object *obj, void *opaque) +{ + GArray *scope_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + pci_for_each_device_under_bus(bus, insert_pcie_root_port_scope, + scope_blob); + } + } + + return 0; +} + /* * Intel =C2=AE Virtualization Technology for Directed I/O * Architecture Specification. Revision 3.3 @@ -2190,11 +2245,26 @@ build_dmar_q35(GArray *table_data, BIOSLinker *link= er, const char *oem_id, =20 if (iommu->dt_supported) { /* 8.5 Root Port ATS Capability Reporting Structure */ + /* + * A PCI bus walk, for each PCIE root port. + * Since we did not enable ALL_PORTS bit in the flags above, we + * need to add the scope for each pcie root port explicitly + * that are attached to bus0 with iommu enabled. + */ + scope_blob =3D g_array_new(false, true, 1); + object_child_foreach_recursive(object_get_root(), + dmar_pcie_root_ports, scope_blob); + build_append_int_noprefix(table_data, 2, 2); /* Type */ - build_append_int_noprefix(table_data, 8, 2); /* Length */ - build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Fl= ags */ + build_append_int_noprefix(table_data, + 8 + scope_blob->len, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Flags */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ + + /* now add the scope to the sub-table */ + g_array_append_vals(table_data, scope_blob->data, scope_blob->len); + g_array_free(scope_blob, true); } =20 acpi_table_end(linker, &table); --=20 2.25.1 From nobody Sun May 19 02:06:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661159556; cv=none; d=zohomail.com; s=zohoarc; b=Y5S2f3JnQSG46grQCSJLpkjdDuTc8CrJzoEC8kyVcM+pOtSfSKIltqtowFihDcucXew9+VD/aNm2xYqD0XfJtpePoJSR5pz1vPOgmUVwAdYnjgVh1JLhhor5/aNH8Ewgdx4SvHD4Sk37jodQMXbURMGo8P7DE5roBAlVJbUzJAI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661159556; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tsirkin" , Igor Mammedov , Ani Sinha Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 3/4] tests/acpi/bios-table-test: add pcie root port device for DMAR test Date: Mon, 22 Aug 2022 14:34:37 +0530 Message-Id: <20220822090438.426748-5-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090438.426748-1-ani@anisinha.ca> References: <20220822090438.426748-1-ani@anisinha.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1036; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1036.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @anisinha-ca.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661159556666100001 Content-Type: text/plain; charset="utf-8" In the previos commit, we are explicitly adding scopes for pcie root ports = in Root Port ATS capability reporting structure. We add a pcie root port in the QEMU test command line for DMAR tests so that we can verify that the scope = of the root port has been correctly added and structure looks sane. After the changes, the above structure will look like this: +[078h 0120 2] Subtable Type : 0002 [Root Port ATS Capabil= ity] +[07Ah 0122 2] Length : 0010 + +[07Ch 0124 1] Flags : 00 +[07Dh 0125 1] Reserved : 00 +[07Eh 0126 2] PCI Segment Number : 0000 + +[080h 0128 1] Device Scope Type : 02 [PCI Bridge Device] +[081h 0129 1] Entry Length : 08 +[082h 0130 2] Reserved : 0000 +[084h 0132 1] Enumeration ID : 00 +[085h 0133 1] PCI Bus Number : 00 + +[086h 0134 2] PCI Path : 02,00 + + Signed-off-by: Ani Sinha --- tests/qtest/bios-tables-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 7c5f736b51..dc79eafbb5 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1141,7 +1141,8 @@ static void test_acpi_q35_kvm_dmar(void) data.machine =3D MACHINE_Q35; data.variant =3D ".dmar"; test_acpi_one("-machine kernel-irqchip=3Dsplit -accel kvm" - " -device intel-iommu,intremap=3Don,device-iotlb=3Don", = &data); + " -device intel-iommu,intremap=3Don,device-iotlb=3Don" + " -device pcie-root-port,bus=3Dpcie.0", &data); free_test_data(&data); } =20 --=20 2.25.1 From nobody Sun May 19 02:06:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1661159786; cv=none; d=zohomail.com; s=zohoarc; b=eprGAPLpjxKs/JsDll/e+299CCRAhe8RPEQgGS6vva1nsh2D6WuzsWon/fVgjsispaFBJo4RDcWcnladIWKuTDVxcigooScAGjl3gZeu1jXlAMgW9nE0LaxO//S9wZ0lnoGtbnW4Q4rs9KxoCjaNGqiMSICvWJ4m9OupfRNN86k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661159786; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q0ObOxK2MiZq3VBWDXHBVl7juOt1W6dENpR2gzKgWb4=; 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Tsirkin" , Igor Mammedov , Ani Sinha Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH 4/4] tests/acpi/bios-tables-test: update DSDT and DMAR table blobs Date: Mon, 22 Aug 2022 14:34:38 +0530 Message-Id: <20220822090438.426748-6-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090438.426748-1-ani@anisinha.ca> References: <20220822090438.426748-1-ani@anisinha.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42e; envelope-from=ani@anisinha.ca; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, LOTS_OF_MONEY=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @anisinha-ca.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661159788552100001 Content-Type: text/plain; charset="utf-8" Changes include explicit addition of pcie root ports in the ATS capability reporting structure and addition of a single pcie root port device in the D= MAR bios table tests. The following DSDT and DMAR table changes happen as a result of the above changes: DMAR: [000h 0000 4] Signature : "DMAR" [DMA Remapping ta= ble] -[004h 0004 4] Table Length : 00000078 +[004h 0004 4] Table Length : 00000088 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : DE [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 1] Host Address Width : 26 [025h 0037 1] Flags : 01 [026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 = 00 [030h 0048 2] Subtable Type : 0000 [Hardware Unit Definit= ion] -[032h 0050 2] Length : 0040 +[032h 0050 2] Length : 0048 [034h 0052 1] Flags : 00 [035h 0053 1] Reserved : 00 [036h 0054 2] PCI Segment Number : 0000 [038h 0056 8] Register Base Address : 00000000FED90000 [040h 0064 1] Device Scope Type : 03 [IOAPIC Device] [041h 0065 1] Entry Length : 08 [042h 0066 2] Reserved : 0000 [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF [046h 0070 2] PCI Path : 00,00 [048h 0072 1] Device Scope Type : 01 [PCI Endpoint Device] @@ -46,60 +46,79 @@ [04Ah 0074 2] Reserved : 0000 [04Ch 0076 1] Enumeration ID : 00 [04Dh 0077 1] PCI Bus Number : 00 [04Eh 0078 2] PCI Path : 00,00 [050h 0080 1] Device Scope Type : 01 [PCI Endpoint Device] [051h 0081 1] Entry Length : 08 [052h 0082 2] Reserved : 0000 [054h 0084 1] Enumeration ID : 00 [055h 0085 1] PCI Bus Number : 00 [056h 0086 2] PCI Path : 01,00 -[058h 0088 1] Device Scope Type : 01 [PCI Endpoint Device] +[058h 0088 1] Device Scope Type : 02 [PCI Bridge Device] [059h 0089 1] Entry Length : 08 [05Ah 0090 2] Reserved : 0000 [05Ch 0092 1] Enumeration ID : 00 [05Dh 0093 1] PCI Bus Number : 00 -[05Eh 0094 2] PCI Path : 1F,00 +[05Eh 0094 2] PCI Path : 02,00 [060h 0096 1] Device Scope Type : 01 [PCI Endpoint Device] [061h 0097 1] Entry Length : 08 [062h 0098 2] Reserved : 0000 [064h 0100 1] Enumeration ID : 00 [065h 0101 1] PCI Bus Number : 00 -[066h 0102 2] PCI Path : 1F,02 +[066h 0102 2] PCI Path : 1F,00 [068h 0104 1] Device Scope Type : 01 [PCI Endpoint Device] [069h 0105 1] Entry Length : 08 [06Ah 0106 2] Reserved : 0000 [06Ch 0108 1] Enumeration ID : 00 [06Dh 0109 1] PCI Bus Number : 00 -[06Eh 0110 2] PCI Path : 1F,03 +[06Eh 0110 2] PCI Path : 1F,02 -[070h 0112 2] Subtable Type : 0002 [Root Port ATS Capabil= ity] -[072h 0114 2] Length : 0008 +[070h 0112 1] Device Scope Type : 01 [PCI Endpoint Device] +[071h 0113 1] Entry Length : 08 +[072h 0114 2] Reserved : 0000 +[074h 0116 1] Enumeration ID : 00 +[075h 0117 1] PCI Bus Number : 00 -[074h 0116 1] Flags : 01 -[075h 0117 1] Reserved : 00 -[076h 0118 2] PCI Segment Number : 0000 +[076h 0118 2] PCI Path : 1F,03 -Raw Table Data: Length 120 (0x78) - 0000: 44 4D 41 52 78 00 00 00 01 15 42 4F 43 48 53 20 // DMARx.....BO= CHS +[078h 0120 2] Subtable Type : 0002 [Root Port ATS Capabil= ity] +[07Ah 0122 2] Length : 0010 + +[07Ch 0124 1] Flags : 00 +[07Dh 0125 1] Reserved : 00 +[07Eh 0126 2] PCI Segment Number : 0000 + +[080h 0128 1] Device Scope Type : 02 [PCI Bridge Device] +[081h 0129 1] Entry Length : 08 +[082h 0130 2] Reserved : 0000 +[084h 0132 1] Enumeration ID : 00 +[085h 0133 1] PCI Bus Number : 00 + +[086h 0134 2] PCI Path : 02,00 + DSDT: DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Scope (\) { OperationRegion (DBG, SystemIO, 0x0402, One) Field (DBG, ByteAcc, NoLock, Preserve) { DBGB, 8 } @@ -3261,23 +3261,59 @@ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State { Return (Zero) } Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State { Return (Zero) } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (Zero) } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device= , x=3D0-9 + { + PCEJ (BSEL, _SUN) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific= Method + { + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM =3D Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + Method (PCNT, 0, NotSerialized) { + ^S10.PCNT () } } } } Signed-off-by: Ani Sinha --- tests/data/acpi/q35/DMAR.dmar | Bin 120 -> 136 bytes tests/data/acpi/q35/DSDT.dmar | Bin 0 -> 8421 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/q35/DMAR.dmar b/tests/data/acpi/q35/DMAR.dmar index 0dca6e68ad8a8ca5b981bcfbc745385a63e9f216..1c1a935ddab174059b8570f67f3= b4cfbe3df2193 100644 GIT binary patch delta 71 zcmb>EVB~V~bqwlYU|?XpH<3$&(PN^qssR%Rkk7!xzzC-0VKftz&&6r^q6S zfh0x%SpgEqhoT9aphr4jfZkf5K(95>OMCOJ0eb2omt2b?K1KchnH^<@q=3D1-*)&8^J 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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Cc: yvugenfi@redhat.com, jusual@redhat.com, kkostiuk@redhat.com, ybendito@redhat.com Subject: [PATCH] hw/acpi: set ATS capability explicitly per pcie root port Date: Mon, 22 Aug 2022 14:34:35 +0530 Message-Id: <20220822090438.426748-3-ani@anisinha.ca> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822090438.426748-1-ani@anisinha.ca> References: <20220822090438.426748-1-ani@anisinha.ca> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::1029; envelope-from=ani@anisinha.ca; helo=mail-pj1-x1029.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @anisinha-ca.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1661159299613100001 Currently the bit 0 of the flags field of Root Port ATS capability reporting structure sub-table under the DMAR table is set to 1. This indicates ALL_PO= RTS, thus enabling ATS capability for all pcie roots without the ability to turn= off ATS for some ports and leaving ATS on for others. This change clears the bit 0 of the flags field of the above structure and explicitly adds scopes for every pcie root port in the structure so that ATS is enabled for all of them. In future, we might add new attribite to the ro= ot ports so that we can selectively enable ATS for some and leave ATS off for others. Signed-off-by: Ani Sinha --- hw/i386/acpi-build.c | 74 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 0355bd3dda..9c5a555536 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -60,6 +60,7 @@ #include "hw/i386/fw_cfg.h" #include "hw/i386/ich9.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pcie_port.h" #include "hw/pci-host/q35.h" #include "hw/i386/x86-iommu.h" =20 @@ -2118,6 +2119,60 @@ dmar_host_bridges(Object *obj, void *opaque) return 0; } =20 +/* + * Insert DMAR scope for PCIE root ports + */ +static void +insert_pcie_root_port_scope(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + const size_t device_scope_size =3D 6 + 2; + /* device scope structure + 1 path entr= y */ + GArray *scope_blob =3D opaque; + + /* + * We are only interested in PCIE root ports. We can extend + * this to check for specific properties of PCIE root ports and based + * on that remove some ports from having ATS capability. + */ + if (!object_dynamic_cast(OBJECT(dev), TYPE_PCIE_ROOT_PORT)) { + return; + } + + /* Dmar Scope Type: 0x02 for all PCIE root ports */ + build_append_int_noprefix(scope_blob, 0x02, 1); + + /* length */ + build_append_int_noprefix(scope_blob, device_scope_size, 1); + /* reserved */ + build_append_int_noprefix(scope_blob, 0, 2); + /* enumeration_id */ + build_append_int_noprefix(scope_blob, 0, 1); + /* bus */ + build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); + /* device */ + build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); + /* function */ + build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); +} + +/* For a given PCI host bridge, walk and insert DMAR scope */ +static int +dmar_pcie_root_ports(Object *obj, void *opaque) +{ + GArray *scope_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + pci_for_each_device_under_bus(bus, insert_pcie_root_port_scope, + scope_blob); + } + } + + return 0; +} + /* * Intel =C2=AE Virtualization Technology for Directed I/O * Architecture Specification. Revision 3.3 @@ -2190,11 +2245,26 @@ build_dmar_q35(GArray *table_data, BIOSLinker *link= er, const char *oem_id, =20 if (iommu->dt_supported) { /* 8.5 Root Port ATS Capability Reporting Structure */ + /* + * A PCI bus walk, for each PCIE root port. + * Since we did not enable ALL_PORTS bit in the flags above, we + * need to add the scope for each pcie root port explicitly + * that are attached to bus0 with iommu enabled. + */ + scope_blob =3D g_array_new(false, true, 1); + object_child_foreach_recursive(object_get_root(), + dmar_pcie_root_ports, scope_blob); + build_append_int_noprefix(table_data, 2, 2); /* Type */ - build_append_int_noprefix(table_data, 8, 2); /* Length */ - build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Fl= ags */ + build_append_int_noprefix(table_data, + 8 + scope_blob->len, 2); /* Length */ + build_append_int_noprefix(table_data, 0, 1); /* Flags */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ build_append_int_noprefix(table_data, 0, 2); /* Segment Number */ + + /* now add the scope to the sub-table */ + g_array_append_vals(table_data, scope_blob->data, scope_blob->len); + g_array_free(scope_blob, true); } =20 acpi_table_end(linker, &table); --=20 2.25.1