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([171.76.82.68]) by smtp.gmail.com with ESMTPSA id w20-20020a056808091400b003432bb4322esm1472388oih.40.2022.08.19.21.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 21:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc; bh=cbHcgzSs8k/RCMfZQqdwlcUrWThNPZ+kkqaV5LAiyLs=; b=ZZGgw5Ehwppzf2PM/uCWIB94WiZcmgm/dOZjPtu9rCKfNgV7dh48uBKYnJWzI+zNR5 vlDhaOn7gLT0UcTHWAt1lW2DwcidpyBrYPg+Pg6ObSx7utWao/KPf2BllpF/Wa4XIStw 1ALQ1dMGdeO7vvW3a+6ZLQ0NdgSAyT7YK1iXsNr+VKxRIM10Uw+mJFHuvWMKs9mAlnPv gGHKofcHVf7FnkcgRjuXBxT76bXnSA/wV0OKPetpaC1Q2yKIp29iQEaAc5dAsO8cjvqk eS9YZOjlBiZYTSqlkQ26QWTGXM+yqxzAdehljmW41fxpf29N+sXS3yxTfPrHWiYMSyzS 3KkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc; bh=cbHcgzSs8k/RCMfZQqdwlcUrWThNPZ+kkqaV5LAiyLs=; b=xeG3lUeYJSGIcnO6nY0BgMWZZTfmOuCdLK0XC4rFRKzqgWLIJ+k2gEaj8q0pwAFMLq gO0YQd9XPzowcb0y5wC0rE4/qeT6VYY0/MjQdw0Xk69qnkWrQZR47T8Rezkklhlb/1EW uC5N5hiFq7dK3RlTfnKEFmcqVWyLAwnmqgGGHzrzddb9zet2yO1fKSrawNTqnMZ1DKDS p98/5zcmGiDDMcoaFiOlY2vezX4GzjI+8MIQU1cnAXXppICULTMq1UrfOgg8Hip4oCp2 g7ScJ9Wyik8jT15Ei4meQTkBxs3enPjXdr3Rnyxe1r9XnwaWhlN5/UL4cKtquJxnT5dK FKCQ== X-Gm-Message-State: ACgBeo2b1FiJSvQ+em3mvBvgXWuQWi4OZTpIdvH280KIs2rSg2qjbkev VnYUONNIqmjos31rMhUJKK4KUA== X-Google-Smtp-Source: AA6agR5c0XOXOL/iZwPPkxyyVUFRSlY43sdb1zxoaSytXNNpy0EEDdx4YLTxNDMoR8oEbDYgi7J0xw== X-Received: by 2002:a05:6870:4152:b0:10e:84d9:6119 with SMTP id r18-20020a056870415200b0010e84d96119mr8232529oad.178.1660969835044; Fri, 19 Aug 2022 21:30:35 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Richard Henderson , Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Andrew Jones Subject: [PATCH v3] target/riscv: Use official extension names for AIA CSRs Date: Sat, 20 Aug 2022 09:59:58 +0530 Message-Id: <20220820042958.377018-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=apatel@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1660969978113100001 Content-Type: text/plain; charset="utf-8" The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-i= nterrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- Changes since v2: - Use env_archcpu() to get RISCVCPU * from CPURISCVState * Changes since v1: - Remove redundant "has_aia" parameter from riscv_cpu_pending_to_irq() --- hw/intc/riscv_imsic.c | 4 +++- hw/riscv/virt.c | 13 ++----------- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 3 ++- target/riscv/csr.c | 24 ++++++++++++++++++------ 6 files changed, 31 insertions(+), 26 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 8615e4cc1d..4d4d5b50ca 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -344,9 +344,11 @@ static void riscv_imsic_realize(DeviceState *dev, Erro= r **errp) =20 /* Force select AIA feature and setup CSR read-modify-write callback */ if (env) { - riscv_set_feature(env, RISCV_FEATURE_AIA); if (!imsic->mmode) { + rcpu->cfg.ext_ssaia =3D true; riscv_cpu_set_geilen(env, imsic->num_pages - 1); + } else { + rcpu->cfg.ext_smaia =3D true; } riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, riscv_imsic_rmw, imsic); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e779d399ae..b041b33afc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -261,17 +261,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, qemu_fdt_add_subnode(mc->fdt, intc_name); qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", intc_phandles[cpu]); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_AIA)) { - static const char * const compat[2] =3D { - "riscv,cpu-intc-aia", "riscv,cpu-intc" - }; - qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", - (char **)&compat, ARRAY_SIZE(compat)= ); - } else { - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", - "riscv,cpu-intc"); - } + qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + "riscv,cpu-intc"); qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL,= 0); qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d11113fbaa..3cf0c86661 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), @@ -669,10 +671,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (cpu->cfg.aia) { - riscv_set_feature(env, RISCV_FEATURE_AIA); - } - if (cpu->cfg.debug) { riscv_set_feature(env, RISCV_FEATURE_DEBUG); } @@ -1058,7 +1056,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), + DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), + DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 42edfa4558..15cad73def 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -85,7 +85,6 @@ enum { RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA, - RISCV_FEATURE_AIA, RISCV_FEATURE_DEBUG }; =20 @@ -452,6 +451,8 @@ struct RISCVCPUConfig { bool ext_zve64f; bool ext_zmmul; bool ext_sscofpmf; + bool ext_smaia; + bool ext_ssaia; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 @@ -472,7 +473,6 @@ struct RISCVCPUConfig { bool mmu; bool pmp; bool epmp; - bool aia; bool debug; uint64_t resetvec; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 81948b37dd..67e4c0efd2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -309,6 +309,7 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_pr= io, uint64_t pending, uint8_t *iprio) { + RISCVCPU *cpu =3D env_archcpu(env); int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; =20 @@ -317,7 +318,7 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 irq =3D ctz64(pending); - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + if (!((extirq =3D=3D IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ss= aia)) { return irq; } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2dcd4e5b2d..b96db1b62b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -181,7 +181,9 @@ static RISCVException any32(CPURISCVState *env, int csr= no) =20 static int aia_any(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -190,7 +192,9 @@ static int aia_any(CPURISCVState *env, int csrno) =20 static int aia_any32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -217,7 +221,9 @@ static int smode32(CPURISCVState *env, int csrno) =20 static int aia_smode(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -226,7 +232,9 @@ static int aia_smode(CPURISCVState *env, int csrno) =20 static int aia_smode32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -282,7 +290,9 @@ static RISCVException pointer_masking(CPURISCVState *en= v, int csrno) =20 static int aia_hmode(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -291,7 +301,9 @@ static int aia_hmode(CPURISCVState *env, int csrno) =20 static int aia_hmode32(CPURISCVState *env, int csrno) { - if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 --=20 2.34.1