From nobody Sat May 4 07:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1660908127; cv=none; d=zohomail.com; s=zohoarc; b=QVlkThgm9RQhRk+ZfHM/tXxxfLJN7S4N91HXdG/vVmTV3PoTVANXeQ7p2coQXom7Bqx7LAIlPnyuC6i3SN6oBcEZHaSI0AmHVMYUnPLfzGNADnrb976sYr+uO9lJVUB2lg7IwSoPNzxgBw9k6lTn1d8R074gMnQMtNKcPLac58c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660908127; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gmgWZcEd2xgM6CGJtMX2e3RN3Kslo8iCQtt3bLXG/as=; b=BdczGF/TczPl047mlsG5MVMvqi4Fvbgs2S/Fx5top4NiKiXOQhZ5NGRAd6P6ObdZZ1GPEh3KaNcBjyXC9uNGvnIoUTk2kSQ2EDjvcjTVqAyKj8TX0eytX7wWg13hyB06R69+OCg299ncSdRAuksp3DRelBzRporKjOPtSMRPl3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660908126991523.1008247276723; Fri, 19 Aug 2022 04:22:06 -0700 (PDT) Received: from localhost ([::1]:43710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oP04j-0007ii-OA for importer@patchew.org; Fri, 19 Aug 2022 07:22:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOzkN-0002Ce-0Y for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:07 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:33348) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oOzkG-0001Q6-HZ for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:02 -0400 Received: by mail-wr1-x436.google.com with SMTP id k9so4784375wri.0 for ; Fri, 19 Aug 2022 04:00:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=gmgWZcEd2xgM6CGJtMX2e3RN3Kslo8iCQtt3bLXG/as=; b=wBXAy7+sSeyMEqVnntIC1ZeLi6BGN4wS3BnY73ClYHUItCTrG9dH8HCgL75ICYr0p0 YEplB0xzns0gpHECYIrHWTOabRZs1lDo7W6ULemAsFxNJhEpGYrYCpefSWzQGbm8NWE/ 2h3EX7v9TlhSrtmKtk6z/RC8gFdPWPw2iAaeGv2ZLOEUfMxIasAdZ1f370yf2u3aAkW5 nDsjUEHehDljKX5IvtQa1BKM37h302dLASyU5m3hBpx2fqFt06FcA+nZT5riBY713hAM 54msD/1aqUCrES5D5MPKZMAD4VEk4vCpODdch7C0yiywOUPHevz8T3Y0n8UIebeD8Z5V OY8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=gmgWZcEd2xgM6CGJtMX2e3RN3Kslo8iCQtt3bLXG/as=; b=wSPyxJ5ZYPKRk1ulCJN/tKxYqh9Tlsmrq9Lz0HsNWRzXXZB6FChDPX4ZCYSGU8Hx3u U/MLxwPqXu+VvAGDr4NykR15HWSPHaSloJuBTINWk8Buw6eP55uZNh9CjfsrC1rGm6Nx 9++br/qqnGRF6o3+ccAM8WYQvz2Hr1akl6Rstm/P2oQ7LZp0KNSI4lYe6lpuR+/Z0+5X O7Qnt6n/rIYlqWjdTeZLmkshtsaaoGSK3sAekjjI33ut7k+gLKqM5PZ2TWC4isskJIxz APTosEHttP36k3rbeSHd2o4L/tHT6l16BMp6+k0dz4ox520hhgdkjVbK46PvuSEruOIP GbsQ== X-Gm-Message-State: ACgBeo3JxlbEqjdrss0Qn/wo6M1QZnLD24eCy2HgLBeY/F5/x781l5B6 xdvFiyX3Q4hcdvZ3iHFoEDyA3A== X-Google-Smtp-Source: AA6agR5IsRs0+LIAr/G2doP9i8eLJM8EcrYDN2nxvC9FeyS7xH1UM9JCSiLdTPy5Q5yq+9jgYkrKmw== X-Received: by 2002:a5d:4204:0:b0:225:382f:a8be with SMTP id n4-20020a5d4204000000b00225382fa8bemr1631192wrq.379.1660906855117; Fri, 19 Aug 2022 04:00:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/6] target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8 Date: Fri, 19 Aug 2022 12:00:47 +0100 Message-Id: <20220819110052.2942289-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819110052.2942289-1-peter.maydell@linaro.org> References: <20220819110052.2942289-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660908128093100001 Content-Type: text/plain; charset="utf-8" In the AArch32 ID register scheme, coprocessor registers with encoding cp15, 0, c0, c{0-7}, {0-7} are all in the space covered by what in v6 and v7 was called the "CPUID scheme", and are supposed to RAZ if they're not allocated to a specific ID register. For our pre-v8 CPUs we get this right, because the regdefs in id_pre_v8_midr_cp_reginfo[] cover these RAZ requirements. However for v8 we failed to put in the necessary patterns to cover this, so we end up UNDEFing on everything we didn't have an ID register for. This is a problem because in Armv8 some encodings in 0, c0, c3, {0-7} are now being used for new ID registers, and guests might thus start trying to read them. (We already have one of these: ID_PFR2.) For v8 CPUs, we already have regdefs for 0, c0, c{0-2}, {0-7} (that is, the space is completely allocated with no reserved spaces). Add entries to v8_idregs[] covering 0, c0, c3, {0-7}: * c3, {0-2} is the reserved AArch32 space corresponding to the AArch64 MVFR[012]_EL1 * c3, {3,5,6,7} are reserved RAZ for both AArch32 and AArch64 (in fact some of these are given defined meanings in Armv8.6, but we don't implement them yet) * c3, 4 is ID_PFR2 (already defined) We then programmatically add RAZ patterns for AArch32 for 0, c0, c{4..15}, {0-7}: * c4-c7 are unused, and not shared with AArch64 (these are the encodings corresponding to where the AArch64 specific ID registers live in the system register space) * c8-c15 weren't required to RAZ in v6/v7, but v8 extends the AArch32 reserved-should-RAZ space to cover these; the equivalent area of the AArch64 sysreg space is not defined as must-RAZ Note that the architecture allows some registers in this space to return an UNKNOWN value; we always return 0. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 65 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d7bc467a2a5..c171770b035 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7345,11 +7345,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, not_v7_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V8)) { - /* AArch64 ID registers, which all have impdef reset values. + /* + * v8 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots * must all RAZ, not UNDEF; future architecture versions may * define new registers here. + * ID registers which are AArch64 views of the AArch32 ID registers + * which already existed in v6 and v7 are handled elsewhere, + * in v6_idregs[]. */ + int i; ARMCPRegInfo v8_idregs[] =3D { /* * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system @@ -7539,7 +7544,34 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.mvfr2 }, - { .name =3D "MVFR3_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + /* + * "0, c0, c3, {0,1,2}" are the encodings corresponding to + * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding + * as RAZ, since it is in the "reserved for future ID + * registers, RAZ" part of the AArch32 encoding space. + */ + { .name =3D "RES_0_C0_C3_0", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "RES_0_C0_C3_1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "RES_0_C0_C3_2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + /* + * Other encodings in "0, c0, c3, ..." are STATE_BOTH because + * they're also RAZ for AArch64, and in v8 are gradually + * being filled with AArch64-view-of-AArch32-ID-register + * for new ID registers. + */ + { .name =3D "RES_0_C0_C3_3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, @@ -7549,17 +7581,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_pfr2 }, - { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + { .name =3D "RES_0_C0_C3_5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, - { .name =3D "MVFR6_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + { .name =3D "RES_0_C0_C3_6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, - { .name =3D "MVFR7_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + { .name =3D "RES_0_C0_C3_7", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, @@ -7625,6 +7657,29 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); + + for (i =3D 4; i < 16; i++) { + /* + * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32. + * For pre-v8 cores there are RAZ patterns for these in + * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here. + * v8 extends the "must RAZ" part of the ID register space + * to also cover c0, 0, c{8-15}, {0-7}. + * These are STATE_AA32 because in the AArch64 sysreg space + * c4-c7 is where the AArch64 ID registers live (and we've + * already defined those in v8_idregs[]), and c8-c15 are not + * "must RAZ" for AArch64. + */ + g_autofree char *name =3D g_strdup_printf("RES_0_C0_C%d_X", i); + ARMCPRegInfo v8_aa32_raz_idregs =3D { + .name =3D name, + .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 0, .crm =3D i, .opc2 =3D= CP_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }; + define_one_arm_cp_reg(cpu, &v8_aa32_raz_idregs); + } } =20 /* --=20 2.25.1 From nobody Sat May 4 07:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=2SwX3hUzWovagIgXNOcUYZeZcVjENtYaAi9CW1/+M/4=; b=SAPTz6qokLZqjkrdp23cbGRtyNxkarU+3wrGR7pD4C3qDbHsypxqx32HBy5LEMUqEk aM62J454dKBXHWtZA5e4cl2euedCqyzj1lAZJFeHyj5dEKuPMYU6CFktGATJIqZtfU4o 49pWWtDDIJ/hw5r9WB7iv59/mL+ssAUvSDnZ+1gj5mLodAtyaQobP97f7sBZ8o5mUrGz sUKPZ39+Tz/ZcORxpyNnk8ymxMgeZynJZtiyulaYUNVbv4abqCKf+NjqbCzQO+kz3m3n aPIQr4N4FXsSCWlzIqN3qj38vqLErWrHSZrJ6GVbuf4Oca00eXIKUephTRTX/xA9OlG9 4gcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=2SwX3hUzWovagIgXNOcUYZeZcVjENtYaAi9CW1/+M/4=; b=xfEKSjgHQoWdbKx6phjpCnTsaDpQ3k9o25gGVZqpZSS5I11AGlx+E2JNGQhBfU/AY6 qcQyDQdiX6aryI/ZWJmGBEhcvGL7qqfWoPJOi8M8Mx/NHUZzdxjznqp/t+3Xc9efstC4 nbWurfn6zcnEao59doJoMgZOKXCMA/geJXxXp324qEhWdxs454XkmfeSwDJ6ONyOzq1t U7PDe7As4YyBqSShJlPJoxyiF8bNaMRGz1k5/5PcPj7Mm7wA4iumAw/j6bgVVvpKiS2+ oYcjUpf1M+Gn06fYwkPH5gqXKszLVm2jajMUl6JxE8bJ2J4KPRBObrBxEwfF+wes5Sgs aVJQ== X-Gm-Message-State: ACgBeo1c6wUUuyMRGBfRGti0DUtZNdFImlNAjT91p5yvZichjg+rx4Hn 8JJTNzn1bWWh62dxFkyyBooUxA== X-Google-Smtp-Source: AA6agR7BNFhRQ1A9do+A2HDmHKi+luEEDmZy6X/FK4l6tPm3JxrM8+hCC1oq0+hX3HolBZgAYCXZgQ== X-Received: by 2002:a5d:6d04:0:b0:21f:877:e2ef with SMTP id e4-20020a5d6d04000000b0021f0877e2efmr4062500wrq.131.1660906855887; Fri, 19 Aug 2022 04:00:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/6] target/arm: Sort KVM reads of AArch32 ID registers into encoding order Date: Fri, 19 Aug 2022 12:00:48 +0100 Message-Id: <20220819110052.2942289-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819110052.2942289-1-peter.maydell@linaro.org> References: <20220819110052.2942289-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660907372467100001 Content-Type: text/plain; charset="utf-8" The code that reads the AArch32 ID registers from KVM in kvm_arm_get_host_cpu_features() does so almost but not quite in encoding order. Move the read of ID_PFR2 down so it's really in encoding order. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/kvm64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 9b9dd46d782..84c4c85f405 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -608,8 +608,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 1, 0)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, ARM64_SYS_REG(3, 0, 0, 1, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, @@ -643,6 +641,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, + ARM64_SYS_REG(3, 0, 0, 3, 4)); =20 /* * DBGDIDR is a bit complicated because the kernel doesn't --=20 2.25.1 From nobody Sat May 4 07:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1660908073; cv=none; d=zohomail.com; s=zohoarc; b=J1hZX7jjVwDS9TYlW+L1Qb/enacnFxnCF3e5m0eZ0ry/ZWXK4TbCWaeEmcs0/jzY6uZL31U9BESG+qiJZeFmE1jj3tectLW0/YLioQUAYXU0OtOEbvdqT3hwAvmCHBS4aRRFT0F19JrO8uQq89Uc9lQ66NwMpWprZD66nfDIy2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660908073; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rlB3te70E8fDcNZgIxgUZkmq5hKy8dXzvxbhDulIQgc=; b=GwLoUoM+bcKBhUjiKIpa1bRQ+xMD0xlO8AGXHfuk7Z+bkj4CzblD22o9Xm72dU4SSqQO1xuMgYXNRvaNA2j66OgxynOdE8yvhqYPr/UDP0kjl5pGZ6/MhDc9nSAzWEgkCAulJ4y4nHCQuOlm5w09ug8KUvsEDmeorp8ylaa/SMA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660908073898435.7591291682004; Fri, 19 Aug 2022 04:21:13 -0700 (PDT) Received: from localhost ([::1]:59254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oP03r-0006nx-IG for importer@patchew.org; Fri, 19 Aug 2022 07:21:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOzkO-0002DE-I0 for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:07 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:46733) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oOzkH-0001QW-Vl for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:03 -0400 Received: by mail-wm1-x336.google.com with SMTP id k6-20020a05600c1c8600b003a54ecc62f6so2299140wms.5 for ; Fri, 19 Aug 2022 04:00:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=rlB3te70E8fDcNZgIxgUZkmq5hKy8dXzvxbhDulIQgc=; b=jQwwI7ZsZYyohUGFe1oyhFvha5d7NUCU+ZFyNS549L2JAmwiV7YsSs4LfHPNdE5hpt Gy/QsVKdxnwpdPvpxdxJlzfF667tP6HKwPaNwq4xCuggnWA3mfv1A1bRTOXDHY/m0vAJ sM2GzR0aEeROPjIOG3ipdTDeO7WxJyFrNLsXIQsU6kO9dFcKUiXsr7ic7rZszHh7z3d/ drM+NbY1r6EX/Xs/0iHgAx0aEtC20fUyG3PijnCMi8xMp8ZoM6TD0EOCDKG/6+lR05Od Li1k53zTJ6CR4BbQqaUlRpuLCKRKFG6sZhEYz2uWK7eH135LzGI33FjrUefeFRrjiTir 6TbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=rlB3te70E8fDcNZgIxgUZkmq5hKy8dXzvxbhDulIQgc=; b=x8ZHIco+Kl+23nuA7BjQBlmVem0MMC7iw+lA0Pe7zLuj32UqQKASbqNEAFKPMKSKxg Be69RWyBhcGM23NV1kv7/t6SHeMO1dvXS8aRJ6B+5wMyWlaW1nm9mibCG2IB6dGoZ/zX wo16UpCf6XNRvjBflEk10pk9AQavxigLOPSM8BpE7vb7XzKq79BEQNIqTJXMTZ39isjB MEmzwLeuuGLfdRFOw5wDoez7Y8YA9X05balYRKIZuZXdWvZnDocq6/on+7V3XZJvrKHH +FV8AK8/zwEZihwwb3WqY4Dmp31a2fmcq+1B2NCv5kAAkfYs8/ScHLnqVrtDCKr+Dc2u i1+g== X-Gm-Message-State: ACgBeo0UapYqdPVCPubTosaPzT7zGQW34fGW0YnonoUACKv/QAxdjKHD tN8LSGgp7kYcRAaA35Fx9hIbfAD8ABicYQ== X-Google-Smtp-Source: AA6agR4Ge7toZL9q9WrkMB4nGAB7moq1a7ZtpQ6yYQc1Cp7hxb9f4o73hFfjyJL54eU3u11FrnFL0w== X-Received: by 2002:a1c:f317:0:b0:3a5:e38f:46b with SMTP id q23-20020a1cf317000000b003a5e38f046bmr4357252wmq.98.1660906856620; Fri, 19 Aug 2022 04:00:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/6] target/arm: Implement ID_MMFR5 Date: Fri, 19 Aug 2022 12:00:49 +0100 Message-Id: <20220819110052.2942289-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819110052.2942289-1-peter.maydell@linaro.org> References: <20220819110052.2942289-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660908075895100001 Content-Type: text/plain; charset="utf-8" In Armv8.6 a new AArch32 ID register ID_MMFR5 is defined. Implement this; we want to be able to use it to report to the guest that we implement FEAT_ETS. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5168e3d837e..fcc5927587e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -975,6 +975,7 @@ struct ArchCPU { uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_mmfr4; + uint32_t id_mmfr5; uint32_t id_pfr0; uint32_t id_pfr1; uint32_t id_pfr2; diff --git a/target/arm/helper.c b/target/arm/helper.c index c171770b035..07378519259 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7586,11 +7586,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, - { .name =3D "RES_0_C0_C3_6", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "ID_MMFR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->isar.id_mmfr5 }, { .name =3D "RES_0_C0_C3_7", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 84c4c85f405..2d737c443eb 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -643,6 +643,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, + ARM64_SYS_REG(3, 0, 0, 3, 6)); =20 /* * DBGDIDR is a bit complicated because the kernel doesn't --=20 2.25.1 From nobody Sat May 4 07:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1660907365; cv=none; d=zohomail.com; s=zohoarc; b=QWFZCAFyiZ4UdH47/FKHH+puMYyDsxEzwFsclt8zVNOVlytLOGyTVil5CXUIMerJcBOWTtpwwNjQtj8vtkchObhY6TveVcs0Txi9v8m0Kh4hQb4iIj77SKevVx667hHtFVr2J9XL7nQBws55GpEFVaxd+3m0ZmJu34huNrjk1Ho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660907365; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D9s+L5yVb1BMeJ0aqDKJfJ1DqXUabclfNuvxPJ/OZKY=; b=hc9xjTRQqlxlUYgdooyRmMibcx9XHOvjLEojtxxBSfLhu/qquvy3sQZzB9Gd3Sry9XGGo2vW5i1Ff39ekkkCOEF2xaasX8hxA2n2reXgvjtH74nD1cEKqnPRCquG9AezUT8mwai/idHb+fJfG9Cs2Ztxpuhb/WgjjrV0nHdEQcw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660907365061484.0146005875589; Fri, 19 Aug 2022 04:09:25 -0700 (PDT) Received: from localhost ([::1]:49136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oOzsQ-0005fG-Ql for importer@patchew.org; Fri, 19 Aug 2022 07:09:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOzkP-0002DZ-79 for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:07 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:38830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oOzkJ-0001Qn-2H for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:04 -0400 Received: by mail-wm1-x334.google.com with SMTP id n23-20020a7bc5d7000000b003a62f19b453so850216wmk.3 for ; Fri, 19 Aug 2022 04:00:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=D9s+L5yVb1BMeJ0aqDKJfJ1DqXUabclfNuvxPJ/OZKY=; b=PDe/8g05I8TMQT04pgN/A3wmwfrLSaX2mCBCyikdzy/VLmdQXSQ692hqL8mZGFD+j/ URsQFRh4qykhw5MY1f/yLskh75MaVqzUBF2hmgCLpnlBW3LpZzBcYsCixeGqEFfhjGqM G48VNHxADoG35DeSwqgIZns1yBz/5Aw+KXP1A0MvElnjW9+3BpOD16+Q7thYPoZHN9gA dMm5ezNSytaArVkgRT7SEVg50DabZk49DMMbUBPHI1yo7bEoCNZPmm3KmtcBx5zaiHVd /y+dC4YDKKSLCRLcDuJNae0nXvBf02l/9K2DREbNIS33N6FkUKPZNwXEXYtnL45Z0sqV 62FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=D9s+L5yVb1BMeJ0aqDKJfJ1DqXUabclfNuvxPJ/OZKY=; b=rVWs/h4bqQIz3uR7PfjZAfHjVo9JJFyWSi57Xkrf2r8p/KBo7G2er/5YDcmxtXrLPH SxsGVtBlZnEy+o1LAKOPIsiN76LwS8hRAg6gbMkQWGoWg7aqzsKhzXHpP7maPIErLcRb tmcXuUtoRwjJ4yFAOJjvMpbKRlWA5tlY4OQUajP83SJOHalYlLhv9nRkBhn/1c50bd2g tDFeQy5RLzbvKkX+isi/sx256qvMaSfvtZt6TCCwh0MV9WktSiS7plOpU0+6JxDbTtha SD+TWAW+TE5dSDj0f0kfRsAadWghuPCqh4KKhjj2fsi267VmDLSFc4Tw5FgMRqlK6Bnm GLxQ== X-Gm-Message-State: ACgBeo2khyAsl+OhyFH9hBLB5g3jh42L/5Z+X9/PM9i5NSw56RncWNZs 23F4uNUmQ0i7/pUQ3fgEfUJczQ== X-Google-Smtp-Source: AA6agR4giTHeR4W52KOkumwu6/FENRngcuH5fmPOScjHP90lhlF39PxC0TtrT/YMojmkgzxvKyq8gQ== X-Received: by 2002:a05:600c:490:b0:3a5:a6aa:bf2f with SMTP id d16-20020a05600c049000b003a5a6aabf2fmr7602020wme.17.1660906857521; Fri, 19 Aug 2022 04:00:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/6] target/arm: Implement ID_DFR1 Date: Fri, 19 Aug 2022 12:00:50 +0100 Message-Id: <20220819110052.2942289-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819110052.2942289-1-peter.maydell@linaro.org> References: <20220819110052.2942289-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660907366659100001 Content-Type: text/plain; charset="utf-8" In Armv8.6, a new AArch32 ID register ID_DFR1 is defined; implement it. We don't have any CPUs with features that they need to advertise here yet, but plumbing in the ID register gives it the right name when debugging and will help in future when we do add a CPU that has non-zero ID_DFR1 fields. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fcc5927587e..fa24ce9f96b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -983,6 +983,7 @@ struct ArchCPU { uint32_t mvfr1; uint32_t mvfr2; uint32_t id_dfr0; + uint32_t id_dfr1; uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 07378519259..7ff03f1a4ba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7581,11 +7581,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_pfr2 }, - { .name =3D "RES_0_C0_C3_5", .state =3D ARM_CP_STATE_BOTH, + { .name =3D "ID_DFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->isar.id_dfr1 }, { .name =3D "ID_MMFR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 2d737c443eb..1197253d12f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -643,6 +643,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, + ARM64_SYS_REG(3, 0, 0, 3, 5)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, ARM64_SYS_REG(3, 0, 0, 3, 6)); =20 --=20 2.25.1 From nobody Sat May 4 07:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1660907816; cv=none; d=zohomail.com; s=zohoarc; b=PTy/92GANIO1dXdO9m+MGpA+X5cP1Oz27TIRVCdtL6oN9eRHxqKRKjuOmUQK68g5lZVKCcFWA5jxTqOYSMZ+h3R0sZ7ojSTurdPu252icxyd8+OaNyeQEewPRrw3k38/6ZWOmZVnXfALz0IdFTQI/0b+0E8Fw9FMNubljGgfZfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660907816; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T2d6RVLzyzWzf/spKdraeHdOh9Hi3cYnCCfjXRwnKAY=; b=dryEr34CvLgROcwZof1dNpSm95aZcl0svzR4DwJICCbPO90LtmJCW5HBZNd0urtxh3Y2tkeWpcjIN67wVvTuPaMbgQQM/RZwvx7nol7rsLXHiHafaY6XcuVMrR88SGXOMAhtIRPKzAOYKm8rvrNsxAC6U51IPCWeI9hIghgjVEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166090781660895.67392192464604; Fri, 19 Aug 2022 04:16:56 -0700 (PDT) Received: from localhost ([::1]:46976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oOzzj-0002iT-4d for importer@patchew.org; Fri, 19 Aug 2022 07:16:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOzkP-0002Dh-Jc for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:07 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:37814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oOzkJ-0001Qu-Od for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:05 -0400 Received: by mail-wr1-x42a.google.com with SMTP id n7so4763494wrv.4 for ; Fri, 19 Aug 2022 04:00:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=T2d6RVLzyzWzf/spKdraeHdOh9Hi3cYnCCfjXRwnKAY=; b=pB3Rw7JHLxETXLhhQKkoqOxrSCKbQO5QRkNaCMeTh3O1z5NGfzSwSqUG8szYxOsBkE HJ7NtJBPucCCfKNK7IasaTWHoFoF4myWOagjqgj0DsWq3tFqz1WVez6ttfZ7H23pw85J 92zMJJhZfoNcxuxKx1PnvAv8xPsgqlaH7/JFOrObjkYX/KBU9Sz9T0mFaoyTD6UUHVft Qh/R2L9RzuRjGFthi0NmxHjZ8h0LQpIoRGFAsOMUiYETvScxQxb5Mwld6ZispScZFPSq S45cACxcuFMAuxm6cWwCHccmUNC4GgGC2rymQMR6xbfSD7FSBVsAHlgRxYnLUiu49vdz 65Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=T2d6RVLzyzWzf/spKdraeHdOh9Hi3cYnCCfjXRwnKAY=; b=e8gaGXuCcDJ6oKBeFgYNMuLaBo5jVeLuDIAx5l2cPc7ZRrrUaRxpWqKz4eJ7p1rDPE yM+ha8RKR3hRJoH1WcpzWBLHezKwgYik2tZJOJ7elfYqnnNKFeqNR03AS4F6I4enzaAf 3zlzdk/0wI4WHy9Yoeffn19iSEsWz2VQhdI6H9tvxWf7CM/foy5cYLZOW2d87hy3D1ce DiIybKVv+0EQO5L3A9n1Ahi1YkTYUXdgWRPt1i4gfdkQN0rb+e/l/CzRpFBkLTbbEbTU tagwObCoFz21A+KWWTaG71uyv0cnTj29kH7U7x2i1g6SSj4xEI+2+VVbbINyUUycgzKh hFKg== X-Gm-Message-State: ACgBeo3t+hjW5Scr0LGGDUUIvcQcS0JqPw2Cl0PNZ+kSj6GXQVvnpbHr sF8NWrNLdmK+l7SZAUvyO7LUUmyXzmdHTA== X-Google-Smtp-Source: AA6agR6NF44+rgUN0Tz/yLqC4Ug1rH/DrRZlDv/yjeOMdf6pVjSp8KFb2MdGEirQdcBvOUTP200jNg== X-Received: by 2002:a05:6000:1549:b0:220:7199:bd4 with SMTP id 9-20020a056000154900b0022071990bd4mr4157147wry.673.1660906858347; Fri, 19 Aug 2022 04:00:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/6] target/arm: Advertise FEAT_ETS for '-cpu max' Date: Fri, 19 Aug 2022 12:00:51 +0100 Message-Id: <20220819110052.2942289-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819110052.2942289-1-peter.maydell@linaro.org> References: <20220819110052.2942289-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660907817567100001 The architectural feature FEAT_ETS (Enhanced Translation Synchronization) is a set of tightened guarantees about memory ordering involving translation table walks: * if memory access RW1 is ordered-before memory access RW2 then it is also ordered-before any translation table walk generated by RW2 that generates a translation fault, address size fault or access fault * TLB maintenance on non-exec-permission translations is guaranteed complete after a DSB (ie it does not need the context synchronization event that you have to have if you don=E2=80=99t have FEAT_ETS) For QEMU=E2=80=99s implementation we don=E2=80=99t reorder translation tabl= e walk accesses, and we guarantee to finish the TLB maintenance as soon as the TLB op is done (the tlb_flush functions will complete at the end of the TLB, and TLB ops always end the TB because they=E2=80=99re sysreg writes). So we=E2=80=99re already compliant and all we need to do is say so in the ID registers for the 'max' CPU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8e494c8bea5..811358fd0a0 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) +- FEAT_ETS (Enhanced Translation Synchronization) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP16 (Half-precision floating-point data processing) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 78e27f778ac..6d65248f29c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1043,6 +1043,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ cpu->isar.id_aa64mmfr1 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3099b38e32b..f63f8cdd954 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -67,6 +67,10 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; =20 + t =3D cpu->isar.id_mmfr5; + t =3D FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */ + cpu->isar.id_mmfr5 =3D t; + t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ --=20 2.25.1 From nobody Sat May 4 07:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1660907842; cv=none; d=zohomail.com; s=zohoarc; b=Kzr3R/ga20FohoSKtOGOpaAg6PKX3J9Y825npPMAvPc9KsKwTvpuyhf011Q8sWUzrJ7Hnyl9X5yo6d35HRt2cQqpbO7ezGtZfHsvgAxmEFGsYk3bSbY+Wc1MWUiKFaaQBCzlztMvUfVB8mO2NeACniCTvHSPil1GUj4nyVEnosc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660907842; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uhwJFdO0H01eXY5Lyz7NeMke3RGgO/dYgfglq68Auzw=; b=DXz2wva4Z6c6occMz0j+9Fsv63WWZw1bpxclpg92NEG+yU7mqkXbQn5TUUCBlb/HAHk7I9yH+wVKsTjJDNSuLDVCy9A6tadzE1uw5+tU/TFfEk47hADwgpFhEr4gru/VQ/OFGSE0S13fthMEGwC6LQNwr+A2kG7wGnOr1C6c4uU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660907842074620.1902842568358; Fri, 19 Aug 2022 04:17:22 -0700 (PDT) Received: from localhost ([::1]:39608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oP008-0003Jz-O8 for importer@patchew.org; Fri, 19 Aug 2022 07:17:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oOzkQ-0002Dm-61 for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:09 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:38656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oOzkK-0001R2-D6 for qemu-devel@nongnu.org; Fri, 19 Aug 2022 07:01:05 -0400 Received: by mail-wr1-x42b.google.com with SMTP id b5so485118wrr.5 for ; Fri, 19 Aug 2022 04:00:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=uhwJFdO0H01eXY5Lyz7NeMke3RGgO/dYgfglq68Auzw=; b=p27WeET1DkKXn2Bq+I2168oF6apMA9lHbKtx3bWHy6TRh73UzFg5iVi6VQr/Fu6twg HgS13tHxpG93O/QOPYrffE7GA8P6iLp7Umrp0kKqY7PA653fJI+DAfVTfxIu7jfIqmBV GTS1UMZDDpji1DAkKQpGdf3OZ7y/rJZ96dQ6XLPGtWfw58Wbha+u6Qjw285F90/hNDxS 2vIF2JnD7j62xTXLjF6ZE5SM6cb7ONY24WtIz1eWjUqOebrT2fiHCt69RLW4iWO3/wqC 6Iew9xd04A7QdJF7AJufNOoPpk1ig5zx/Otmr1fAz8KP3scU7govT1jPQ0cIjIKvQN3z 8XNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=uhwJFdO0H01eXY5Lyz7NeMke3RGgO/dYgfglq68Auzw=; b=67IEEZLVXC70us0g4iJi36GqLpF0xjv3SxHqdkNTbWkmTcU0cWlyoU7YSY+KLZhEf6 4rM1cTugzDzyeQ3bXdC9bggZl1Whm5S8vMX2APFFdArsqH1oKNoAqB1r8HE7ZBvx2PMj vh9OKLlxvwwV9pTroCh9JB9SBwvjt6Tes5W50PEFe4ssbzs5q3vjeYWmmVHAsNheCM3l 7CZG2w8QKYd6mprhvKPBGMHQtRhXSwnxlB3hNnrfH2j97LQJewtts19GkGY1t55KfH7M rDZYdAsa+sQRD911iRpX9VABPR9aiKq1LBS8g9Rc2TOIUUxuy7d121ArdKMhutG9m/15 p8Uw== X-Gm-Message-State: ACgBeo1RItR8ZTOqH6JEbimWDNDMevMU0Mtkj/cwxDEikSpVDAl7azKG OrYfdE4GbifeC9wmTUlAzGltrw== X-Google-Smtp-Source: AA6agR4I2ef4SmeWkX9m31eW9Maxyy2H7Ek/cUIHm0wkyfNKobm8NEA3hwKYKhPejaiG5rj/qgCncg== X-Received: by 2002:a5d:5a82:0:b0:224:f744:1799 with SMTP id bp2-20020a5d5a82000000b00224f7441799mr3839724wrb.582.1660906859067; Fri, 19 Aug 2022 04:00:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/6] target/arm: Add missing space in comment Date: Fri, 19 Aug 2022 12:00:52 +0100 Message-Id: <20220819110052.2942289-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220819110052.2942289-1-peter.maydell@linaro.org> References: <20220819110052.2942289-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660907843570100001 Content-Type: text/plain; charset="utf-8" Fix a missing space before a comment terminator. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f63f8cdd954..b714c61d940 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -64,7 +64,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_mmfr5; --=20 2.25.1