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([2605:ef80:80f6:61fa:9bc2:5095:d612:5e22]) by smtp.gmail.com with ESMTPSA id y23-20020a056870b01700b0010ef8ccde67sm2285220oae.13.2022.08.16.13.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 13:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=xEQZVGp1RTivKylQ7UGFI7xtIFjejFxCKqT/C8jhtT8=; b=I/QRPeixV/YsGiUDTxHgbEPGCapQKXw22SwyZ3PhaLRx3tC8tL/HjXUM27ObZCieHR /AZn0zCWGMgjXS3hhTXt9ILqTY+UswzOOnYqnI28kdPFc6i525oEO/H9UQlo8VrT4KJD gtb3cF/YxQq2TqZ9zhXTNNKkhk3NIdaOFitg/G7qZDi9Ibmi2p3IautyaOxVMbz3nmP5 ve2Fc1rApuH2XKqrCt5aJOsHWx04UUV2YELnfU68M+a4mQ0sg6mbIdFXG6q6GyG9v+kT ROZTybRB/jRWn2WdEu80kP9HPyjKl5J9li5V0TRFLq50RvfudFlbg5DZEWTo1EtR1wQN G6ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=xEQZVGp1RTivKylQ7UGFI7xtIFjejFxCKqT/C8jhtT8=; b=dLH+9Yfb+5z8mrWeXtI3CDjyoc+p31LKFZCQLaj3hGg4bLyp/dYTq8sttvWQCWmG8k CofsL7m2FpVqkeq2Dsw+4dxC7sVY2p9eYTJnJFXyr94yich8xvGVrLd3PYnIoHiO9H0x 8ZOWUv5TJsg4qGzSfHv9GkvyIcA9BEXlzCK4PDxR9SeBclnSt/PMqTNdWKyhi+oNL9lG CsE7pyNzRNuqtOxO9y+jYmo8ri8fv+4NoIOQ9x9+r/pLqsCDThVaFv7bxpOtoEoNARcu YwwTa/bEp+ibSU1aPnlykzUvjBitd32bZ3YBWfztq/moERbb9I8mKf8UuV8mebZzNb1I iGLQ== X-Gm-Message-State: ACgBeo1L1jBpfQbPNxbbYKDlJ5z7rp1xQSKPBxZq+jsVPOWW3jaT9FPK nEXNwwzUz5jrxu6niEN4OS8qqDfVLSl42w== X-Google-Smtp-Source: AA6agR54psQ9YjiiSxiGldX/ePdcL0bkcVlvtJfWEsDJhNyFkYzf5fksTmHv4bNxHp1FBFGXCRE6YQ== X-Received: by 2002:a05:6830:1be4:b0:636:d697:42e8 with SMTP id k4-20020a0568301be400b00636d69742e8mr8481978otb.248.1660682094105; Tue, 16 Aug 2022 13:34:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, alex.bennee@linaro.org, iii@linux.ibm.com Subject: [PATCH v2 23/33] accel/tcg: Introduce TARGET_TB_PCREL Date: Tue, 16 Aug 2022 15:33:50 -0500 Message-Id: <20220816203400.161187-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220816203400.161187-1-richard.henderson@linaro.org> References: <20220816203400.161187-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660683129503100001 Content-Type: text/plain; charset="utf-8" Prepare for targets to be able to produce TBs that can run in more than one virtual context. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ include/exec/exec-all.h | 41 ++++++++++++++++++++++++++--- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 55 ++++++++++++++++++++++++++++++--------- accel/tcg/translate-all.c | 48 ++++++++++++++++++++++------------ 5 files changed, 115 insertions(+), 33 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..87e2bc4e59 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -54,6 +54,9 @@ # error TARGET_PAGE_BITS must be defined in cpu-param.h # endif #endif +#ifndef TARGET_TB_PCREL +# define TARGET_TB_PCREL 0 +#endif =20 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cec3ef1666..b41835bb55 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -459,8 +459,32 @@ struct tb_tc { }; =20 struct TranslationBlock { - target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ - target_ulong cs_base; /* CS base for this block */ +#if !TARGET_TB_PCREL + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are + * written such that the TB is associated only with the physical + * page and may be run in any virtual address context. In this case, + * PC must always be taken from ENV in a target-specific manner. + * Unwind information is taken as byte offsets from the "current" + * value of the PC, as tracked by the translator. + */ + target_ulong pc; +#endif + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + target_ulong cs_base; + uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ =20 @@ -536,13 +560,24 @@ struct TranslationBlock { /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ static inline target_ulong tb_pc(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + qemu_build_not_reached(); +#else return tb->pc; +#endif } =20 -/* Similarly, but for logs. */ +/* + * Similarly, but for logs. In this case, when the virtual pc + * is not available, use the physical address. + */ static inline target_ulong tb_pc_log(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + return tb->page_addr[0]; +#else return tb->pc; +#endif } =20 /* Hide the qatomic_read to make code a little easier on the eyes */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8edef14199..7dcfccf6e2 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -235,6 +235,7 @@ struct hvf_vcpu_state; =20 typedef struct { TranslationBlock *tb; + vaddr pc; } CPUJumpCache; =20 /* work queue */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f146960b7b..f7c82a8f2c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -185,7 +185,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if (tb_pc(tb) =3D=3D desc->pc && + if ((TARGET_TB_PCREL || tb_pc(tb) =3D=3D desc->pc) && tb->page_addr[0] =3D=3D desc->page_addr0 && tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && @@ -227,7 +227,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, return NULL; } desc.page_addr0 =3D phys_pc; - h =3D tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc), + flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } =20 @@ -243,21 +244,42 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); =20 hash =3D tb_jmp_cache_hash_func(pc); - tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); - - if (likely(tb && - tb->pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - tb_cflags(tb) =3D=3D cflags)) { - return tb; + if (TARGET_TB_PCREL) { + /* Use acquire to ensure current load of pc from tb_jmp_cache[]. */ + tb =3D qatomic_load_acquire(&cpu->tb_jmp_cache[hash].tb); + } else { + /* Use rcu_read to ensure current load of pc from *tb. */ + tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); } + if (likely(tb)) { + target_ulong jmp_pc; + + if (TARGET_TB_PCREL) { + jmp_pc =3D qatomic_read(&cpu->tb_jmp_cache[hash].pc); + } else { + jmp_pc =3D tb_pc(tb); + } + if (jmp_pc =3D=3D pc && + tb->cs_base =3D=3D cs_base && + tb->flags =3D=3D flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && + tb_cflags(tb) =3D=3D cflags) { + return tb; + } + } + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); + + if (TARGET_TB_PCREL) { + /* Use store_release on tb to ensure pc is current. */ + qatomic_set(&cpu->tb_jmp_cache[hash].pc, pc); + qatomic_store_release(&cpu->tb_jmp_cache[hash].tb, tb); + } else { + qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); + } return tb; } =20 @@ -445,6 +467,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { + assert(!TARGET_TB_PCREL); assert(cc->set_pc); cc->set_pc(cpu, tb_pc(last_tb)); } @@ -988,7 +1011,13 @@ int cpu_exec(CPUState *cpu) * for the fast lookup */ h =3D tb_jmp_cache_hash_func(pc); - qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); + if (TARGET_TB_PCREL) { + /* Use store_release on tb to ensure pc is current. */ + qatomic_set(&cpu->tb_jmp_cache[h].pc, pc); + qatomic_store_release(&cpu->tb_jmp_cache[h].tb, tb); + } else { + qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 1248ee3433..27435b97db 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -298,7 +298,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { - prev =3D (j =3D=3D 0 ? tb_pc(tb) : 0); + prev =3D (!TARGET_TB_PCREL && j =3D=3D 0 ? tb_pc(tb) : 0); } else { prev =3D tcg_ctx->gen_insn_data[i - 1][j]; } @@ -326,7 +326,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_ico= unt) { - target_ulong data[TARGET_INSN_START_WORDS] =3D { tb_pc(tb) }; + target_ulong data[TARGET_INSN_START_WORDS]; uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; const uint8_t *p =3D tb->tc.ptr + tb->tc.size; @@ -342,6 +342,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tr= anslationBlock *tb, return -1; } =20 + memset(data, 0, sizeof(data)); + if (!TARGET_TB_PCREL) { + data[0] =3D tb_pc(tb); + } + /* Reconstruct the stored insn data while looking for the point at which the end of the insn exceeds the searched_pc. */ for (i =3D 0; i < num_insns; ++i) { @@ -884,13 +889,13 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a =3D ap; const TranslationBlock *b =3D bp; =20 - return tb_pc(a) =3D=3D tb_pc(b) && - a->cs_base =3D=3D b->cs_base && - a->flags =3D=3D b->flags && - (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALID) && - a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && - a->page_addr[0] =3D=3D b->page_addr[0] && - a->page_addr[1] =3D=3D b->page_addr[1]; + return ((TARGET_TB_PCREL || tb_pc(a) =3D=3D tb_pc(b)) && + a->cs_base =3D=3D b->cs_base && + a->flags =3D=3D b->flags && + (tb_cflags(a) & ~CF_INVALID) =3D=3D (tb_cflags(b) & ~CF_INVALI= D) && + a->trace_vcpu_dstate =3D=3D b->trace_vcpu_dstate && + a->page_addr[0] =3D=3D b->page_addr[0] && + a->page_addr[1] =3D=3D b->page_addr[1]); } =20 void tb_htable_init(void) @@ -1169,8 +1174,8 @@ static void do_tb_phys_invalidate(TranslationBlock *t= b, bool rm_from_page_list) =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0]; - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; } @@ -1186,10 +1191,17 @@ static void do_tb_phys_invalidate(TranslationBlock = *tb, bool rm_from_page_list) } =20 /* remove the TB from the hash list */ - h =3D tb_jmp_cache_hash_func(tb->pc); - CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h].tb) =3D=3D tb) { - qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); + if (TARGET_TB_PCREL) { + /* Any TB may be at any virtual address */ + CPU_FOREACH(cpu) { + cpu_tb_jmp_cache_clear(cpu); + } + } else { + h =3D tb_jmp_cache_hash_func(tb_pc(tb)); + CPU_FOREACH(cpu) { + if (qatomic_read(&cpu->tb_jmp_cache[h].tb) =3D=3D tb) { + qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); + } } } =20 @@ -1300,8 +1312,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phy= s_pc, } =20 /* add in the hash table */ - h =3D tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, - tb->trace_vcpu_dstate); + h =3D tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); =20 /* remove TB from the page(s) if we couldn't insert it */ @@ -1371,7 +1383,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D tcg_splitwx_to_rx(gen_code_buf); +#if !TARGET_TB_PCREL tb->pc =3D pc; +#endif tb->cs_base =3D cs_base; tb->flags =3D flags; tb->cflags =3D cflags; --=20 2.34.1