From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581119859361.9062045556443; Mon, 15 Aug 2022 09:31:59 -0700 (PDT) Received: from localhost ([::1]:43784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNd0P-00089K-Jb for importer@patchew.org; Mon, 15 Aug 2022 12:31:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcpi-0007CJ-Um; Mon, 15 Aug 2022 12:21:00 -0400 Received: from [200.168.210.66] (port=25068 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcpg-0005gw-8j; Mon, 15 Aug 2022 12:20:54 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 4FC8380046B; Mon, 15 Aug 2022 13:20:43 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 01/13] target/ppc: define PPC_INTERRUPT_* values directly Date: Mon, 15 Aug 2022 13:20:07 -0300 Message-Id: <20220815162020.2420093-2-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:43.0561 (UTC) FILETIME=[F7D69990:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581121597100001 Content-Type: text/plain; charset="utf-8" This enum defines the bit positions in env->pending_interrupts for each interrupt. However, except for the comparison in kvmppc_set_interrupt, the values are always used as (1 << PPC_INTERRUPT_*). Define them directly like that to save some clutter. No functional change intended. Signed-off-by: Matheus Ferst Reviewed-by: David Gibson --- hw/ppc/ppc.c | 10 +++--- hw/ppc/trace-events | 2 +- target/ppc/cpu.h | 40 +++++++++++----------- target/ppc/cpu_init.c | 56 +++++++++++++++--------------- target/ppc/excp_helper.c | 74 ++++++++++++++++++++-------------------- target/ppc/misc_helper.c | 6 ++-- 6 files changed, 94 insertions(+), 94 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 690f448cb9..77e611e81c 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -40,7 +40,7 @@ static void cpu_ppc_tb_stop (CPUPPCState *env); static void cpu_ppc_tb_start (CPUPPCState *env); =20 -void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) +void ppc_set_irq(PowerPCCPU *cpu, int irq, int level) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; @@ -56,21 +56,21 @@ void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) old_pending =3D env->pending_interrupts; =20 if (level) { - env->pending_interrupts |=3D 1 << n_IRQ; + env->pending_interrupts |=3D irq; cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { - env->pending_interrupts &=3D ~(1 << n_IRQ); + env->pending_interrupts &=3D ~irq; if (env->pending_interrupts =3D=3D 0) { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } } =20 if (old_pending !=3D env->pending_interrupts) { - kvmppc_set_interrupt(cpu, n_IRQ, level); + kvmppc_set_interrupt(cpu, irq, level); } =20 =20 - trace_ppc_irq_set_exit(env, n_IRQ, level, env->pending_interrupts, + trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts, CPU(cpu)->interrupt_request); =20 if (locked) { diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 5c0a215cad..c9ee1285b8 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -116,7 +116,7 @@ ppc40x_set_tb_clk(uint32_t value) "new frequency %" PRI= u32 ppc40x_timers_init(uint32_t value) "frequency %" PRIu32 =20 ppc_irq_set(void *env, uint32_t pin, uint32_t level) "env [%p] pin %d leve= l %d" -ppc_irq_set_exit(void *env, uint32_t n_IRQ, uint32_t level, uint32_t pendi= ng, uint32_t request) "env [%p] n_IRQ %d level %d =3D> pending 0x%08" PRIx3= 2 " req 0x%08" PRIx32 +ppc_irq_set_exit(void *env, uint32_t irq, uint32_t level, uint32_t pending= , uint32_t request) "env [%p] irq 0x%05" PRIx32 " level %d =3D> pending 0x%= 08" PRIx32 " req 0x%08" PRIx32 ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d" ppc_irq_reset(const char *name) "%s" ppc_irq_cpu(const char *action) "%s" diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a4c893cfad..c7864bb3b1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2418,27 +2418,27 @@ enum { /* Hardware exceptions definitions */ enum { /* External hardware exception sources */ - PPC_INTERRUPT_RESET =3D 0, /* Reset exception = */ - PPC_INTERRUPT_WAKEUP, /* Wakeup exception = */ - PPC_INTERRUPT_MCK, /* Machine check exception = */ - PPC_INTERRUPT_EXT, /* External interrupt = */ - PPC_INTERRUPT_SMI, /* System management interrupt = */ - PPC_INTERRUPT_CEXT, /* Critical external interrupt = */ - PPC_INTERRUPT_DEBUG, /* External debug exception = */ - PPC_INTERRUPT_THERM, /* Thermal exception = */ + PPC_INTERRUPT_RESET =3D 0x00001, /* Reset exception = */ + PPC_INTERRUPT_WAKEUP =3D 0x00002, /* Wakeup exception = */ + PPC_INTERRUPT_MCK =3D 0x00004, /* Machine check exception = */ + PPC_INTERRUPT_EXT =3D 0x00008, /* External interrupt = */ + PPC_INTERRUPT_SMI =3D 0x00010, /* System management interrupt = */ + PPC_INTERRUPT_CEXT =3D 0x00020, /* Critical external interrupt = */ + PPC_INTERRUPT_DEBUG =3D 0x00040, /* External debug exception = */ + PPC_INTERRUPT_THERM =3D 0x00080, /* Thermal exception = */ /* Internal hardware exception sources */ - PPC_INTERRUPT_DECR, /* Decrementer exception = */ - PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception = */ - PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt= */ - PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt = */ - PPC_INTERRUPT_WDT, /* Watchdog timer interrupt = */ - PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt = */ - PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt = */ - PPC_INTERRUPT_PERFM, /* Performance monitor interrupt = */ - PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ - PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ - PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ - PPC_INTERRUPT_EBB, /* Event-based Branch exception = */ + PPC_INTERRUPT_DECR =3D 0x00100, /* Decrementer exception = */ + PPC_INTERRUPT_HDECR =3D 0x00200, /* Hypervisor decrementer excepti= on */ + PPC_INTERRUPT_PIT =3D 0x00400, /* Programmable interval timer in= t. */ + PPC_INTERRUPT_FIT =3D 0x00800, /* Fixed interval timer interrupt= */ + PPC_INTERRUPT_WDT =3D 0x01000, /* Watchdog timer interrupt = */ + PPC_INTERRUPT_CDOORBELL =3D 0x02000, /* Critical doorbell interrupt = */ + PPC_INTERRUPT_DOORBELL =3D 0x04000, /* Doorbell interrupt = */ + PPC_INTERRUPT_PERFM =3D 0x08000, /* Performance monitor interrupt = */ + PPC_INTERRUPT_HMI =3D 0x10000, /* Hypervisor Maintenance interru= pt */ + PPC_INTERRUPT_HDOORBELL =3D 0x20000, /* Hypervisor Doorbell interrupt = */ + PPC_INTERRUPT_HVIRT =3D 0x40000, /* Hypervisor virtualization inte= rrupt */ + PPC_INTERRUPT_EBB =3D 0x80000, /* Event-based Branch exception = */ }; =20 /* Processor Compatibility mask (PCR) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d1493a660c..850334545a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5932,23 +5932,23 @@ static bool cpu_has_work_POWER7(CPUState *cs) if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && + if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { return true; } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { return true; } return false; @@ -6096,31 +6096,31 @@ static bool cpu_has_work_POWER8(CPUState *cs) if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && + if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { return true; } - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { return true; } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { return true; } return false; @@ -6307,7 +6307,7 @@ static bool cpu_has_work_POWER9(CPUState *cs) return true; } /* External Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && (env->spr[SPR_LPCR] & LPCR_EEE)) { bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); if (!heic || !FIELD_EX64_HV(env->msr) || @@ -6316,31 +6316,31 @@ static bool cpu_has_work_POWER9(CPUState *cs) } } /* Decrementer Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && (env->spr[SPR_LPCR] & LPCR_DEE)) { return true; } /* Machine Check or Hypervisor Maintenance Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | - 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + if ((env->pending_interrupts & (PPC_INTERRUPT_MCK | PPC_INTERRUPT_= HMI)) + && (env->spr[SPR_LPCR] & LPCR_OEE)) { return true; } /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && (env->spr[SPR_LPCR] & LPCR_PDEE)) { return true; } /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && (env->spr[SPR_LPCR] & LPCR_HDEE)) { return true; } /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && (env->spr[SPR_LPCR] & LPCR_HVEE)) { return true; } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { return true; } return false; @@ -6524,7 +6524,7 @@ static bool cpu_has_work_POWER10(CPUState *cs) return true; } /* External Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && (env->spr[SPR_LPCR] & LPCR_EEE)) { bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); if (!heic || !FIELD_EX64_HV(env->msr) || @@ -6533,31 +6533,31 @@ static bool cpu_has_work_POWER10(CPUState *cs) } } /* Decrementer Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && (env->spr[SPR_LPCR] & LPCR_DEE)) { return true; } /* Machine Check or Hypervisor Maintenance Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | - 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { + if ((env->pending_interrupts & (PPC_INTERRUPT_MCK | PPC_INTERRUPT_= HMI)) + && (env->spr[SPR_LPCR] & LPCR_OEE)) { return true; } /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && + if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && (env->spr[SPR_LPCR] & LPCR_PDEE)) { return true; } /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && (env->spr[SPR_LPCR] & LPCR_HDEE)) { return true; } /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && + if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && (env->spr[SPR_LPCR] & LPCR_HVEE)) { return true; } - if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { return true; } return false; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7550aafed6..b9476b5d03 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1683,21 +1683,21 @@ static void ppc_hw_interrupt(CPUPPCState *env) bool async_deliver; =20 /* External reset */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_RESET); + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_RESET; powerpc_excp(cpu, POWERPC_EXCP_RESET); return; } /* Machine check exception */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_MCK); + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_MCK; powerpc_excp(cpu, POWERPC_EXCP_MCHECK); return; } #if 0 /* TODO */ /* External debug exception */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DEBUG); + if (env->pending_interrupts & PPC_INTERRUPT_DEBUG) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_DEBUG; powerpc_excp(cpu, POWERPC_EXCP_DEBUG); return; } @@ -1712,19 +1712,19 @@ static void ppc_hw_interrupt(CPUPPCState *env) async_deliver =3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sres= et; =20 /* Hypervisor decrementer exception */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { + if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_HDECR); + env->pending_interrupts &=3D ~PPC_INTERRUPT_HDECR; powerpc_excp(cpu, POWERPC_EXCP_HDECR); return; } } =20 /* Hypervisor virtualization interrupt */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) { + if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { /* LPCR will be clear when not supported so this will work */ bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { @@ -1734,7 +1734,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) } =20 /* External interrupt can ignore MSR:EE under some circumstances */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { + if (env->pending_interrupts & PPC_INTERRUPT_EXT) { bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ @@ -1751,45 +1751,45 @@ static void ppc_hw_interrupt(CPUPPCState *env) } if (FIELD_EX64(env->msr, MSR, CE)) { /* External critical interrupt */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { + if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { powerpc_excp(cpu, POWERPC_EXCP_CRITICAL); return; } } if (async_deliver !=3D 0) { /* Watchdog timer on embedded PowerPC */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_WDT); + if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_WDT; powerpc_excp(cpu, POWERPC_EXCP_WDT); return; } - if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_CDOORBELL); + if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_CDOORBELL; powerpc_excp(cpu, POWERPC_EXCP_DOORCI); return; } /* Fixed interval timer on embedded PowerPC */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_FIT); + if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_FIT; powerpc_excp(cpu, POWERPC_EXCP_FIT); return; } /* Programmable interval timer on embedded PowerPC */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_PIT); + if (env->pending_interrupts & PPC_INTERRUPT_PIT) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_PIT; powerpc_excp(cpu, POWERPC_EXCP_PIT); return; } /* Decrementer exception */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { + if (env->pending_interrupts & PPC_INTERRUPT_DECR) { if (ppc_decr_clear_on_delivery(env)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DECR); + env->pending_interrupts &=3D ~PPC_INTERRUPT_DECR; } powerpc_excp(cpu, POWERPC_EXCP_DECR); return; } - if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DOORBELL); + if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; if (is_book3s_arch2x(env)) { powerpc_excp(cpu, POWERPC_EXCP_SDOOR); } else { @@ -1797,31 +1797,31 @@ static void ppc_hw_interrupt(CPUPPCState *env) } return; } - if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_HDOORBELL); + if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_HDOORBELL; powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); return; } - if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_PERFM); + if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_PERFM; powerpc_excp(cpu, POWERPC_EXCP_PERFM); return; } /* Thermal interrupt */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_THERM); + if (env->pending_interrupts & PPC_INTERRUPT_THERM) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_THERM; powerpc_excp(cpu, POWERPC_EXCP_THERM); return; } /* EBB exception */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) { + if (env->pending_interrupts & PPC_INTERRUPT_EBB) { /* * EBB exception must be taken in problem state and * with BESCR_GE set. */ if (FIELD_EX64(env->msr, MSR, PR) && (env->spr[SPR_BESCR] & BESCR_GE)) { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_EBB); + env->pending_interrupts &=3D ~PPC_INTERRUPT_EBB; =20 if (env->spr[SPR_BESCR] & BESCR_PMEO) { powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); @@ -2098,7 +2098,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp) if (FIELD_EX64(env->msr, MSR, PR)) { powerpc_excp(cpu, ebb_excp); } else { - env->pending_interrupts |=3D 1 << PPC_INTERRUPT_EBB; + env->pending_interrupts |=3D PPC_INTERRUPT_EBB; cpu_interrupt(cs, CPU_INTERRUPT_HARD); } } @@ -2209,7 +2209,7 @@ void helper_msgclr(CPUPPCState *env, target_ulong rb) return; } =20 - env->pending_interrupts &=3D ~(1 << irq); + env->pending_interrupts &=3D ~irq; } =20 void helper_msgsnd(target_ulong rb) @@ -2228,7 +2228,7 @@ void helper_msgsnd(target_ulong rb) CPUPPCState *cenv =3D &cpu->env; =20 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] =3D=3D pir))= { - cenv->pending_interrupts |=3D 1 << irq; + cenv->pending_interrupts |=3D irq; cpu_interrupt(cs, CPU_INTERRUPT_HARD); } } @@ -2253,7 +2253,7 @@ void helper_book3s_msgclr(CPUPPCState *env, target_ul= ong rb) return; } =20 - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_HDOORBELL); + env->pending_interrupts &=3D ~PPC_INTERRUPT_HDOORBELL; } =20 static void book3s_msgsnd_common(int pir, int irq) @@ -2267,7 +2267,7 @@ static void book3s_msgsnd_common(int pir, int irq) =20 /* TODO: broadcast message to all threads of the same processor */ if (cenv->spr_cb[SPR_PIR].default_value =3D=3D pir) { - cenv->pending_interrupts |=3D 1 << irq; + cenv->pending_interrupts |=3D irq; cpu_interrupt(cs, CPU_INTERRUPT_HARD); } } @@ -2294,7 +2294,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_u= long rb) return; } =20 - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DOORBELL); + env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; } =20 /* diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index b0a5e7ce76..05e35572bc 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -163,7 +163,7 @@ target_ulong helper_load_dpdes(CPUPPCState *env) helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MS= GP); =20 /* TODO: TCG supports only one thread */ - if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { + if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { dpdes =3D 1; } =20 @@ -185,10 +185,10 @@ void helper_store_dpdes(CPUPPCState *env, target_ulon= g val) } =20 if (val & 0x1) { - env->pending_interrupts |=3D 1 << PPC_INTERRUPT_DOORBELL; + env->pending_interrupts |=3D PPC_INTERRUPT_DOORBELL; cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { - env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_DOORBELL); + env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; } } #endif /* defined(TARGET_PPC64) */ --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660580904266707.5712526126517; Mon, 15 Aug 2022 09:28:24 -0700 (PDT) Received: from localhost ([::1]:57424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcwx-00052E-82 for importer@patchew.org; Mon, 15 Aug 2022 12:28:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcpo-0007CY-HR; Mon, 15 Aug 2022 12:21:00 -0400 Received: from [200.168.210.66] (port=25068 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcpk-0005gw-0u; Mon, 15 Aug 2022 12:20:57 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 80E6D800186; Mon, 15 Aug 2022 13:20:43 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 02/13] target/ppc: always use ppc_set_irq to set env->pending_interrupts Date: Mon, 15 Aug 2022 13:20:08 -0300 Message-Id: <20220815162020.2420093-3-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:43.0748 (UTC) FILETIME=[F7F32240:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660580906897100001 Content-Type: text/plain; charset="utf-8" Use ppc_set_irq to raise/clear interrupts to ensure CPU_INTERRUPT_HARD will be set/reset accordingly. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 17 +++++++---------- target/ppc/misc_helper.c | 9 ++------- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b9476b5d03..ae9576546f 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "internal.h" #include "helper_regs.h" +#include "hw/ppc/ppc.h" =20 #include "trace.h" =20 @@ -2080,7 +2081,6 @@ void helper_rfebb(CPUPPCState *env, target_ulong s) static void do_ebb(CPUPPCState *env, int ebb_excp) { PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); =20 /* * FSCR_EBB and FSCR_IC_EBB are the same bits used with @@ -2098,8 +2098,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp) if (FIELD_EX64(env->msr, MSR, PR)) { powerpc_excp(cpu, ebb_excp); } else { - env->pending_interrupts |=3D PPC_INTERRUPT_EBB; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + ppc_set_irq(cpu, PPC_INTERRUPT_EBB, 1); } } =20 @@ -2209,7 +2208,7 @@ void helper_msgclr(CPUPPCState *env, target_ulong rb) return; } =20 - env->pending_interrupts &=3D ~irq; + ppc_set_irq(env_archcpu(env), irq, 0); } =20 void helper_msgsnd(target_ulong rb) @@ -2228,8 +2227,7 @@ void helper_msgsnd(target_ulong rb) CPUPPCState *cenv =3D &cpu->env; =20 if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] =3D=3D pir))= { - cenv->pending_interrupts |=3D irq; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + ppc_set_irq(cpu, irq, 1); } } qemu_mutex_unlock_iothread(); @@ -2253,7 +2251,7 @@ void helper_book3s_msgclr(CPUPPCState *env, target_ul= ong rb) return; } =20 - env->pending_interrupts &=3D ~PPC_INTERRUPT_HDOORBELL; + ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0); } =20 static void book3s_msgsnd_common(int pir, int irq) @@ -2267,8 +2265,7 @@ static void book3s_msgsnd_common(int pir, int irq) =20 /* TODO: broadcast message to all threads of the same processor */ if (cenv->spr_cb[SPR_PIR].default_value =3D=3D pir) { - cenv->pending_interrupts |=3D irq; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + ppc_set_irq(cpu, irq, 1); } } qemu_mutex_unlock_iothread(); @@ -2294,7 +2291,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_u= long rb) return; } =20 - env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; + ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0); } =20 /* diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 05e35572bc..a9bc1522e2 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -25,6 +25,7 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "mmu-book3s-v3.h" +#include "hw/ppc/ppc.h" =20 #include "helper_regs.h" =20 @@ -173,7 +174,6 @@ target_ulong helper_load_dpdes(CPUPPCState *env) void helper_store_dpdes(CPUPPCState *env, target_ulong val) { PowerPCCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); =20 helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_M= SGP); =20 @@ -184,12 +184,7 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong= val) return; } =20 - if (val & 0x1) { - env->pending_interrupts |=3D PPC_INTERRUPT_DOORBELL; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; - } + ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1); } #endif /* defined(TARGET_PPC64) */ =20 --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660580810631375.9293622002763; Mon, 15 Aug 2022 09:26:50 -0700 (PDT) Received: from localhost ([::1]:52608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcvR-0002Sv-EP for importer@patchew.org; Mon, 15 Aug 2022 12:26:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcpt-0007Il-19; Mon, 15 Aug 2022 12:21:05 -0400 Received: from [200.168.210.66] (port=25068 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcpr-0005gw-0M; Mon, 15 Aug 2022 12:21:04 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:43 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id A3F1080046B; Mon, 15 Aug 2022 13:20:43 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 03/13] target/ppc: move interrupt masking out of ppc_hw_interrupt Date: Mon, 15 Aug 2022 13:20:09 -0300 Message-Id: <20220815162020.2420093-4-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:43.0952 (UTC) FILETIME=[F8124300:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660580811767100001 Content-Type: text/plain; charset="utf-8" Move the interrupt masking logic to a new method, ppc_pending_interrupt, and only handle the interrupt processing in ppc_hw_interrupt. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 228 ++++++++++++++++++++++++--------------- 1 file changed, 141 insertions(+), 87 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index ae9576546f..8690017c70 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1678,29 +1678,22 @@ void ppc_cpu_do_interrupt(CPUState *cs) powerpc_excp(cpu, cs->exception_index); } =20 -static void ppc_hw_interrupt(CPUPPCState *env) +static int ppc_pending_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu =3D env_archcpu(env); bool async_deliver; =20 /* External reset */ if (env->pending_interrupts & PPC_INTERRUPT_RESET) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_RESET; - powerpc_excp(cpu, POWERPC_EXCP_RESET); - return; + return PPC_INTERRUPT_RESET; } /* Machine check exception */ if (env->pending_interrupts & PPC_INTERRUPT_MCK) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_MCK; - powerpc_excp(cpu, POWERPC_EXCP_MCHECK); - return; + return PPC_INTERRUPT_MCK; } #if 0 /* TODO */ /* External debug exception */ if (env->pending_interrupts & PPC_INTERRUPT_DEBUG) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_DEBUG; - powerpc_excp(cpu, POWERPC_EXCP_DEBUG); - return; + return PPC_INTERRUPT_DEBUG; } #endif =20 @@ -1718,9 +1711,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ - env->pending_interrupts &=3D ~PPC_INTERRUPT_HDECR; - powerpc_excp(cpu, POWERPC_EXCP_HDECR); - return; + return PPC_INTERRUPT_HDECR; } } =20 @@ -1729,8 +1720,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) /* LPCR will be clear when not supported so this will work */ bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { - powerpc_excp(cpu, POWERPC_EXCP_HVIRT); - return; + return PPC_INTERRUPT_HVIRT; } } =20 @@ -1742,77 +1732,47 @@ static void ppc_hw_interrupt(CPUPPCState *env) if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { - if (books_vhyp_promotes_external_to_hvirt(cpu)) { - powerpc_excp(cpu, POWERPC_EXCP_HVIRT); - } else { - powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); - } - return; + return PPC_INTERRUPT_EXT; } } if (FIELD_EX64(env->msr, MSR, CE)) { /* External critical interrupt */ if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { - powerpc_excp(cpu, POWERPC_EXCP_CRITICAL); - return; + return PPC_INTERRUPT_CEXT; } } if (async_deliver !=3D 0) { /* Watchdog timer on embedded PowerPC */ if (env->pending_interrupts & PPC_INTERRUPT_WDT) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_WDT; - powerpc_excp(cpu, POWERPC_EXCP_WDT); - return; + return PPC_INTERRUPT_WDT; } if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_CDOORBELL; - powerpc_excp(cpu, POWERPC_EXCP_DOORCI); - return; + return PPC_INTERRUPT_CDOORBELL; } /* Fixed interval timer on embedded PowerPC */ if (env->pending_interrupts & PPC_INTERRUPT_FIT) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_FIT; - powerpc_excp(cpu, POWERPC_EXCP_FIT); - return; + return PPC_INTERRUPT_FIT; } /* Programmable interval timer on embedded PowerPC */ if (env->pending_interrupts & PPC_INTERRUPT_PIT) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_PIT; - powerpc_excp(cpu, POWERPC_EXCP_PIT); - return; + return PPC_INTERRUPT_PIT; } /* Decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_DECR) { - if (ppc_decr_clear_on_delivery(env)) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_DECR; - } - powerpc_excp(cpu, POWERPC_EXCP_DECR); - return; + return PPC_INTERRUPT_DECR; } if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; - if (is_book3s_arch2x(env)) { - powerpc_excp(cpu, POWERPC_EXCP_SDOOR); - } else { - powerpc_excp(cpu, POWERPC_EXCP_DOORI); - } - return; + return PPC_INTERRUPT_DOORBELL; } if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_HDOORBELL; - powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); - return; + return PPC_INTERRUPT_HDOORBELL; } if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_PERFM; - powerpc_excp(cpu, POWERPC_EXCP_PERFM); - return; + return PPC_INTERRUPT_PERFM; } /* Thermal interrupt */ if (env->pending_interrupts & PPC_INTERRUPT_THERM) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_THERM; - powerpc_excp(cpu, POWERPC_EXCP_THERM); - return; + return PPC_INTERRUPT_THERM; } /* EBB exception */ if (env->pending_interrupts & PPC_INTERRUPT_EBB) { @@ -1822,33 +1782,104 @@ static void ppc_hw_interrupt(CPUPPCState *env) */ if (FIELD_EX64(env->msr, MSR, PR) && (env->spr[SPR_BESCR] & BESCR_GE)) { - env->pending_interrupts &=3D ~PPC_INTERRUPT_EBB; - - if (env->spr[SPR_BESCR] & BESCR_PMEO) { - powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); - } else if (env->spr[SPR_BESCR] & BESCR_EEO) { - powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); - } - - return; + return PPC_INTERRUPT_EBB; } } } =20 - if (env->resume_as_sreset) { - /* - * This is a bug ! It means that has_work took us out of halt with= out - * anything to deliver while in a PM state that requires getting - * out via a 0x100 - * - * This means we will incorrectly execute past the power management - * instruction instead of triggering a reset. - * - * It generally means a discrepancy between the wakeup conditions = in the - * processor has_work implementation and the logic in this functio= n. - */ - cpu_abort(env_cpu(env), - "Wakeup from PM state but interrupt Undelivered"); + return 0; +} + +static void ppc_hw_interrupt(CPUPPCState *env, int pending_interrupt) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + + switch (pending_interrupt) { + case PPC_INTERRUPT_RESET: /* External reset */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_RESET; + powerpc_excp(cpu, POWERPC_EXCP_RESET); + break; + case PPC_INTERRUPT_MCK: /* Machine check exception */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_MCK; + powerpc_excp(cpu, POWERPC_EXCP_MCHECK); + break; +#if 0 /* TODO */ + case PPC_INTERRUPT_DEBUG: /* External debug exception */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_DEBUG; + powerpc_excp(cpu, POWERPC_EXCP_DEBUG); + break; +#endif + + case PPC_INTERRUPT_HDECR: /* Hypervisor decrementer exception */ + /* HDEC clears on delivery */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_HDECR; + powerpc_excp(cpu, POWERPC_EXCP_HDECR); + break; + case PPC_INTERRUPT_HVIRT: /* Hypervisor virtualization interrupt */ + powerpc_excp(cpu, POWERPC_EXCP_HVIRT); + break; + + case PPC_INTERRUPT_EXT: + if (books_vhyp_promotes_external_to_hvirt(cpu)) { + powerpc_excp(cpu, POWERPC_EXCP_HVIRT); + } else { + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL); + } + break; + case PPC_INTERRUPT_CEXT: /* External critical interrupt */ + powerpc_excp(cpu, POWERPC_EXCP_CRITICAL); + break; + + case PPC_INTERRUPT_WDT: /* Watchdog timer on embedded PowerPC */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_WDT; + powerpc_excp(cpu, POWERPC_EXCP_WDT); + break; + case PPC_INTERRUPT_CDOORBELL: + env->pending_interrupts &=3D ~PPC_INTERRUPT_CDOORBELL; + powerpc_excp(cpu, POWERPC_EXCP_DOORCI); + break; + case PPC_INTERRUPT_FIT: /* Fixed interval timer on embedded PowerPC */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_FIT; + powerpc_excp(cpu, POWERPC_EXCP_FIT); + break; + case PPC_INTERRUPT_PIT: /* Programmable interval timer on embedded Pow= erPC */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_PIT; + powerpc_excp(cpu, POWERPC_EXCP_PIT); + break; + case PPC_INTERRUPT_DECR: /* Decrementer exception */ + if (ppc_decr_clear_on_delivery(env)) { + env->pending_interrupts &=3D ~PPC_INTERRUPT_DECR; + } + powerpc_excp(cpu, POWERPC_EXCP_DECR); + break; + case PPC_INTERRUPT_DOORBELL: + env->pending_interrupts &=3D ~PPC_INTERRUPT_DOORBELL; + if (is_book3s_arch2x(env)) { + powerpc_excp(cpu, POWERPC_EXCP_SDOOR); + } else { + powerpc_excp(cpu, POWERPC_EXCP_DOORI); + } + break; + case PPC_INTERRUPT_HDOORBELL: + env->pending_interrupts &=3D ~PPC_INTERRUPT_HDOORBELL; + powerpc_excp(cpu, POWERPC_EXCP_SDOOR_HV); + break; + case PPC_INTERRUPT_PERFM: + env->pending_interrupts &=3D ~PPC_INTERRUPT_PERFM; + powerpc_excp(cpu, POWERPC_EXCP_PERFM); + break; + case PPC_INTERRUPT_THERM: /* Thermal interrupt */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_THERM; + powerpc_excp(cpu, POWERPC_EXCP_THERM); + break; + case PPC_INTERRUPT_EBB: /* EBB exception */ + env->pending_interrupts &=3D ~PPC_INTERRUPT_EBB; + if (env->spr[SPR_BESCR] & BESCR_PMEO) { + powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); + } else if (env->spr[SPR_BESCR] & BESCR_EEO) { + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); + } + break; } } =20 @@ -1884,15 +1915,38 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; + int pending_interrupt; =20 - if (interrupt_request & CPU_INTERRUPT_HARD) { - ppc_hw_interrupt(env); - if (env->pending_interrupts =3D=3D 0) { - cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; - } - return true; + if ((interrupt_request & CPU_INTERRUPT_HARD) =3D=3D 0) { + return false; } - return false; + + pending_interrupt =3D ppc_pending_interrupt(env); + if (pending_interrupt =3D=3D 0) { + if (env->resume_as_sreset) { + /* + * This is a bug ! It means that has_work took us out of halt + * without anything to deliver while in a PM state that requir= es + * getting out via a 0x100 + * + * This means we will incorrectly execute past the power manag= ement + * instruction instead of triggering a reset. + * + * It generally means a discrepancy between the wakeup conditi= ons in + * the processor has_work implementation and the logic in this + * function. + */ + cpu_abort(env_cpu(env), + "Wakeup from PM state but interrupt Undelivered"); + } + return false; + } + + ppc_hw_interrupt(env, pending_interrupt); + if (env->pending_interrupts =3D=3D 0) { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + return true; } =20 #endif /* !CONFIG_USER_ONLY */ --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581559729466.10351022373004; Mon, 15 Aug 2022 09:39:19 -0700 (PDT) Received: from localhost ([::1]:57800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNd7V-000426-69 for importer@patchew.org; Mon, 15 Aug 2022 12:39:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcpv-0007Jk-L8; Mon, 15 Aug 2022 12:21:11 -0400 Received: from [200.168.210.66] (port=25068 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcpu-0005gw-67; Mon, 15 Aug 2022 12:21:07 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id D3DDB800186; Mon, 15 Aug 2022 13:20:43 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 04/13] target/ppc: prepare to split ppc_interrupt_pending by excp_model Date: Mon, 15 Aug 2022 13:20:10 -0300 Message-Id: <20220815162020.2420093-5-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:44.0108 (UTC) FILETIME=[F82A10C0:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581560574100001 Content-Type: text/plain; charset="utf-8" Rename the method to ppc_interrupt_pending_legacy and create a new ppc_interrupt_pending that will call the appropriate interrupt masking method based on env->excp_model. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 8690017c70..59981efd16 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1678,7 +1678,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) powerpc_excp(cpu, cs->exception_index); } =20 -static int ppc_pending_interrupt(CPUPPCState *env) +static int ppc_pending_interrupt_legacy(CPUPPCState *env) { bool async_deliver; =20 @@ -1790,6 +1790,14 @@ static int ppc_pending_interrupt(CPUPPCState *env) return 0; } =20 +static int ppc_pending_interrupt(CPUPPCState *env) +{ + switch (env->excp_model) { + default: + return ppc_pending_interrupt_legacy(env); + } +} + static void ppc_hw_interrupt(CPUPPCState *env, int pending_interrupt) { PowerPCCPU *cpu =3D env_archcpu(env); --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581136713394.39784524187894; Mon, 15 Aug 2022 09:32:16 -0700 (PDT) Received: from localhost ([::1]:41326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNd0g-0008Tb-JL for importer@patchew.org; Mon, 15 Aug 2022 12:32:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcr0-0008E1-Jm; Mon, 15 Aug 2022 12:22:14 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcqy-0005wd-Mi; Mon, 15 Aug 2022 12:22:14 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 0511280046B; Mon, 15 Aug 2022 13:20:44 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 05/13] target/ppc: create an interrupt masking method for POWER9/POWER10 Date: Mon, 15 Aug 2022 13:20:11 -0300 Message-Id: <20220815162020.2420093-6-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:44.0296 (UTC) FILETIME=[F846C080:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581137700100002 Content-Type: text/plain; charset="utf-8" Create an interrupt masking method for the POWER9 and POWER10 processors. The new method is based on cpu_has_work_POWER{9,10} and ppc_pending_interrupt_legacy. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 160 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 59981efd16..2ca6a917b2 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1678,6 +1678,163 @@ void ppc_cpu_do_interrupt(CPUState *cs) powerpc_excp(cpu, cs->exception_index); } =20 +static int ppc_pending_interrupt_p9(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + bool async_deliver =3D false; + + /* External reset */ + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + return PPC_INTERRUPT_RESET; + } + + if (cs->halted) { + uint64_t psscr =3D env->spr[SPR_PSSCR]; + + if (!(psscr & PSSCR_EC)) { + /* If EC is clear, return any system-caused interrupt */ + async_deliver =3D true; + } else { + /* External Exception */ + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && + (env->spr[SPR_LPCR] & LPCR_EEE)) { + bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); + if (!heic || !FIELD_EX64_HV(env->msr) || + FIELD_EX64(env->msr, MSR, PR)) { + return PPC_INTERRUPT_EXT; + } + } + /* Decrementer Exception */ + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && + (env->spr[SPR_LPCR] & LPCR_DEE)) { + return PPC_INTERRUPT_DECR; + } + /* Machine Check or Hypervisor Maintenance Exception */ + if (env->spr[SPR_LPCR] & LPCR_OEE) { + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + return PPC_INTERRUPT_MCK; + } + if (env->pending_interrupts & PPC_INTERRUPT_HMI) { + return PPC_INTERRUPT_HMI; + } + } + /* Privileged Doorbell Exception */ + if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && + (env->spr[SPR_LPCR] & LPCR_PDEE)) { + return PPC_INTERRUPT_DOORBELL; + } + /* Hypervisor Doorbell Exception */ + if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && + (env->spr[SPR_LPCR] & LPCR_HDEE)) { + return PPC_INTERRUPT_HDOORBELL; + } + /* Hypervisor virtualization exception */ + if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && + (env->spr[SPR_LPCR] & LPCR_HVEE)) { + return PPC_INTERRUPT_HVIRT; + } + return 0; + } + } + + /* Machine check exception */ + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + return PPC_INTERRUPT_MCK; + } + + /* + * For interrupts that gate on MSR:EE, we need to do something a + * bit more subtle, as we need to let them through even when EE is + * clear when coming out of some power management states (in order + * for them to become a 0x100). + */ + async_deliver |=3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sre= set; + + /* Hypervisor decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + /* LPCR will be clear when not supported so this will work */ + bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { + /* HDEC clears on delivery */ + return PPC_INTERRUPT_HDECR; + } + } + + /* Hypervisor virtualization interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { + /* LPCR will be clear when not supported so this will work */ + bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { + return PPC_INTERRUPT_HVIRT; + } + } + + /* External interrupt can ignore MSR:EE under some circumstances */ + if (env->pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); + /* HEIC blocks delivery to the hypervisor */ + if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && + !FIELD_EX64(env->msr, MSR, PR))) || + (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { + return PPC_INTERRUPT_EXT; + } + } + if (FIELD_EX64(env->msr, MSR, CE)) { + /* External critical interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { + return PPC_INTERRUPT_CEXT; + } + } + if (async_deliver !=3D 0) { + /* Watchdog timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + return PPC_INTERRUPT_WDT; + } + if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { + return PPC_INTERRUPT_CDOORBELL; + } + /* Fixed interval timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + return PPC_INTERRUPT_FIT; + } + /* Programmable interval timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_PIT) { + return PPC_INTERRUPT_PIT; + } + /* Decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + return PPC_INTERRUPT_DECR; + } + if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + return PPC_INTERRUPT_DOORBELL; + } + if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + return PPC_INTERRUPT_HDOORBELL; + } + if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + return PPC_INTERRUPT_PERFM; + } + /* Thermal interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_THERM) { + return PPC_INTERRUPT_THERM; + } + /* EBB exception */ + if (env->pending_interrupts & PPC_INTERRUPT_EBB) { + /* + * EBB exception must be taken in problem state and + * with BESCR_GE set. + */ + if (FIELD_EX64(env->msr, MSR, PR) && + (env->spr[SPR_BESCR] & BESCR_GE)) { + return PPC_INTERRUPT_EBB; + } + } + } + + return 0; +} + static int ppc_pending_interrupt_legacy(CPUPPCState *env) { bool async_deliver; @@ -1793,6 +1950,9 @@ static int ppc_pending_interrupt_legacy(CPUPPCState *= env) static int ppc_pending_interrupt(CPUPPCState *env) { switch (env->excp_model) { + case POWERPC_EXCP_POWER9: + case POWERPC_EXCP_POWER10: + return ppc_pending_interrupt_p9(env); default: return ppc_pending_interrupt_legacy(env); } --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581135506305.3819559554606; Mon, 15 Aug 2022 09:32:15 -0700 (PDT) Received: from localhost ([::1]:41324 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNd0g-0008Ry-Ba for importer@patchew.org; Mon, 15 Aug 2022 12:32:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcr3-0008H0-HW; Mon, 15 Aug 2022 12:22:17 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcr2-0005wd-3z; Mon, 15 Aug 2022 12:22:17 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 338C0800186; Mon, 15 Aug 2022 13:20:44 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 06/13] target/ppc: remove embedded interrupts from ppc_pending_interrupt_p9 Date: Mon, 15 Aug 2022 13:20:12 -0300 Message-Id: <20220815162020.2420093-7-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:44.0469 (UTC) FILETIME=[F8612650:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581137693100001 Content-Type: text/plain; charset="utf-8" Critical Input, Watchdog Timer, and Fixed Interval Timer are only defined for embedded CPUs. The Programmable Interval Timer is 40x-only. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2ca6a917b2..42b57019ba 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1780,28 +1780,10 @@ static int ppc_pending_interrupt_p9(CPUPPCState *en= v) return PPC_INTERRUPT_EXT; } } - if (FIELD_EX64(env->msr, MSR, CE)) { - /* External critical interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { - return PPC_INTERRUPT_CEXT; - } - } if (async_deliver !=3D 0) { - /* Watchdog timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_WDT) { - return PPC_INTERRUPT_WDT; - } if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { return PPC_INTERRUPT_CDOORBELL; } - /* Fixed interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_FIT) { - return PPC_INTERRUPT_FIT; - } - /* Programmable interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_PIT) { - return PPC_INTERRUPT_PIT; - } /* Decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581914809760.163203208818; Mon, 15 Aug 2022 09:45:14 -0700 (PDT) Received: from localhost ([::1]:56816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdDE-0002P8-Iw for importer@patchew.org; Mon, 15 Aug 2022 12:45:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrA-0008IP-4N; Mon, 15 Aug 2022 12:22:24 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcr4-0005wd-KM; Mon, 15 Aug 2022 12:22:20 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 65DE380046B; Mon, 15 Aug 2022 13:20:44 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 07/13] target/ppc: create an interrupt masking method for POWER8 Date: Mon, 15 Aug 2022 13:20:13 -0300 Message-Id: <20220815162020.2420093-8-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:44.0704 (UTC) FILETIME=[F8850200:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581916027100001 Content-Type: text/plain; charset="utf-8" Create an interrupt masking method for POWER8. The new method is based on cpu_has_work_POWER8 and ppc_pending_interrupt_legacy. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 138 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 42b57019ba..13c2d5e2ce 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1678,6 +1678,142 @@ void ppc_cpu_do_interrupt(CPUState *cs) powerpc_excp(cpu, cs->exception_index); } =20 +static int ppc_pending_interrupt_p8(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + bool async_deliver =3D false; + + /* External reset */ + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + return PPC_INTERRUPT_RESET; + } + + if (cs->halted) { + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { + return PPC_INTERRUPT_EXT; + } + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { + return PPC_INTERRUPT_DECR; + } + if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { + return PPC_INTERRUPT_MCK; + } + if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { + return PPC_INTERRUPT_HMI; + } + if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { + return PPC_INTERRUPT_DOORBELL; + } + if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && + (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { + return PPC_INTERRUPT_HDOORBELL; + } + return 0; + } + + /* Machine check exception */ + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + return PPC_INTERRUPT_MCK; + } + + /* + * For interrupts that gate on MSR:EE, we need to do something a + * bit more subtle, as we need to let them through even when EE is + * clear when coming out of some power management states (in order + * for them to become a 0x100). + */ + async_deliver |=3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sre= set; + + /* Hypervisor decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + /* LPCR will be clear when not supported so this will work */ + bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { + /* HDEC clears on delivery */ + return PPC_INTERRUPT_HDECR; + } + } + + /* Hypervisor virtualization interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { + /* LPCR will be clear when not supported so this will work */ + bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { + return PPC_INTERRUPT_HVIRT; + } + } + + /* External interrupt can ignore MSR:EE under some circumstances */ + if (env->pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); + /* HEIC blocks delivery to the hypervisor */ + if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && + !FIELD_EX64(env->msr, MSR, PR))) || + (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { + return PPC_INTERRUPT_EXT; + } + } + if (FIELD_EX64(env->msr, MSR, CE)) { + /* External critical interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { + return PPC_INTERRUPT_CEXT; + } + } + if (async_deliver !=3D 0) { + /* Watchdog timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + return PPC_INTERRUPT_WDT; + } + if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { + return PPC_INTERRUPT_CDOORBELL; + } + /* Fixed interval timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + return PPC_INTERRUPT_FIT; + } + /* Programmable interval timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_PIT) { + return PPC_INTERRUPT_PIT; + } + /* Decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + return PPC_INTERRUPT_DECR; + } + if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + return PPC_INTERRUPT_DOORBELL; + } + if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + return PPC_INTERRUPT_HDOORBELL; + } + if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + return PPC_INTERRUPT_PERFM; + } + /* Thermal interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_THERM) { + return PPC_INTERRUPT_THERM; + } + /* EBB exception */ + if (env->pending_interrupts & PPC_INTERRUPT_EBB) { + /* + * EBB exception must be taken in problem state and + * with BESCR_GE set. + */ + if (FIELD_EX64(env->msr, MSR, PR) && + (env->spr[SPR_BESCR] & BESCR_GE)) { + return PPC_INTERRUPT_EBB; + } + } + } + + return 0; +} + static int ppc_pending_interrupt_p9(CPUPPCState *env) { CPUState *cs =3D env_cpu(env); @@ -1932,6 +2068,8 @@ static int ppc_pending_interrupt_legacy(CPUPPCState *= env) static int ppc_pending_interrupt(CPUPPCState *env) { switch (env->excp_model) { + case POWERPC_EXCP_POWER8: + return ppc_pending_interrupt_p8(env); case POWERPC_EXCP_POWER9: case POWERPC_EXCP_POWER10: return ppc_pending_interrupt_p9(env); --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581795581775.7150935706127; Mon, 15 Aug 2022 09:43:15 -0700 (PDT) Received: from localhost ([::1]:57116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdBK-0006yj-EU for importer@patchew.org; Mon, 15 Aug 2022 12:43:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33188) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrC-0008NV-RZ; Mon, 15 Aug 2022 12:22:26 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcrB-0005wd-99; Mon, 15 Aug 2022 12:22:26 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:44 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 9BB4F800186; Mon, 15 Aug 2022 13:20:44 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 08/13] target/ppc: remove unused interrupts from ppc_pending_interrupt_p8 Date: Mon, 15 Aug 2022 13:20:14 -0300 Message-Id: <20220815162020.2420093-9-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:44.0860 (UTC) FILETIME=[F89CCFC0:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581797477100002 Content-Type: text/plain; charset="utf-8" The Hypervisor Virtualization Interrupt was introduced in PowerISA v3.0. Critical Input, Watchdog Timer, and Fixed Interval Timer are only defined for embedded CPUs. The Programmable Interval Timer is 40x-only. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 13c2d5e2ce..0dbd385bf0 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1739,15 +1739,6 @@ static int ppc_pending_interrupt_p8(CPUPPCState *env) } } =20 - /* Hypervisor virtualization interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { - /* LPCR will be clear when not supported so this will work */ - bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); - if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { - return PPC_INTERRUPT_HVIRT; - } - } - /* External interrupt can ignore MSR:EE under some circumstances */ if (env->pending_interrupts & PPC_INTERRUPT_EXT) { bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); @@ -1759,28 +1750,10 @@ static int ppc_pending_interrupt_p8(CPUPPCState *en= v) return PPC_INTERRUPT_EXT; } } - if (FIELD_EX64(env->msr, MSR, CE)) { - /* External critical interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { - return PPC_INTERRUPT_CEXT; - } - } if (async_deliver !=3D 0) { - /* Watchdog timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_WDT) { - return PPC_INTERRUPT_WDT; - } if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { return PPC_INTERRUPT_CDOORBELL; } - /* Fixed interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_FIT) { - return PPC_INTERRUPT_FIT; - } - /* Programmable interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_PIT) { - return PPC_INTERRUPT_PIT; - } /* Decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660582062127726.6968140087697; Mon, 15 Aug 2022 09:47:42 -0700 (PDT) Received: from localhost ([::1]:34282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdFd-0004xH-2f for importer@patchew.org; Mon, 15 Aug 2022 12:47:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrH-00005L-P1; Mon, 15 Aug 2022 12:22:31 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcrE-0005wd-0K; Mon, 15 Aug 2022 12:22:31 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id C02A980046B; Mon, 15 Aug 2022 13:20:44 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 09/13] target/ppc: create an interrupt masking method for POWER7 Date: Mon, 15 Aug 2022 13:20:15 -0300 Message-Id: <20220815162020.2420093-10-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:45.0063 (UTC) FILETIME=[F8BBC970:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660582063655100001 Content-Type: text/plain; charset="utf-8" The new method is based on cpu_has_work_POWER7 and ppc_pending_interrupt_legacy. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 130 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0dbd385bf0..a67ab28661 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1678,6 +1678,134 @@ void ppc_cpu_do_interrupt(CPUState *cs) powerpc_excp(cpu, cs->exception_index); } =20 +static int ppc_pending_interrupt_p7(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + bool async_deliver; + + /* External reset */ + if (env->pending_interrupts & PPC_INTERRUPT_RESET) { + return PPC_INTERRUPT_RESET; + } + + if (cs->halted) { + if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { + return PPC_INTERRUPT_EXT; + } + if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { + return PPC_INTERRUPT_DECR; + } + if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { + return PPC_INTERRUPT_MCK; + } + if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && + (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { + return PPC_INTERRUPT_HMI; + } + return 0; + } + + /* Machine check exception */ + if (env->pending_interrupts & PPC_INTERRUPT_MCK) { + return PPC_INTERRUPT_MCK; + } + + /* + * For interrupts that gate on MSR:EE, we need to do something a + * bit more subtle, as we need to let them through even when EE is + * clear when coming out of some power management states (in order + * for them to become a 0x100). + */ + async_deliver =3D FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sres= et; + + /* Hypervisor decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { + /* LPCR will be clear when not supported so this will work */ + bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { + /* HDEC clears on delivery */ + return PPC_INTERRUPT_HDECR; + } + } + + /* Hypervisor virtualization interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { + /* LPCR will be clear when not supported so this will work */ + bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { + return PPC_INTERRUPT_HVIRT; + } + } + + /* External interrupt can ignore MSR:EE under some circumstances */ + if (env->pending_interrupts & PPC_INTERRUPT_EXT) { + bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); + bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); + /* HEIC blocks delivery to the hypervisor */ + if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && + !FIELD_EX64(env->msr, MSR, PR))) || + (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { + return PPC_INTERRUPT_EXT; + } + } + if (FIELD_EX64(env->msr, MSR, CE)) { + /* External critical interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { + return PPC_INTERRUPT_CEXT; + } + } + if (async_deliver !=3D 0) { + /* Watchdog timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_WDT) { + return PPC_INTERRUPT_WDT; + } + if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { + return PPC_INTERRUPT_CDOORBELL; + } + /* Fixed interval timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_FIT) { + return PPC_INTERRUPT_FIT; + } + /* Programmable interval timer on embedded PowerPC */ + if (env->pending_interrupts & PPC_INTERRUPT_PIT) { + return PPC_INTERRUPT_PIT; + } + /* Decrementer exception */ + if (env->pending_interrupts & PPC_INTERRUPT_DECR) { + return PPC_INTERRUPT_DECR; + } + if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) { + return PPC_INTERRUPT_DOORBELL; + } + if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) { + return PPC_INTERRUPT_HDOORBELL; + } + if (env->pending_interrupts & PPC_INTERRUPT_PERFM) { + return PPC_INTERRUPT_PERFM; + } + /* Thermal interrupt */ + if (env->pending_interrupts & PPC_INTERRUPT_THERM) { + return PPC_INTERRUPT_THERM; + } + /* EBB exception */ + if (env->pending_interrupts & PPC_INTERRUPT_EBB) { + /* + * EBB exception must be taken in problem state and + * with BESCR_GE set. + */ + if (FIELD_EX64(env->msr, MSR, PR) && + (env->spr[SPR_BESCR] & BESCR_GE)) { + return PPC_INTERRUPT_EBB; + } + } + } + + return 0; +} + static int ppc_pending_interrupt_p8(CPUPPCState *env) { CPUState *cs =3D env_cpu(env); @@ -2041,6 +2169,8 @@ static int ppc_pending_interrupt_legacy(CPUPPCState *= env) static int ppc_pending_interrupt(CPUPPCState *env) { switch (env->excp_model) { + case POWERPC_EXCP_POWER7: + return ppc_pending_interrupt_p7(env); case POWERPC_EXCP_POWER8: return ppc_pending_interrupt_p8(env); case POWERPC_EXCP_POWER9: --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660581796066502.85114988807766; Mon, 15 Aug 2022 09:43:16 -0700 (PDT) Received: from localhost ([::1]:57118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdBK-000755-SO for importer@patchew.org; Mon, 15 Aug 2022 12:43:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33242) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrN-000089-6k; Mon, 15 Aug 2022 12:22:41 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcrI-0005wd-Rd; Mon, 15 Aug 2022 12:22:34 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id EF20A800186; Mon, 15 Aug 2022 13:20:44 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 10/13] target/ppc: remove unused interrupts from ppc_pending_interrupt_p7 Date: Mon, 15 Aug 2022 13:20:16 -0300 Message-Id: <20220815162020.2420093-11-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:45.0219 (UTC) FILETIME=[F8D39730:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660581797466100001 Content-Type: text/plain; charset="utf-8" The Hypervisor Virtualization Interrupt was introduced in PowerISA v3.0. Critical Input, Watchdog Timer, and Fixed Interval Timer are only defined for embedded CPUs. The Programmable Interval Timer is 40x-only. The Event-Based Branch Facility was added in PowerISA v2.07. Signed-off-by: Matheus Ferst --- target/ppc/excp_helper.c | 38 -------------------------------------- 1 file changed, 38 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a67ab28661..b4c1198ea2 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1731,15 +1731,6 @@ static int ppc_pending_interrupt_p7(CPUPPCState *env) } } =20 - /* Hypervisor virtualization interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) { - /* LPCR will be clear when not supported so this will work */ - bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); - if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { - return PPC_INTERRUPT_HVIRT; - } - } - /* External interrupt can ignore MSR:EE under some circumstances */ if (env->pending_interrupts & PPC_INTERRUPT_EXT) { bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); @@ -1751,28 +1742,10 @@ static int ppc_pending_interrupt_p7(CPUPPCState *en= v) return PPC_INTERRUPT_EXT; } } - if (FIELD_EX64(env->msr, MSR, CE)) { - /* External critical interrupt */ - if (env->pending_interrupts & PPC_INTERRUPT_CEXT) { - return PPC_INTERRUPT_CEXT; - } - } if (async_deliver !=3D 0) { - /* Watchdog timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_WDT) { - return PPC_INTERRUPT_WDT; - } if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) { return PPC_INTERRUPT_CDOORBELL; } - /* Fixed interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_FIT) { - return PPC_INTERRUPT_FIT; - } - /* Programmable interval timer on embedded PowerPC */ - if (env->pending_interrupts & PPC_INTERRUPT_PIT) { - return PPC_INTERRUPT_PIT; - } /* Decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; @@ -1790,17 +1763,6 @@ static int ppc_pending_interrupt_p7(CPUPPCState *env) if (env->pending_interrupts & PPC_INTERRUPT_THERM) { return PPC_INTERRUPT_THERM; } - /* EBB exception */ - if (env->pending_interrupts & PPC_INTERRUPT_EBB) { - /* - * EBB exception must be taken in problem state and - * with BESCR_GE set. - */ - if (FIELD_EX64(env->msr, MSR, PR) && - (env->spr[SPR_BESCR] & BESCR_GE)) { - return PPC_INTERRUPT_EBB; - } - } } =20 return 0; --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660582464634214.47921643101722; Mon, 15 Aug 2022 09:54:24 -0700 (PDT) Received: from localhost ([::1]:36232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdM7-0001PO-9O for importer@patchew.org; Mon, 15 Aug 2022 12:54:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrP-00008E-Vd; Mon, 15 Aug 2022 12:22:41 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcrO-0005wd-CK; Mon, 15 Aug 2022 12:22:39 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 244EF80046B; Mon, 15 Aug 2022 13:20:45 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 11/13] target/ppc: remove ppc_store_lpcr from CONFIG_USER_ONLY builds Date: Mon, 15 Aug 2022 13:20:17 -0300 Message-Id: <20220815162020.2420093-12-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:45.0626 (UTC) FILETIME=[F911B1A0:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660582466443100001 Content-Type: text/plain; charset="utf-8" Writes to LPCR are hypervisor privileged. Signed-off-by: Matheus Ferst --- target/ppc/cpu.c | 2 ++ target/ppc/cpu.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 401b6f9e63..9f261bde8e 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -73,6 +73,7 @@ void ppc_store_msr(CPUPPCState *env, target_ulong value) hreg_store_msr(env, value, 0); } =20 +#if !defined(CONFIG_USER_ONLY) void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) { PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); @@ -82,6 +83,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) /* The gtse bit affects hflags */ hreg_compute_hflags(env); } +#endif =20 static inline void fpscr_set_rounding_mode(CPUPPCState *env) { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c7864bb3b1..5018296f02 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1370,9 +1370,9 @@ void ppc_translate_init(void); =20 #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); +void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr(CPUPPCState *env, target_ulong value); -void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); =20 void ppc_cpu_list(void); =20 --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660582067260501.8172815145508; Mon, 15 Aug 2022 09:47:47 -0700 (PDT) Received: from localhost ([::1]:34284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdFh-000576-81 for importer@patchew.org; Mon, 15 Aug 2022 12:47:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrS-0000DE-U7; Mon, 15 Aug 2022 12:22:42 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcrR-0005wd-4V; Mon, 15 Aug 2022 12:22:42 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 4E0C2800186; Mon, 15 Aug 2022 13:20:45 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 12/13] target/ppc: introduce ppc_maybe_interrupt Date: Mon, 15 Aug 2022 13:20:18 -0300 Message-Id: <20220815162020.2420093-13-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:45.0766 (UTC) FILETIME=[F9270E60:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660582067692100001 Content-Type: text/plain; charset="utf-8" This new method will check if any pending interrupt was unmasked and then call cpu_interrupt/cpu_reset_interrupt accordingly. Code that raises/lowers or masks/unmasks interrupts should call this method to keep CPU_INTERRUPT_HARD coherent with env->pending_interrupts. Signed-off-by: Matheus Ferst --- hw/ppc/ppc.c | 7 +------ target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 19 +++++++++++++++++++ target/ppc/helper_regs.c | 2 ++ target/ppc/translate.c | 8 ++++++-- 5 files changed, 29 insertions(+), 8 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 77e611e81c..dc86c1c7db 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -42,7 +42,6 @@ static void cpu_ppc_tb_start (CPUPPCState *env); =20 void ppc_set_irq(PowerPCCPU *cpu, int irq, int level) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; unsigned int old_pending; bool locked =3D false; @@ -57,19 +56,15 @@ void ppc_set_irq(PowerPCCPU *cpu, int irq, int level) =20 if (level) { env->pending_interrupts |=3D irq; - cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { env->pending_interrupts &=3D ~irq; - if (env->pending_interrupts =3D=3D 0) { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } } =20 if (old_pending !=3D env->pending_interrupts) { + ppc_maybe_interrupt(env); kvmppc_set_interrupt(cpu, irq, level); } =20 - trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts, CPU(cpu)->interrupt_request); =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5018296f02..f65e0d7de8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1358,6 +1358,7 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction = f, CPUState *cs, int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY +void ppc_maybe_interrupt(CPUPPCState *env); void ppc_cpu_do_interrupt(CPUState *cpu); bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_do_system_reset(CPUState *cs); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b4c1198ea2..788dcd732a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2143,6 +2143,23 @@ static int ppc_pending_interrupt(CPUPPCState *env) } } =20 +void ppc_maybe_interrupt(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + + if (ppc_pending_interrupt(env)) { + if (!qemu_mutex_iothread_locked()) { + qemu_mutex_lock_iothread(); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + qemu_mutex_unlock_iothread(); + } else { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + static void ppc_hw_interrupt(CPUPPCState *env, int pending_interrupt) { PowerPCCPU *cpu =3D env_archcpu(env); @@ -2380,6 +2397,8 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) /* Condition for waking up at 0x100 */ env->resume_as_sreset =3D (insn !=3D PPC_PM_STOP) || (env->spr[SPR_PSSCR] & PSSCR_EC); + + ppc_maybe_interrupt(env); } #endif /* defined(TARGET_PPC64) */ =20 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 12235ea2e9..2e85e124ab 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -260,6 +260,8 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value= , int alter_hv) env->msr =3D value; hreg_compute_hflags(env); #if !defined(CONFIG_USER_ONLY) + ppc_maybe_interrupt(env); + if (unlikely(FIELD_EX64(env->msr, MSR, POW))) { if (!env->pending_interrupts && (*env->check_pow)(env)) { cs->halted =3D 1; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 388337f81b..60dd66f736 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6174,7 +6174,8 @@ static void gen_wrtee(DisasContext *ctx) t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); - tcg_gen_or_tl(cpu_msr, cpu_msr, t0); + tcg_gen_or_tl(t0, cpu_msr, t0); + gen_helper_store_msr(cpu_env, t0); tcg_temp_free(t0); /* * Stop translation to have a chance to raise an exception if we @@ -6192,7 +6193,10 @@ static void gen_wrteei(DisasContext *ctx) #else CHK_SV(ctx); if (ctx->opcode & 0x00008000) { - tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); + TCGv t0 =3D tcg_temp_new(); + tcg_gen_ori_tl(t0, cpu_msr, (1 << MSR_EE)); + gen_helper_store_msr(cpu_env, t0); + tcg_temp_free(t0); /* Stop translation to have a chance to raise an exception */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } else { --=20 2.25.1 From nobody Sat May 4 21:54:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 166058244433987.98495921428332; Mon, 15 Aug 2022 09:54:04 -0700 (PDT) Received: from localhost ([::1]:47248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNdLh-0001Bb-GN for importer@patchew.org; Mon, 15 Aug 2022 12:53:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNcrV-0000MJ-Sk; Mon, 15 Aug 2022 12:22:49 -0400 Received: from [200.168.210.66] (port=4179 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNcrT-0005wd-WC; Mon, 15 Aug 2022 12:22:45 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 15 Aug 2022 13:20:45 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id AEE8980046B; Mon, 15 Aug 2022 13:20:45 -0300 (-03) From: Matheus Ferst To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, fbarrat@linux.ibm.com, alex.bennee@linaro.org, Matheus Ferst Subject: [RFC PATCH 13/13] target/ppc: unify cpu->has_work based on cs->interrupt_request Date: Mon, 15 Aug 2022 13:20:19 -0300 Message-Id: <20220815162020.2420093-14-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> References: <20220815162020.2420093-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 15 Aug 2022 16:20:45.0969 (UTC) FILETIME=[F9460810:01D8B0C2] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=200.168.210.66; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660582447671100001 Content-Type: text/plain; charset="utf-8" Now that cs->interrupt_request indicates if there is any unmasked interrupt, checking if the CPU has work to do can be simplified to a single check that works for all CPU models. Signed-off-by: Matheus Ferst --- target/ppc/cpu_init.c | 212 +----------------------------------------- 1 file changed, 1 insertion(+), 211 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 850334545a..303e81596d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5923,46 +5923,10 @@ static bool ppc_pvr_match_power7(PowerPCCPUClass *p= cc, uint32_t pvr) return false; } =20 -static bool cpu_has_work_POWER7(CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - - if (cs->halted) { - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && - (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { - return true; - } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { - return true; - } - return false; - } else { - return FIELD_EX64(env->msr, MSR, EE) && - (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER7"; dc->desc =3D "POWER7"; @@ -5971,7 +5935,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER7; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER7; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6087,54 +6050,10 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *p= cc, uint32_t pvr) return false; } =20 -static bool cpu_has_work_POWER8(CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - - if (cs->halted) { - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_MCK) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_HMI) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { - return true; - } - if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && - (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { - return true; - } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { - return true; - } - return false; - } else { - return FIELD_EX64(env->msr, MSR, EE) && - (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER8"; dc->desc =3D "POWER8"; @@ -6143,7 +6062,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; pcc->init_proc =3D init_proc_POWER8; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER8; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6290,71 +6208,10 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *p= cc, uint32_t pvr) return false; } =20 -static bool cpu_has_work_POWER9(CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - - if (cs->halted) { - uint64_t psscr =3D env->spr[SPR_PSSCR]; - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - /* If EC is clear, just return true on any pending interrupt */ - if (!(psscr & PSSCR_EC)) { - return true; - } - /* External Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_EEE)) { - bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (!heic || !FIELD_EX64_HV(env->msr) || - FIELD_EX64(env->msr, MSR, PR)) { - return true; - } - } - /* Decrementer Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_DEE)) { - return true; - } - /* Machine Check or Hypervisor Maintenance Exception */ - if ((env->pending_interrupts & (PPC_INTERRUPT_MCK | PPC_INTERRUPT_= HMI)) - && (env->spr[SPR_LPCR] & LPCR_OEE)) { - return true; - } - /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && - (env->spr[SPR_LPCR] & LPCR_PDEE)) { - return true; - } - /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && - (env->spr[SPR_LPCR] & LPCR_HDEE)) { - return true; - } - /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && - (env->spr[SPR_LPCR] & LPCR_HVEE)) { - return true; - } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { - return true; - } - return false; - } else { - return FIELD_EX64(env->msr, MSR, EE) && - (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER9"; dc->desc =3D "POWER9"; @@ -6364,7 +6221,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6507,71 +6363,10 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *= pcc, uint32_t pvr) return false; } =20 -static bool cpu_has_work_POWER10(CPUState *cs) -{ - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - - if (cs->halted) { - uint64_t psscr =3D env->spr[SPR_PSSCR]; - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - /* If EC is clear, just return true on any pending interrupt */ - if (!(psscr & PSSCR_EC)) { - return true; - } - /* External Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_EXT) && - (env->spr[SPR_LPCR] & LPCR_EEE)) { - bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (!heic || !FIELD_EX64_HV(env->msr) || - FIELD_EX64(env->msr, MSR, PR)) { - return true; - } - } - /* Decrementer Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_DECR) && - (env->spr[SPR_LPCR] & LPCR_DEE)) { - return true; - } - /* Machine Check or Hypervisor Maintenance Exception */ - if ((env->pending_interrupts & (PPC_INTERRUPT_MCK | PPC_INTERRUPT_= HMI)) - && (env->spr[SPR_LPCR] & LPCR_OEE)) { - return true; - } - /* Privileged Doorbell Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) && - (env->spr[SPR_LPCR] & LPCR_PDEE)) { - return true; - } - /* Hypervisor Doorbell Exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) && - (env->spr[SPR_LPCR] & LPCR_HDEE)) { - return true; - } - /* Hypervisor virtualization exception */ - if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) && - (env->spr[SPR_LPCR] & LPCR_HVEE)) { - return true; - } - if (env->pending_interrupts & PPC_INTERRUPT_RESET) { - return true; - } - return false; - } else { - return FIELD_EX64(env->msr, MSR, EE) && - (cs->interrupt_request & CPU_INTERRUPT_HARD); - } -} - POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); =20 dc->fw_name =3D "PowerPC,POWER10"; dc->desc =3D "POWER10"; @@ -6582,7 +6377,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER10; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -7139,11 +6933,7 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) =20 static bool ppc_cpu_has_work(CPUState *cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - - return FIELD_EX64(env->msr, MSR, EE) && - (cs->interrupt_request & CPU_INTERRUPT_HARD); + return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 static void ppc_cpu_reset(DeviceState *dev) --=20 2.25.1