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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1660533467; x=1663125468; bh=DpUrOLtNTJGn6WeISd xZPFtJtbvXhcV5iwomnnWlCDE=; b=g7x70M0d0SVAeSmb7xRuccwp0Q+QA+SAvK v0f42pr2xYdlxFpRAP2itZ6iMHnssbejrEOBYMjefa34/lLOxrenK13oVM77EB/S gC2zkXojMKkZ8Y8hOqRt9dX+Y/7LLqW7izwHk5m+QSDMoHEpVj38bT659mkJlG1j Giw22wthJxB9ecLOQNIHUhWWsv2SYDpIbTuuayQiAMd5r/EatFIvDZzOfzuYY2ZB w9xkE7EuqrFuewjsfuwBClZYiyOs7htXCjsvgWMDuDExiyKeOpHnb2dsKKTueutt iicF1Wm8V+x1+354w4VU0yT+Syd8un2WKy0oyipGmQ4cSx71lt2g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis Subject: [PATCH v2 3/4] hw/ssi: ibex_spi: fixup/add rw1c functionality Date: Mon, 15 Aug 2022 13:16:24 +1000 Message-Id: <20220815031624.170857-4-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> References: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=219596703=wilfred.mallawa@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660533575257100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch adds the `rw1c` functionality to the respective registers. The status fields are cleared when the respective field is set. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 34 ++++++++++++++++++++++++++++++++-- include/hw/ssi/ibex_spi_host.h | 4 ++-- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index d377f1100c..19dd094d76 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -350,7 +350,17 @@ static void ibex_spi_host_write(void *opaque, hwaddr a= ddr, =20 switch (addr) { /* Skipping any R/O registers */ - case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: + case IBEX_SPI_HOST_INTR_STATE: + /* rw1c status register */ + if (FIELD_EX32(val32, INTR_STATE, ERROR)) { + data =3D FIELD_DP32(data, INTR_STATE, ERROR, 0); + } + if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { + data =3D FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0); + } + s->regs[addr] =3D data; + break; + case IBEX_SPI_HOST_INTR_ENABLE: s->regs[addr] =3D val32; break; case IBEX_SPI_HOST_INTR_TEST: @@ -493,7 +503,27 @@ static void ibex_spi_host_write(void *opaque, hwaddr a= ddr, * When an error occurs, the corresponding bit must be cleared * here before issuing any further commands */ - s->regs[addr] =3D val32; + status =3D s->regs[addr]; + /* rw1c status register */ + if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { + status =3D FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { + status =3D FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0); + } + s->regs[addr] =3D status; break; case IBEX_SPI_HOST_EVENT_ENABLE: /* Controls which classes of SPI events raise an interrupt. */ diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h index 3fedcb6805..1f6d077766 100644 --- a/include/hw/ssi/ibex_spi_host.h +++ b/include/hw/ssi/ibex_spi_host.h @@ -40,7 +40,7 @@ OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST) =20 /* SPI Registers */ -#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */ +#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */ #define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */ #define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */ #define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */ @@ -54,7 +54,7 @@ #define IBEX_SPI_HOST_TXDATA (0x28 / 4) =20 #define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */ -#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */ +#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw1c */ #define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */ =20 /* FIFO Len in Bytes */ --=20 2.37.1