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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1660533439; x=1663125440; bh=w4GzVfAkvrf4UkgJX3 Gd2cdwXyJJ91gEYqXUW4q6J+0=; b=ejr17W+ZHwlN2idAZ6lsD5Q+Gpj/nRUc2I 4o6enwmGZqjJ14zBVXCaWe4lJ2CVyKPVCXMBxDyKGimAe441kekcY6zqKua2CGgG 1xjzIbxyu2xIeGHnJHw2Y9TJpIJDKFfFwJiXJ0EVmYyVqAqDTctPKdv+CdN1fYuy /kKfMhGY/kZPfsfnWQiCvrR808KUQiijU0YlEcn3jRoI7+sT8PS1pRbiw+dWgRL2 oXEYPCN+VThFSFibWcVmZlhqjFimVl9MTQOCKeqU2HSJlVwdrTVt7M1ECu3UGqLv lap/xh8naFlCXe9ucIm9x9kUJVFiSrT2bTeTNu6e9+GGmHhwU5qg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis , Andrew Jones Subject: [PATCH v2 1/4] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Date: Mon, 15 Aug 2022 13:16:22 +1000 Message-Id: <20220815031624.170857-2-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> References: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=219596703=wilfred.mallawa@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660533565444100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch fixes up minor typos in ibex_spi_host Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- hw/ssi/ibex_spi_host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index d14580b409..601041d719 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -172,7 +172,7 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) & R_INTR_STATE_SPI_EVENT_MASK; int err_irq =3D 0, event_irq =3D 0; =20 - /* Error IRQ enabled and Error IRQ Cleared*/ + /* Error IRQ enabled and Error IRQ Cleared */ if (error_en && !err_pending) { /* Event enabled, Interrupt Test Error */ if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) { @@ -434,7 +434,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, case IBEX_SPI_HOST_TXDATA: /* * This is a hardware `feature` where - * the first word written TXDATA after init is omitted entirely + * the first word written to TXDATA after init is omitted entirely */ if (s->init_status) { s->init_status =3D false; @@ -487,7 +487,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, break; case IBEX_SPI_HOST_ERROR_STATUS: /* - * Indicates that any errors that have occurred. + * Indicates any errors that have occurred. * When an error occurs, the corresponding bit must be cleared * here before issuing any further commands */ --=20 2.37.1 From nobody Fri May 3 15:02:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=219596703=wilfred.mallawa@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660533569373100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch addresses the coverity issues specified in [1], as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been implemented to clean up the code. Patch V2: Style changes have been made as suggested by Andrew Jones, to promote code readability. [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html Fixes: Coverity CID 1488107 Signed-off-by: Wilfred Mallawa Reviewed-by: Andrew Jones --- hw/ssi/ibex_spi_host.c | 128 +++++++++++++++++++++-------------------- 1 file changed, 65 insertions(+), 63 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 601041d719..d377f1100c 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -108,18 +108,20 @@ static inline uint8_t div4_round_up(uint8_t dividend) =20 static void ibex_spi_rxfifo_reset(IbexSPIHostState *s) { + uint32_t data =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Empty the RX FIFO and assert RXEMPTY */ fifo8_reset(&s->rx_fifo); - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXFULL_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_RXEMPTY_MASK; + data =3D FIELD_DP32(data, STATUS, RXEMPTY, 1); + s->regs[IBEX_SPI_HOST_STATUS] =3D data; } =20 static void ibex_spi_txfifo_reset(IbexSPIHostState *s) { + uint32_t data =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Empty the TX FIFO and assert TXEMPTY */ fifo8_reset(&s->tx_fifo); - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXFULL_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_TXEMPTY_MASK; + data =3D FIELD_DP32(data, STATUS, TXEMPTY, 1); + s->regs[IBEX_SPI_HOST_STATUS] =3D data; } =20 static void ibex_spi_host_reset(DeviceState *dev) @@ -162,37 +164,38 @@ static void ibex_spi_host_reset(DeviceState *dev) */ static void ibex_spi_host_irq(IbexSPIHostState *s) { - bool error_en =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE] - & R_INTR_ENABLE_ERROR_MASK; - bool event_en =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE] - & R_INTR_ENABLE_SPI_EVENT_MASK; - bool err_pending =3D s->regs[IBEX_SPI_HOST_INTR_STATE] - & R_INTR_STATE_ERROR_MASK; - bool status_pending =3D s->regs[IBEX_SPI_HOST_INTR_STATE] - & R_INTR_STATE_SPI_EVENT_MASK; + uint32_t intr_test_reg =3D s->regs[IBEX_SPI_HOST_INTR_TEST]; + uint32_t intr_en_reg =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE]; + uint32_t intr_state_reg =3D s->regs[IBEX_SPI_HOST_INTR_STATE]; + + uint32_t err_en_reg =3D s->regs[IBEX_SPI_HOST_ERROR_ENABLE]; + uint32_t event_en_reg =3D s->regs[IBEX_SPI_HOST_EVENT_ENABLE]; + uint32_t err_status_reg =3D s->regs[IBEX_SPI_HOST_ERROR_STATUS]; + uint32_t status_reg =3D s->regs[IBEX_SPI_HOST_STATUS]; + + + bool error_en =3D FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR); + bool event_en =3D FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT); + bool err_pending =3D FIELD_EX32(intr_state_reg, INTR_STATE, ERROR); + bool status_pending =3D FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVE= NT); + int err_irq =3D 0, event_irq =3D 0; =20 /* Error IRQ enabled and Error IRQ Cleared */ if (error_en && !err_pending) { /* Event enabled, Interrupt Test Error */ - if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) { + if (FIELD_EX32(intr_test_reg, INTR_TEST, ERROR)) { err_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] - & R_ERROR_ENABLE_CMDBUSY_MASK) && - s->regs[IBEX_SPI_HOST_ERROR_STATUS] - & R_ERROR_STATUS_CMDBUSY_MASK) { + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDBUSY) && + FIELD_EX32(err_status_reg, ERROR_STATUS, CMDBUSY)) { /* Wrote to COMMAND when not READY */ err_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] - & R_ERROR_ENABLE_CMDINVAL_MASK) && - s->regs[IBEX_SPI_HOST_ERROR_STATUS] - & R_ERROR_STATUS_CMDINVAL_MASK) { + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDINVAL) && + FIELD_EX32(err_status_reg, ERROR_STATUS, CMDINVAL)) { /* Invalid command segment */ err_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] - & R_ERROR_ENABLE_CSIDINVAL_MASK) && - s->regs[IBEX_SPI_HOST_ERROR_STATUS] - & R_ERROR_STATUS_CSIDINVAL_MASK) { + } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CSIDINVAL) && + FIELD_EX32(err_status_reg, ERROR_STATUS, CSIDINVAL)) { /* Invalid value for CSID */ err_irq =3D 1; } @@ -204,22 +207,19 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) =20 /* Event IRQ Enabled and Event IRQ Cleared */ if (event_en && !status_pending) { - if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK)= { + if (FIELD_EX32(intr_test_reg, INTR_STATE, SPI_EVENT)) { /* Event enabled, Interrupt Test Event */ event_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] - & R_EVENT_ENABLE_READY_MASK) && - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK))= { + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, READY) && + FIELD_EX32(status_reg, STATUS, READY)) { /* SPI Host ready for next command */ event_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] - & R_EVENT_ENABLE_TXEMPTY_MASK) && - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK= )) { + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, TXEMPTY) && + FIELD_EX32(status_reg, STATUS, TXEMPTY)) { /* SPI TXEMPTY, TXFIFO drained */ event_irq =3D 1; - } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] - & R_EVENT_ENABLE_RXFULL_MASK) && - (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)= ) { + } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, RXFULL) && + FIELD_EX32(status_reg, STATUS, RXFULL)) { /* SPI RXFULL, RXFIFO full */ event_irq =3D 1; } @@ -232,10 +232,11 @@ static void ibex_spi_host_irq(IbexSPIHostState *s) =20 static void ibex_spi_host_transfer(IbexSPIHostState *s) { - uint32_t rx, tx; + uint32_t rx, tx, data; /* Get num of one byte transfers */ - uint8_t segment_len =3D ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_L= EN_MASK) - >> R_COMMAND_LEN_SHIFT); + uint8_t segment_len =3D FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND], + COMMAND, LEN); + while (segment_len > 0) { if (fifo8_is_empty(&s->tx_fifo)) { /* Assert Stall */ @@ -262,22 +263,21 @@ static void ibex_spi_host_transfer(IbexSPIHostState *= s) --segment_len; } =20 + data =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Assert Ready */ - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_READY_MASK; + data =3D FIELD_DP32(data, STATUS, READY, 1); /* Set RXQD */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXQD_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D (R_STATUS_RXQD_MASK - & div4_round_up(segment_len)); + data =3D FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len)); /* Set TXQD */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXQD_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D (fifo8_num_used(&s->tx_fifo) / 4) - & R_STATUS_TXQD_MASK; + data =3D FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / = 4); /* Clear TXFULL */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXFULL_MASK; - /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */ - ibex_spi_txfifo_reset(s); + data =3D FIELD_DP32(data, STATUS, TXFULL, 0); /* Reset RXEMPTY */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXEMPTY_MASK; + data =3D FIELD_DP32(data, STATUS, RXEMPTY, 0); + /* Update register status */ + s->regs[IBEX_SPI_HOST_STATUS] =3D data; + /* Drop remaining bytes that exceed segment_len */ + ibex_spi_txfifo_reset(s); =20 ibex_spi_host_irq(s); } @@ -340,7 +340,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, { IbexSPIHostState *s =3D opaque; uint32_t val32 =3D val64; - uint32_t shift_mask =3D 0xff; + uint32_t shift_mask =3D 0xff, data =3D 0, status =3D 0; uint8_t txqd_len; =20 trace_ibex_spi_host_write(addr, size, val64); @@ -397,21 +397,23 @@ static void ibex_spi_host_write(void *opaque, hwaddr = addr, s->regs[addr] =3D val32; =20 /* STALL, IP not enabled */ - if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) { + if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL], + CONTROL, SPIEN))) { return; } =20 /* SPI not ready, IRQ Error */ - if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) { + if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS], + STATUS, READY))) { s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=3D R_ERROR_STATUS_CMDBUS= Y_MASK; ibex_spi_host_irq(s); return; } + /* Assert Not Ready */ s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_READY_MASK; =20 - if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHI= FT) - !=3D BIDIRECTIONAL_TRANSFER) { + if (FIELD_EX32(val32, COMMAND, DIRECTION) !=3D BIDIRECTIONAL_TRANS= FER) { qemu_log_mask(LOG_UNIMP, "%s: Rx Only/Tx Only are not supported\n", __fun= c__); } @@ -452,8 +454,8 @@ static void ibex_spi_host_write(void *opaque, hwaddr ad= dr, return; } /* Byte ordering is set by the IP */ - if ((s->regs[IBEX_SPI_HOST_STATUS] & - R_STATUS_BYTEORDER_MASK) =3D=3D 0) { + status =3D s->regs[IBEX_SPI_HOST_STATUS]; + if (FIELD_EX32(status, STATUS, BYTEORDER) =3D=3D 0) { /* LE: LSB transmitted first (default for ibex processor) = */ shift_mask =3D 0xff << (i * 8); } else { @@ -464,18 +466,18 @@ static void ibex_spi_host_write(void *opaque, hwaddr = addr, =20 fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); } - + status =3D s->regs[IBEX_SPI_HOST_STATUS]; /* Reset TXEMPTY */ - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXEMPTY_MASK; + status =3D FIELD_DP32(status, STATUS, TXEMPTY, 0); /* Update TXQD */ - txqd_len =3D (s->regs[IBEX_SPI_HOST_STATUS] & - R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT; + txqd_len =3D FIELD_EX32(status, STATUS, TXQD); /* Partial bytes (size < 4) are padded, in words. */ txqd_len +=3D 1; - s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXQD_MASK; - s->regs[IBEX_SPI_HOST_STATUS] |=3D txqd_len; + status =3D FIELD_DP32(status, STATUS, TXQD, txqd_len); /* Assert Ready */ - s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_READY_MASK; + status =3D FIELD_DP32(status, STATUS, READY, 1); + /* Update register status */ + s->regs[IBEX_SPI_HOST_STATUS] =3D status; break; case IBEX_SPI_HOST_ERROR_ENABLE: s->regs[addr] =3D val32; --=20 2.37.1 From nobody Fri May 3 15:02:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660533574699908.1282452294029; Sun, 14 Aug 2022 20:19:34 -0700 (PDT) Received: from localhost ([::1]:43722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oNQdZ-0007df-M7 for importer@patchew.org; Sun, 14 Aug 2022 23:19:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oNQbz-0004Xt-Mr for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1660533467; x=1663125468; bh=DpUrOLtNTJGn6WeISd xZPFtJtbvXhcV5iwomnnWlCDE=; b=g7x70M0d0SVAeSmb7xRuccwp0Q+QA+SAvK v0f42pr2xYdlxFpRAP2itZ6iMHnssbejrEOBYMjefa34/lLOxrenK13oVM77EB/S gC2zkXojMKkZ8Y8hOqRt9dX+Y/7LLqW7izwHk5m+QSDMoHEpVj38bT659mkJlG1j Giw22wthJxB9ecLOQNIHUhWWsv2SYDpIbTuuayQiAMd5r/EatFIvDZzOfzuYY2ZB w9xkE7EuqrFuewjsfuwBClZYiyOs7htXCjsvgWMDuDExiyKeOpHnb2dsKKTueutt iicF1Wm8V+x1+354w4VU0yT+Syd8un2WKy0oyipGmQ4cSx71lt2g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa , Alistair Francis Subject: [PATCH v2 3/4] hw/ssi: ibex_spi: fixup/add rw1c functionality Date: Mon, 15 Aug 2022 13:16:24 +1000 Message-Id: <20220815031624.170857-4-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> References: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=219596703=wilfred.mallawa@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660533575257100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch adds the `rw1c` functionality to the respective registers. The status fields are cleared when the respective field is set. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 34 ++++++++++++++++++++++++++++++++-- include/hw/ssi/ibex_spi_host.h | 4 ++-- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index d377f1100c..19dd094d76 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -350,7 +350,17 @@ static void ibex_spi_host_write(void *opaque, hwaddr a= ddr, =20 switch (addr) { /* Skipping any R/O registers */ - case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: + case IBEX_SPI_HOST_INTR_STATE: + /* rw1c status register */ + if (FIELD_EX32(val32, INTR_STATE, ERROR)) { + data =3D FIELD_DP32(data, INTR_STATE, ERROR, 0); + } + if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) { + data =3D FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0); + } + s->regs[addr] =3D data; + break; + case IBEX_SPI_HOST_INTR_ENABLE: s->regs[addr] =3D val32; break; case IBEX_SPI_HOST_INTR_TEST: @@ -493,7 +503,27 @@ static void ibex_spi_host_write(void *opaque, hwaddr a= ddr, * When an error occurs, the corresponding bit must be cleared * here before issuing any further commands */ - s->regs[addr] =3D val32; + status =3D s->regs[addr]; + /* rw1c status register */ + if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) { + status =3D FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) { + status =3D FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0); + } + if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) { + status =3D FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0); + } + s->regs[addr] =3D status; break; case IBEX_SPI_HOST_EVENT_ENABLE: /* Controls which classes of SPI events raise an interrupt. */ diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h index 3fedcb6805..1f6d077766 100644 --- a/include/hw/ssi/ibex_spi_host.h +++ b/include/hw/ssi/ibex_spi_host.h @@ -40,7 +40,7 @@ OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST) =20 /* SPI Registers */ -#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */ +#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw1c */ #define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */ #define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */ #define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */ @@ -54,7 +54,7 @@ #define IBEX_SPI_HOST_TXDATA (0x28 / 4) =20 #define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */ -#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */ +#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw1c */ #define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */ =20 /* FIFO Len in Bytes */ --=20 2.37.1 From nobody Fri May 3 15:02:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1660533473; x=1663125474; bh=MdQobky66vKbHGU/y2 zi8zZA1scl005jHEY18jAZWQg=; b=saNCRPPmJf+X9QKgQUB35vObqRxbzAqT/r B1HaWcDHnwAG02MZ39FHlGB+bx7lsgJe5xTPEP88oip9iO4eHRt/zrMjuRQIf8TF S3FoQZmrmtDH95jR/KHQM95ja1YOt+WdkxpxebgmdE+Nj/eJMg70nhzeS2n8nxbP 2I4RdviqgjO0Rqe3oTxk7+tkbVIGpYT1VcDvFGmZpxc/x/oqmSABEKlaSOelEI2k CIlt2XC+BaqerZCP9CMn5RZex5z3ybWFH1HCVgBQ7u+kN9nW8kcY/8h7LrBqiW76 4MpuFsmsWCvCt5kFvqMQ+POeaUd5liAKU82ErD2RlY1yu/QCcKDQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Wilfred Mallawa To: Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa Subject: [PATCH v2 4/4] hw/ssi: ibex_spi: update reg addr Date: Mon, 15 Aug 2022 13:16:25 +1000 Message-Id: <20220815031624.170857-5-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> References: <20220815031624.170857-1-wilfred.mallawa@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=219596703=wilfred.mallawa@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660533669884100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa Updates the `EVENT_ENABLE` register to offset `0x34` as per OpenTitan spec [1]. [1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis --- hw/ssi/ibex_spi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 19dd094d76..3b8dcbce05 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -93,7 +93,7 @@ REG32(ERROR_STATUS, 0x30) FIELD(ERROR_STATUS, CMDINVAL, 3, 1) FIELD(ERROR_STATUS, CSIDINVAL, 4, 1) FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1) -REG32(EVENT_ENABLE, 0x30) +REG32(EVENT_ENABLE, 0x34) FIELD(EVENT_ENABLE, RXFULL, 0, 1) FIELD(EVENT_ENABLE, TXEMPTY, 1, 1) FIELD(EVENT_ENABLE, RXWM, 2, 1) --=20 2.37.1