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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b1-20020a05600c4e0100b003a2f6367049sm6633918wmq.48.2022.08.11.10.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 10:16:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=cLYZa9syzOzFbEHzRWobfZOnBIH37RGsYCkH7ST7i5w=; b=Yngm7okkwjvpniEmjAR1RtrXxlmoeVVzU+nCIbTLPa6upYUFbop0qjeyjI0cLsNtv1 29ggIuvn4p2IcNhKOW3rKuNOdteZJFbmo36Eoc3fri+A1Wj6pgahSgcjo/3ctCVIzjdA j1nk11HWA5gd3vpHJh6UWHmb204RsewVBLyRHG9hskpI4lMfSGXSmQtFEdbhousH00tZ 9h31ZUo2K/hjt7MPaCDksOhhdCH7Nun0zDo018hfIgRRRuvRp32gEmCiyPu+ann2tNuQ 5Nq8w6Ic5BC7+MfAD4QQax4EtcJDwoNB6clzz4v0vKAKoxX7FnjpaZ+Kjb1s6jBpia3O nBNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=cLYZa9syzOzFbEHzRWobfZOnBIH37RGsYCkH7ST7i5w=; b=OWQu6Aq8dlt1H7/hx0D5OukdUk7DmjLnnkMTiaq4kT389qhHCzmjMfpcN1ckgvqNLL xEsDX++AFQk5o8y8OL26da4yVCWFBbbUGe5GZL0AkU/y/AHZiVgzaNLAQHbe81UBg1Tj RwW2WpTw/PQz+a2mO0kp1s8r4KP+ecevWRkdPzz2PrEDv+IYjsBRTFH2KMelhzMDWpgg VCEtcZYPyteRykD6am1kawNedy9BEdPdOPW/PwFuXI+liXfO50mJ28SXY8ZSOk2dsqR2 jNAxXk6SNJdq+bzZIJ3KVz6djc57vZMk0XOhykdL4Cc7ym66LQPaJP4BUS3k/gktPofp xW8w== X-Gm-Message-State: ACgBeo13TN5NSnWYdCl76dw6FjTZFnRgDBvOcvqYvxvrdHsWZg1K6atj oXLypFCH/tWkb8CJbTu0N3rUpnXf7XRbZw== X-Google-Smtp-Source: AA6agR5rlQJpgHpXTLMT09rV8r+DRTrCr35Aq6L4kItzHni6mtK2pFYbdjMymfdjg7oxX6dr1uysIg== X-Received: by 2002:a5d:4204:0:b0:21f:a52f:a36e with SMTP id n4-20020a5d4204000000b0021fa52fa36emr25841wrq.458.1660238188219; Thu, 11 Aug 2022 10:16:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits Date: Thu, 11 Aug 2022 18:16:17 +0100 Message-Id: <20220811171619.1154755-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220811171619.1154755-1-peter.maydell@linaro.org> References: <20220811171619.1154755-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660238901073100001 Content-Type: text/plain; charset="utf-8" FEAT_PMUv3p5 introduces new bits MDCR_EL2.HCCD and MDCR_EL3.SCCD, which disable the cycle counter from counting at EL2 and EL3. Add the code to support these bits. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 20 ++++++++++++++++++++ target/arm/helper.c | 20 ++++++++++++++++---- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 122ec8a47ec..9e7fe64ceae 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1332,6 +1332,8 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) =20 +#define MDCR_MCCD (1ULL << 34) /* MDCR_EL3 */ +#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ @@ -3724,6 +3726,13 @@ static inline bool isar_feature_aa32_pmuv3p4(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 6 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; @@ -4048,6 +4057,12 @@ static inline bool isar_feature_aa64_pmuv3p4(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; @@ -4221,6 +4236,11 @@ static inline bool isar_feature_any_pmuv3p4(const AR= MISARegisters *id) return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); } =20 +static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); +} + static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) { return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); diff --git a/target/arm/helper.c b/target/arm/helper.c index 9507375b8e2..f601025cc40 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1084,8 +1084,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, * We use these to decide whether we need to wrap a write to MDCR_EL2 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. */ -#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN) -#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME) +#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR= _HCCD) +#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_MCCD) =20 /* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing * the current EL, security state, and register configuration. @@ -1120,8 +1120,20 @@ static bool pmu_counter_enabled(CPUARMState *env, ui= nt8_t counter) prohibited =3D prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); } =20 - if (prohibited && counter =3D=3D 31) { - prohibited =3D env->cp15.c9_pmcr & PMCRDP; + if (counter =3D=3D 31) { + /* + * The cycle counter defaults to running. PMCR.DP says "disable + * the cycle counter when event counting is prohibited". + * Some MDCR bits disable the cycle counter specifically. + */ + prohibited =3D prohibited && env->cp15.c9_pmcr & PMCRDP; + if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + if (el =3D=3D 3) { + prohibited =3D prohibited || (env->cp15.mdcr_el3 & MDCR_MC= CD); + } else if (el =3D=3D 2) { + prohibited =3D prohibited || (mdcr_el2 & MDCR_HCCD); + } + } } =20 if (counter =3D=3D 31) { --=20 2.25.1