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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b1-20020a05600c4e0100b003a2f6367049sm6633918wmq.48.2022.08.11.10.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 10:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc; bh=nkPgesIJ7tHWPAYMw0IGC2hbyuZcRqrKpcJIVrclGtI=; b=Qp1YDNqmw/vQSXL7KvulLGtEMi7O/ciUVbm5gTwIjEE4yH0ugw/VyyHh42KNGA6l1m AVUP7bp7mjSVDL8LdvwPdQRDuEsRNRzr2KcDddEZeKos6V49xbXBPKIwh76dfmcsd89H KUKy0vkmUuycTOfLiS7+pYC0Hoi73O9R6dW/Go5nA87Npq0wAAejYyezes3iTaLr8vhj a1/HeYXc+frzZMDJg7IGlgOcIniqh17IKSPSKILixDt68TKD5NspZlrcjnS2kY9HTdnj A7cBVmu1pC5S1prNTcQy4gxElXGMhKR2fU/rwfqf5YOdlhlf708cIUWtGrnHypIGUWnk uDdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc; bh=nkPgesIJ7tHWPAYMw0IGC2hbyuZcRqrKpcJIVrclGtI=; b=dSk8M3pCF17W5KjRL1f8LKzaztACfmFnsC+EDk59djyMLyLJMXlOAVOMJGBkXXFd0R MKCEuZYvqCqF89omQHdY85SKGAe0d7/DU22b/+gLuZ0jnjJlcli+kQ1JnJFUN1+AnpZI 2QveXDk3VI8ALw+R7yjhKN8UFgXDSKeJ+pn32WY+zPYvL6lzHhMJ8X5JACqNlq9DwMy/ U4kUv6n2qrXlepULcnaDrm2xQZKRaSrP767hJ6nNJZO0ZeRW6eRnwzuKfGEqPnSiUb9y P1FkE5GND5NmmtJGzqOpy2VhXeBDg13fPbW6E+zSY5yDUZZon0+cgFeFLVaMYLVFE+Ha KFmg== X-Gm-Message-State: ACgBeo0lz88VAVXjYk/+HgDbZBFs/WJ5iG7yYqgZOp2oMLO2jgebO5+x 3OIMz5o3YoTmiKFap45WBCWqmpr1s+LfQw== X-Google-Smtp-Source: AA6agR6dW5Si8i+KY6Md0lHNlyrB0uRyi3L7oZfc2ny9ek6L/Du4GMX2vW2Y+eMBWnzELYZpFPVbcA== X-Received: by 2002:a5d:4907:0:b0:21f:bc42:989 with SMTP id x7-20020a5d4907000000b0021fbc420989mr7445wrq.375.1660238184570; Thu, 11 Aug 2022 10:16:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/10] target/arm: Ignore PMCR.D when PMCR.LC is set Date: Thu, 11 Aug 2022 18:16:13 +0100 Message-Id: <20220811171619.1154755-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220811171619.1154755-1-peter.maydell@linaro.org> References: <20220811171619.1154755-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1660238873444100001 Content-Type: text/plain; charset="utf-8" The architecture requires that if PMCR.LC is set (for a 64-bit cycle counter) then PMCR.D (which enables the clock divider so the counter ticks every 64 cycles rather than every cycle) should be ignored. We were always honouring PMCR.D; fix the bug so we correctly ignore it in this situation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a367371921..41def52cf7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1172,6 +1172,17 @@ static void pmu_update_irq(CPUARMState *env) (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } =20 +static bool pmccntr_clockdiv_enabled(CPUARMState *env) +{ + /* + * Return true if the clock divider is enabled and the cycle counter + * is supposed to tick only once every 64 clock cycles. This is + * controlled by PMCR.D, but if PMCR.LC is set to enable the long + * (64-bit) cycle counter PMCR.D has no effect. + */ + return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) =3D=3D PMCRD; +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1184,8 +1195,7 @@ static void pmccntr_op_start(CPUARMState *env) =20 if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles =3D cycles; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ + if (pmccntr_clockdiv_enabled(env)) { eff_cycles /=3D 64; } =20 @@ -1228,8 +1238,7 @@ static void pmccntr_op_finish(CPUARMState *env) #endif =20 uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ + if (pmccntr_clockdiv_enabled(env)) { prev_cycles /=3D 64; } env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; --=20 2.25.1