From nobody Tue Apr 30 13:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1660018761; cv=none; d=zohomail.com; s=zohoarc; b=GBovCcamErk5pgBKAMmqK2FEbV5EatqTSBxFLWR34woST5sr2C3SBiqZzF/4xF+gWePXpnnhoLwAmgdiGpCOnBMDzWOiFg1mwztoZa6hqXP2N83E5v4xBolWa0CcxhjTNJbuFTia9M9NIFsH1iwun0Watf18oA2GMG/G3XIQzFU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660018761; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gHX3AQgs74fUz96oz6+lxFeZi05SpyH8+P6/Mg5Op8I=; b=ikBll8SOEtGilcz0dQG0lmN95p4VeyrPXiyKRtiFbf+8AEAICNLTa18x6OIlq/rwG3yJnPkDNrTIqtlVNENuvCmXarRA9uVlKDoHdjesTy4lJFALnLoUh/qfiI5z8lArGvJ51WOUr2ueqIbmNAcWZI+HTjgegvLn9Yw/7JFCj28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660018761212565.0847604196833; Mon, 8 Aug 2022 21:19:21 -0700 (PDT) Received: from localhost ([::1]:32914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oLGi7-0001CK-Qk for importer@patchew.org; Tue, 09 Aug 2022 00:19:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oLGfs-0006kh-Hq for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:00 -0400 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]:43728) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oLGfq-0004Zm-7h for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:00 -0400 Received: by mail-ot1-x32e.google.com with SMTP id cm4-20020a056830650400b0063675a4dd74so7778786otb.10 for ; Mon, 08 Aug 2022 21:16:57 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id g15-20020a9d648f000000b0061c9ccb051bsm2712738otl.37.2022.08.08.21.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Aug 2022 21:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=gHX3AQgs74fUz96oz6+lxFeZi05SpyH8+P6/Mg5Op8I=; b=nf9tTOCeMObUUguOWDqkrAdqsK73Yu6jmM6bLiBrgLF57d+OGDvXAkjrSrIZTgtsKJ QNP2dE9+43rYmF0mvguHI0kvMu0wLb0UFSiiZm0JwQTP+NLxS9QLrr2lIEDinisZXZ3M RzNELwnuUmo4t4gCPxsh1zIMel3lICWuXmqlRjD/aPujd4vVMTkcNT1wHshVCggyt2cH NyeppxaPHlsWm+moVRpCOO67BKQCxKfU91T6BiQ4OOPeuAPFwFD0bwiy8KCM3x1ji+C8 rfYAgXhh3hZgxLZE3KXjLY12Pn5ifJRqAhttcNIUSiHbwAU5KHphtamiSmz1Qdbe2vi/ nGlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=gHX3AQgs74fUz96oz6+lxFeZi05SpyH8+P6/Mg5Op8I=; b=kKkVwZPQgEC7W38kuN0g9Wx7q6MVHnoPkc6AQy4VM6gyGnt1dg5PZxYxHozEcR7F51 bTi4S0D13qH48SGfAfDQYtjLHXGAqf27tE8ft8WDuITToqEhco0lgwU251Qufbe3iLc0 G9UmnPbNCQeCaG1/KWxfs4rAkfPhHTyRblw37+z9rEXAN4JzSXb86KZueQ8o2veZQuhK SnCXMJPJc12/irjEbgydVMG4b1a2yA/Mf0b/wv3hvfobghHq1Q0kju/kyx/6Yza/TOi4 flUu/ZSfbxlFMhgPQoIw+FT7LKt/fgbw+wrdeyyXfRQ1o+XwNkm0Kkf/FB3PplVxrw8z zP2Q== X-Gm-Message-State: ACgBeo0ZUm/nKtByQ1ifPo4SbuvenAo7w3EItt9v1KxWsLi66FFDMGIo TnD9oSQ0AViRneQC9ED9VL57PcGoUbxWkg== X-Google-Smtp-Source: AA6agR6cft/07ELn90QPmr2Zku34ul3+yI1Gp+yEN0ra8pHy2M8OOoRzm3X8sYJnCKnxKC+DWfqFJA== X-Received: by 2002:a05:6830:43a0:b0:61c:c25b:eb88 with SMTP id s32-20020a05683043a000b0061cc25beb88mr8088646otv.111.1660018616613; Mon, 08 Aug 2022 21:16:56 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [PATCH v8 1/4] target/riscv: Add smstateen support Date: Tue, 9 Aug 2022 09:46:40 +0530 Message-Id: <20220809041643.124888-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220809041643.124888-1-mchitale@ventanamicro.com> References: <20220809041643.124888-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=mchitale@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1660018762852100001 Content-Type: text/plain; charset="utf-8" Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 37 ++++ target/riscv/csr.c | 373 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 21 +++ 4 files changed, 435 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4be4b82a83..6bff935c57 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -354,6 +354,9 @@ struct CPUArchState { =20 /* CSRs for execution enviornment configuration */ uint64_t menvcfg; + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; target_ulong senvcfg; uint64_t henvcfg; #endif @@ -427,6 +430,7 @@ struct RISCVCPUConfig { bool ext_ifencei; bool ext_icsr; bool ext_zihintpause; + bool ext_smstateen; bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6be5a9e9f0..c773e0d310 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -199,6 +199,12 @@ /* Supervisor Configuration CSRs */ #define CSR_SENVCFG 0x10A =20 +/* Supervisor state CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -242,6 +248,16 @@ #define CSR_HENVCFG 0x60A #define CSR_HENVCFGH 0x61A =20 +/* Hypervisor state CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -283,6 +299,27 @@ #define CSR_MENVCFG 0x30A #define CSR_MENVCFGH 0x31A =20 +/* Machine state CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Common defines for all smstateen */ +#define SMSTATEEN_MAX_COUNT 4 +#define SMSTATEEN0_CS (1ULL << 0) +#define SMSTATEEN0_FCSR (1ULL << 1) +#define SMSTATEEN0_HSCONTXT (1ULL << 57) +#define SMSTATEEN0_IMSIC (1ULL << 58) +#define SMSTATEEN0_AIA (1ULL << 59) +#define SMSTATEEN0_SVSLCT (1ULL << 60) +#define SMSTATEEN0_HSENVCFG (1ULL << 62) +#define SMSTATEEN_STATEEN (1ULL << 63) + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d81f466c80..d5761996ba 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -346,6 +346,72 @@ static RISCVException umode32(CPURISCVState *env, int = csrno) return umode(env, csrno); } =20 +static RISCVException mstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + +static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int bas= e) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv < PRV_M) { + if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return hmode(env, csrno); +} + +static RISCVException hstateen(CPURISCVState *env, int csrno) +{ + return hstateen_pred(env, csrno, CSR_HSTATEEN0); +} + +static RISCVException hstateenh(CPURISCVState *env, int csrno) +{ + return hstateen_pred(env, csrno, CSR_HSTATEEN0H); +} + +static RISCVException sstateen(CPURISCVState *env, int csrno) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + int index =3D csrno - CSR_SSTATEEN0; + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv < PRV_M) { + if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + } + + return smode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -1706,6 +1772,263 @@ static RISCVException write_henvcfgh(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, + uint64_t wr_mask, uint64_t new_val) +{ + *reg =3D (*reg & ~wr_mask) | (new_val & wr_mask); +} + +static RISCVException read_mstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen(CPURISCVState *env, int csrno, + uint64_t wr_mask, target_ulong new_va= l) +{ + uint64_t *reg; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_mstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_mstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, + uint64_t wr_mask, target_ulong new_v= al) +{ + uint64_t *reg, val; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_mstateenh(env, csrno, wr_mask, new_val); +} + +static RISCVException write_mstateen1h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen2h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen3h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_hstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D csrno - CSR_HSTATEEN0; + + *val =3D env->hstateen[index] & env->mstateen[index]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + int index =3D csrno - CSR_HSTATEEN0; + uint64_t *reg, wr_mask; + + reg =3D &env->hstateen[index]; + wr_mask =3D env->mstateen[index] & mask; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_hstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_hstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D csrno - CSR_HSTATEEN0H; + + *val =3D (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + int index =3D csrno - CSR_HSTATEEN0H; + uint64_t *reg, wr_mask, val; + + reg =3D &env->hstateen[index]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + wr_mask =3D env->mstateen[index] & mask; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_hstateenh(env, csrno, wr_mask, new_val); +} + +static RISCVException write_hstateen1h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen2h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen3h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_sstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + int index =3D csrno - CSR_SSTATEEN0; + + *val =3D env->sstateen[index] & env->mstateen[index]; + if (virt) { + *val &=3D env->hstateen[index]; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + int index =3D csrno - CSR_SSTATEEN0; + uint64_t wr_mask; + uint64_t *reg; + + wr_mask =3D env->mstateen[index] & mask; + if (virt) { + wr_mask &=3D env->hstateen[index]; + } + + reg =3D &env->sstateen[index]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_sstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_sstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_sstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_sstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3575,6 +3898,56 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 + /* Smstateen extension CSRs */ + [CSR_MSTATEEN0] =3D { "mstateen0", mstateen, read_mstateen, write_msta= teen0, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN0H] =3D { "mstateen0h", mstateen, read_mstateenh, + write_mstateen0h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1] =3D { "mstateen1", mstateen, read_mstateen, write_msta= teen1, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1H] =3D { "mstateen1h", mstateen, read_mstateenh, + write_mstateen1h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2] =3D { "mstateen2", mstateen, read_mstateen, write_msta= teen2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2H] =3D { "mstateen2h", mstateen, read_mstateenh, + write_mstateen2h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3] =3D { "mstateen3", mstateen, read_mstateen, write_msta= teen3, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3H] =3D { "mstateen3h", mstateen, read_mstateenh, + write_mstateen3h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0] =3D { "hstateen0", hstateen, read_hstateen, write_hsta= teen0, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0H] =3D { "hstateen0h", hstateenh, read_hstateenh, + write_hstateen0h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1] =3D { "hstateen1", hstateen, read_hstateen, write_hsta= teen1, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1H] =3D { "hstateen1h", hstateenh, read_hstateenh, + write_hstateen1h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2] =3D { "hstateen2", hstateen, read_hstateen, write_hsta= teen2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2H] =3D { "hstateen2h", hstateenh, read_hstateenh, + write_hstateen2h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3] =3D { "hstateen3", hstateen, read_hstateen, write_hsta= teen3, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3H] =3D { "hstateen3h", hstateenh, read_hstateenh, + write_hstateen3h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN0] =3D { "sstateen0", sstateen, read_sstateen, write_ssta= teen0, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN1] =3D { "sstateen1", sstateen, read_sstateen, write_ssta= teen1, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN2] =3D { "sstateen2", sstateen, read_sstateen, write_ssta= teen2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN3] =3D { "sstateen3", sstateen, read_sstateen, write_ssta= teen3, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index dc182ca811..ef418ac19d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -262,6 +262,26 @@ static int riscv_cpu_post_load(void *opaque, int versi= on_id) return 0; } =20 +static bool smstateen_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_smstateen; +} + +static const VMStateDescription vmstate_smstateen =3D { + .name =3D "cpu/smtateen", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D smstateen_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), + VMSTATE_END_OF_LIST() + } +}; + static bool envcfg_needed(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -372,6 +392,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_kvmtimer, &vmstate_envcfg, &vmstate_debug, + &vmstate_smstateen, NULL } }; --=20 2.25.1 From nobody Tue Apr 30 13:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1660018767; cv=none; d=zohomail.com; s=zohoarc; b=gzKYQjGNsSMq76mUPl315SGxbgJs3LEpktHbOQpP2QLSXsuxNp3kCCUn77uZzk0GamCLibhxtFFFPYrsckNboyhCcH+mp/Mj33nHdJivOUSHtKjclx4v38AsupSxesZyD0Ab/A8K3AXCX0tP2eLooAGXGgPdaNKNjswIBB0nPIo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660018767; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6VS+6hSiE9qBG72L+hE7gB3Y7Tt/y3Jtoyf/Aepz/Iw=; b=ZL7goU5EARufBx9XBT3ujwAEpyiiksDlyyyhVru5gbCxuTqNFynHY6afxtmdNF+fZMKNHhag/bdfPWbbf0wd2BymZkxoW6FA2AiOjOo3fNX5war1kPYzp9ZA704RWMUW2Dc9IOMcgWRW2Qxf6lj1A1BzQHYi0uinYbkVMVLdt4g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660018767184963.6610506650289; Mon, 8 Aug 2022 21:19:27 -0700 (PDT) Received: from localhost ([::1]:33518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oLGiE-0001af-6B for importer@patchew.org; Tue, 09 Aug 2022 00:19:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oLGfu-0006od-IS for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:02 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]:40844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oLGfs-0004ZO-Nj for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:02 -0400 Received: by mail-oi1-x230.google.com with SMTP id c185so12610636oia.7 for ; Mon, 08 Aug 2022 21:17:00 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id g15-20020a9d648f000000b0061c9ccb051bsm2712738otl.37.2022.08.08.21.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Aug 2022 21:16:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=6VS+6hSiE9qBG72L+hE7gB3Y7Tt/y3Jtoyf/Aepz/Iw=; b=BlDNhf26JopcSyYRVR1ZZ2tAs21HMJgN5tI92PpsgkehM8+tvuJJdEk/82jX/q024R T+46oz/+Hh6Hohjo8Q1WPQtsbvuhgCld3W6y3gSMaxZIZvGuthXLRMi5YimTZvw499KZ 6WoGt213JA7tq+zjYkJzIdRA6jGjnbEA9n6U7mLfQQlZSVv5N6oa8hUimzGjWoC+ydwZ NeIv4xu0X75/j4a36/oXeZIuCwiFKWgzD7TfZT9JV8RGeftK7dp/yt8PeZOFs61tMJdW M6rC3f5YKdC/lu3X+pL3SHbenG9gR9TR6krsJBPfG3jY9m7SnTosT44EB61WAg8+vf5s YVgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=6VS+6hSiE9qBG72L+hE7gB3Y7Tt/y3Jtoyf/Aepz/Iw=; b=pyOO3sM7QAf2vBC5gSIn28AWL6Th3ZPAVIfQ4H2WXvNKTh5gGDdosh4KbSMjMMGYji fniX4/1H4gIRfRrcma2Xblob2Bfklnw8E26AB5j6/5vh1/gF5pRIa5VDP+YQzimI+84n D8uahwHQ7kqibkI51JRDHjNaFMn7fH4NL+FR5SEuxhDi2qQdScPBRMPAppkrUS0KzXiU qNO1Cm78b9ZpGGESKLTolcTLv5bEuIemEeMBc2ljVNkxHMt62LgHW2YKy0rknHCDa5u/ V+0Gh5b5D5rG7jn8w5l84OSxORSD/s9jdAZDoPPQkd3loZE/Y5bTlDkaPAp+y2nFzkur oeXw== X-Gm-Message-State: ACgBeo3t9UV49wAz0tLcp0OXNjEep7VFKgZlqyMStHT+jx4RK7C1AMx4 lJe5u6sRoTdnZgxT56jS+vzaLg4U1cMYRA== X-Google-Smtp-Source: AA6agR5Wh0pB68HauvJbUxV2ei6a0mjPhV++op2qPyI0/PqaqFi4BgSrIbLfyYrfa+darGEgx67Xew== X-Received: by 2002:a05:6808:210d:b0:343:1027:2e63 with SMTP id r13-20020a056808210d00b0034310272e63mr655801oiw.228.1660018619757; Mon, 08 Aug 2022 21:16:59 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [PATCH v8 2/4] target/riscv: smstateen check for h/s/envcfg Date: Tue, 9 Aug 2022 09:46:41 +0530 Message-Id: <20220809041643.124888-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220809041643.124888-1-mchitale@ventanamicro.com> References: <20220809041643.124888-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=mchitale@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1660018768831100001 Content-Type: text/plain; charset="utf-8" Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the correspon= ding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction tra= p is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 87 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 80 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d5761996ba..d8383c7307 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -40,6 +40,42 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *= ops) } =20 /* Predicates */ +#if !defined(CONFIG_USER_ONLY) +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, + uint64_t bit) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (env->priv =3D=3D PRV_M || !cpu->cfg.ext_smstateen) { + return RISCV_EXCP_NONE; + } + + if (!(env->mstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + if (env->priv =3D=3D PRV_U && !(env->sstateen[index] & bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if (env->priv =3D=3D PRV_U && riscv_has_ext(env, RVS)) { + if (!(env->sstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return RISCV_EXCP_NONE; +} +#endif + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1719,6 +1755,13 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, static RISCVException read_senvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->senvcfg; return RISCV_EXCP_NONE; } @@ -1727,15 +1770,27 @@ static RISCVException write_senvcfg(CPURISCVState *= env, int csrno, target_ulong val) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + RISCVException ret; =20 - env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } =20 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg; return RISCV_EXCP_NONE; } @@ -1744,6 +1799,12 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D HENVCFG_PBMTE | HENVCFG_STCE; @@ -1757,6 +1818,13 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg >> 32; return RISCV_EXCP_NONE; } @@ -1766,9 +1834,14 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, { uint64_t mask =3D HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh =3D (uint64_t)val << 32; + RISCVException ret; =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); return RISCV_EXCP_NONE; } =20 @@ -1800,7 +1873,7 @@ static RISCVException write_mstateen(CPURISCVState *e= nv, int csrno, static RISCVException write_mstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_mstateen(env, csrno, wr_mask, new_val); } @@ -1847,7 +1920,7 @@ static RISCVException write_mstateenh(CPURISCVState *= env, int csrno, static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_mstateenh(env, csrno, wr_mask, new_val); } @@ -1896,7 +1969,7 @@ static RISCVException write_hstateen(CPURISCVState *e= nv, int csrno, static RISCVException write_hstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_hstateen(env, csrno, wr_mask, new_val); } @@ -1947,7 +2020,7 @@ static RISCVException write_hstateenh(CPURISCVState *= env, int csrno, static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_hstateenh(env, csrno, wr_mask, new_val); } @@ -2006,7 +2079,7 @@ static RISCVException write_sstateen(CPURISCVState *e= nv, int csrno, static RISCVException write_sstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_sstateen(env, csrno, wr_mask, new_val); } --=20 2.25.1 From nobody Tue Apr 30 13:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1660018960; cv=none; d=zohomail.com; s=zohoarc; b=jIu7tuV4WkgetRSWkWUytfQjCIpjHZzJTmgOf1P67lPcZPyP1Ji1cWxHcOj3iA2mjJ4JdGh8hWbkRnDUef8K3jJFeJ9Inf8WXIdmj1Q/Ltl/r2xo67BsBohmyYYFUpVPb7XMFooYqpzmbwxWOBzmxyF4xAQ5BrssYX4mmEs4npg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660018960; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BMmxFsyDj+c8vZq8bg2cbIWWNModRnAwN84nUo3Lk30=; b=kMuqr4mowoABXMePD3d+dsiH4R147ZiUEhuIi/pN1qCqyNeX9ulQglcsiWAeFkF8oqJ3Z8dQ26PeHed4pvqmN9d9ZSR0iBn6dLD303JEZurvTwgQu0cG8EBK4qnAzp/kND0ZBCsIUXg1GXnl23zZDnveP37cYGE9fxI9bmxuybM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660018960731841.9814553349115; Mon, 8 Aug 2022 21:22:40 -0700 (PDT) Received: from localhost ([::1]:39110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oLGlK-0005PU-Jy for importer@patchew.org; Tue, 09 Aug 2022 00:22:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oLGfy-0006qY-PF for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:06 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]:38830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oLGfw-0004aT-Bn for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:06 -0400 Received: by mail-ot1-x333.google.com with SMTP id cb12-20020a056830618c00b00616b871cef3so7806746otb.5 for ; Mon, 08 Aug 2022 21:17:04 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id g15-20020a9d648f000000b0061c9ccb051bsm2712738otl.37.2022.08.08.21.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Aug 2022 21:17:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=BMmxFsyDj+c8vZq8bg2cbIWWNModRnAwN84nUo3Lk30=; b=OR7Lv9yHQNlNKk8enRl5INE+liz4LJnYErCXBA29oCwfUeK+bYGpH6KpMwRP4rN081 1W+3+DHQg4FDM09nBYfxNQmBKU09tPA3GBpy5lhY1XvOUL9imbaUcB3CJjlTVVkRJvVU ppkFozAv/aLYuOWkBLPqz4jhCqWx8xNjH+b3fmZXFaHCEj8aov4pbFjzkB85TsOXXeGD VjtlPp76dAr4RGAqckr66LeuyG/ZjZyonf2J4BzR43VZ5LkLUoECDIGaaaFUHiE8uSCf Rbhh/FX70os/3Rc/jojFpkLIwGICdQVOCsSpWemHdHd879W/d+R+f31ly2qzI5xYfc29 Atsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=BMmxFsyDj+c8vZq8bg2cbIWWNModRnAwN84nUo3Lk30=; b=SVcFHn22MYqmtKnQJNjFXgdaBR9/skm4e2ogvpVUjB1w2KAK/aigSI2EUgSfIsKXDS 0J5k9McNWhRxpuEeJSY3k4fyi9Y1FY3qwWstPjfmkK5O3KHcydseMTmW12HqD5X7IgRy LkGVC7l7CCpipuJhINLKj9/2ombrWjaa/+LTwaseEinqz3zNG6X7isGjOTWYvHb+k8Zv By9LKCWFSXsZjfCasrHLoNPgyWjhq4iArmqwUBPuGkzSkNjkcoE/5hEhqQ8Bvi42JVZ/ e6On7ZHpyzZXxrTNK+0zcbkLCRwpVOskCW+9zz9EqeyEEeRPYwFp6RHEqqjDr6qh0FbY IhNw== X-Gm-Message-State: ACgBeo014gGHdV3XHN3lKVrG/6NncpZmmCuxPpNtvFPB5fm+VFbEcC4r yk/UFh19MzV68oIk4Jc5DyF0QEhF9BoNFg== X-Google-Smtp-Source: AA6agR6HFEXRnNzcxy8RDUnZukd7K4UYFvgl6VL31BiPPnKea2U6OzMGoQl5Ing70abUVMkbObpJMQ== X-Received: by 2002:a05:6830:925:b0:61d:1f55:57ce with SMTP id v37-20020a056830092500b0061d1f5557cemr7919341ott.78.1660018623013; Mon, 08 Aug 2022 21:17:03 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [PATCH v8 3/4] target/riscv: smstateen check for fcsr Date: Tue, 9 Aug 2022 09:46:42 +0530 Message-Id: <20220809041643.124888-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220809041643.124888-1-mchitale@ventanamicro.com> References: <20220809041643.124888-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=mchitale@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1660018962750100001 Content-Type: text/plain; charset="utf-8" If smstateen is implemented and sstateen0.fcsr is clear then the floating p= oint operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 23 +++++++++++++ target/riscv/insn_trans/trans_rvf.c.inc | 40 +++++++++++++++++++++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ 3 files changed, 72 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d8383c7307..a62081ab2d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -83,6 +83,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -1874,6 +1878,9 @@ static RISCVException write_mstateen0(CPURISCVState *= env, int csrno, target_ulong new_val) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } =20 return write_mstateen(env, csrno, wr_mask, new_val); } @@ -1922,6 +1929,10 @@ static RISCVException write_mstateen0h(CPURISCVState= *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } =20 @@ -1971,6 +1982,10 @@ static RISCVException write_hstateen0(CPURISCVState = *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_hstateen(env, csrno, wr_mask, new_val); } =20 @@ -2022,6 +2037,10 @@ static RISCVException write_hstateen0h(CPURISCVState= *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_hstateenh(env, csrno, wr_mask, new_val); } =20 @@ -2081,6 +2100,10 @@ static RISCVException write_sstateen0(CPURISCVState = *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_sstateen(env, csrno, wr_mask, new_val); } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index a1d3eb52ad..ce8a0cc34b 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -24,9 +24,43 @@ return false; \ } while (0) =20 -#define REQUIRE_ZFINX_OR_F(ctx) do {\ - if (!ctx->cfg_ptr->ext_zfinx) { \ - REQUIRE_EXT(ctx, RVF); \ +#ifndef CONFIG_USER_ONLY +static inline bool smstateen_check(DisasContext *ctx, int index) +{ + CPUState *cpu =3D ctx->cs; + CPURISCVState *env =3D cpu->env_ptr; + uint64_t stateen =3D env->mstateen[index]; + + if (!ctx->cfg_ptr->ext_smstateen || env->priv =3D=3D PRV_M) { + return true; + } + + if (ctx->virt_enabled) { + stateen &=3D env->hstateen[index]; + } + + if (env->priv =3D=3D PRV_U && has_ext(ctx, RVS)) { + stateen &=3D env->sstateen[index]; + } + + if (!(stateen & SMSTATEEN0_FCSR)) { + return false; + } + + return true; +} +#else +#define smstateen_check(ctx, index) (true) +#endif + +#define REQUIRE_ZFINX_OR_F(ctx) do { \ + if (!has_ext(ctx, RVF)) { \ + if (!ctx->cfg_ptr->ext_zfinx) { \ + return false; \ + } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } \ } while (0) =20 diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 5d07150cd0..44d962c920 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -20,18 +20,27 @@ if (!ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 #define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ @@ -39,6 +48,9 @@ ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 static bool trans_flh(DisasContext *ctx, arg_flh *a) --=20 2.25.1 From nobody Tue Apr 30 13:03:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1660018774; cv=none; d=zohomail.com; s=zohoarc; b=FoJHUs/Ggls+nhGML+Z9z1Ty3QVllqXx1FmD1TTg3tRth4zPBPGCw5991xJQGPdyhW8/wOZQF/yMn+bQ0cmaEgoJhFa3W1GNXZ7GEQx2/5GzrvF+iOcPm+pVCYzAtHMGs6NpPGsUyqttTwXL8X/5+s1CacPNSquaqGDX649MJzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660018774; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/6PKI0QUD/9+yYYe7TmpMU06G0Kr05B5w6N+00Yhr4M=; b=KZY7XQeaxCVV6NOqb3gyUhQsGx0vjhEadTNSVqynrscDGI9spx6K/K6KDwx1WBYjXrSf0Zl1pk1r5tp+J4MhnnHq7A1yn3Yvmt5sFSLRPgfSyPVmRVUEiBv9XR51gFnwgAVn/ehMtHAc4m4xxvN13BD/lRQ73LErp4mgLE+CMvc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660018774570180.3279767001709; Mon, 8 Aug 2022 21:19:34 -0700 (PDT) Received: from localhost ([::1]:33714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oLGiL-0001iF-Hi for importer@patchew.org; Tue, 09 Aug 2022 00:19:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oLGg1-0006xr-4m for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:09 -0400 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]:41972) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oLGfz-0004ap-Iw for qemu-devel@nongnu.org; Tue, 09 Aug 2022 00:17:08 -0400 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-10ea30a098bso12732317fac.8 for ; Mon, 08 Aug 2022 21:17:07 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id g15-20020a9d648f000000b0061c9ccb051bsm2712738otl.37.2022.08.08.21.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Aug 2022 21:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=/6PKI0QUD/9+yYYe7TmpMU06G0Kr05B5w6N+00Yhr4M=; b=SRWrWnpLYToiJN677yUU06TNWNUZTMMzZLITpRKIbOakokRBcNH3q1vy5x12N3eoNd Fcxo9nHvItLEUd2RtQtVgPTawtQNg9owl1ZkkujMAyF0w3HCOLYHtHAtz05BdiWhRcbI Xy4DuX8YYCjkwSRsy89sACIbyuLyAC98nemcHdajffyHljGcL9Cvdw1OKRHEe52OHJYv /Vt6Nn7BLWeuksHlNymSA2HZEx1fDpA7SayquhyhgEwRkeBDMOpyg6Eqyv9oZQ78wg/P k9WQTygmSWucyCMzNqOoEgkloBhMSLWhI9RqfNy3QjLfF+UVViJjjOvm/9yahwG+GQEE W8ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=/6PKI0QUD/9+yYYe7TmpMU06G0Kr05B5w6N+00Yhr4M=; b=R/kvj8HUf4bpRgh204RgJBnosCX5HEHQ58fRaPV4XgE4bSTCLw29T5IKLTkYzPgM4+ /klcZF5+FlyWHzgjKStm3gzHdP4RzYH8N7w2sc0ex60gLHymtDVJ+NyH69ACDXItISXM uP38vb5MpXW/BC9znfsegaDZbDS6zVQIgoPBKdJztfVSBnwQSuiy6Q9GKZ2lqbaNgWoz 4ebX0B7HD98SWfc5OFPTThAGJGKCq1OpcpdYJCRF9xHZSpJ7aaRL1B9GFkFeDFnX7b1b 3IfyWd2L4EDssWYYUmhk39XFlGRJEqh64eBMIiD4WpBND3Hodw689Bav/QMLI9nFVWkt 0psg== X-Gm-Message-State: ACgBeo2cfKZU1MmlOtU555eSxZ9jXs6wrW1hzKD02j7n3l94La6Sp7Xz Ld9Xi2o0NqvWjWRDjeIaubzSyUceWlc81Q== X-Google-Smtp-Source: AA6agR7C36NQ6nipu4XJ4x4bZAYyM/KkOiYWjt7gNU8MP1ttlSUiLJZzKh5creAQPV6DMpTMOG6tkw== X-Received: by 2002:a05:6870:f20c:b0:10e:e5e3:dac2 with SMTP id t12-20020a056870f20c00b0010ee5e3dac2mr10327621oao.228.1660018626103; Mon, 08 Aug 2022 21:17:06 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [PATCH v8 4/4] target/riscv: smstateen knobs Date: Tue, 9 Aug 2022 09:46:43 +0530 Message-Id: <20220809041643.124888-5-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220809041643.124888-1-mchitale@ventanamicro.com> References: <20220809041643.124888-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1660018774859100001 Content-Type: text/plain; charset="utf-8" Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4635c7df4..d8a0f4e700 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -99,6 +99,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smstateen, true, PRIV_VERSION_1_12_0, ext_smstateen= ), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), @@ -1001,6 +1002,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), --=20 2.25.1