From nobody Mon Feb 9 18:46:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659955355155389.24313241893253; Mon, 8 Aug 2022 03:42:35 -0700 (PDT) Received: from localhost ([::1]:53566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oL0DR-000318-TV for importer@patchew.org; Mon, 08 Aug 2022 06:42:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKzzQ-0005Fg-Co; Mon, 08 Aug 2022 06:28:04 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:36959 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKzzO-0001Qo-5L; Mon, 08 Aug 2022 06:28:04 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4M1XTY0t3Rz4xV7; Mon, 8 Aug 2022 20:28:01 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4M1XTW0fqRz4xTy; Mon, 8 Aug 2022 20:27:58 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v3 07/22] ppc/ppc405: QOM'ify CPU Date: Mon, 8 Aug 2022 12:27:19 +0200 Message-Id: <20220808102734.133084-8-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220808102734.133084-1-clg@kaod.org> References: <20220808102734.133084-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=c6th=YM=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1659955358168100001 Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC realize routine. We will clean that up in the following patches. ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe this could be done in model initializer of the CPU families needing it. Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405.h | 2 +- include/hw/ppc/ppc4xx.h | 1 + hw/ppc/ppc405_boards.c | 2 +- hw/ppc/ppc405_uc.c | 35 +++++++++++++++++++++++++---------- hw/ppc/ppc4xx_devs.c | 2 +- 5 files changed, 29 insertions(+), 13 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index dc862bc8614c..8cc76cc8b3fe 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -79,7 +79,7 @@ struct Ppc405SoCState { hwaddr ram_size; =20 uint32_t sysclk; - PowerPCCPU *cpu; + PowerPCCPU cpu; DeviceState *uic; }; =20 diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 980f964b5a91..021376c2d260 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -29,6 +29,7 @@ #include "exec/memory.h" =20 /* PowerPC 4xx core initialization */ +void ppc4xx_reset(void *opaque); PowerPCCPU *ppc4xx_init(const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 0b39ff08bd65..5ba12d60bc00 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -313,7 +313,7 @@ static void ppc405_init(MachineState *machine) =20 /* Load ELF kernel and rootfs.cpio */ } else if (kernel_filename && !machine->firmware) { - boot_from_kernel(machine, ppc405->soc.cpu); + boot_from_kernel(machine, &ppc405->soc.cpu); } } =20 diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index abcc2537140c..fa3853df2233 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1432,22 +1432,36 @@ static void ppc405ep_cpc_init (CPUPPCState *env, cl= k_setup_t clk_setup[8], #endif } =20 +static void ppc405_soc_instance_init(Object *obj) +{ + Ppc405SoCState *s =3D PPC405_SOC(obj); + + object_initialize_child(obj, "cpu", &s->cpu, + POWERPC_CPU_TYPE_NAME("405ep")); +} + static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; + clk_setup_t clk_setup[PPC405EP_CLK_NB]; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; CPUPPCState *env; =20 memset(clk_setup, 0, sizeof(clk_setup)); =20 /* init CPUs */ - s->cpu =3D ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), - &clk_setup[PPC405EP_CPU_CLK], - &tlb_clk_setup, s->sysclk); - env =3D &s->cpu->env; - clk_setup[PPC405EP_CPU_CLK].cb =3D tlb_clk_setup.cb; - clk_setup[PPC405EP_CPU_CLK].opaque =3D tlb_clk_setup.opaque; + if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { + return; + } + qemu_register_reset(ppc4xx_reset, &s->cpu); + + env =3D &s->cpu.env; + + clk_setup[PPC405EP_CPU_CLK].cb =3D + ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT); + clk_setup[PPC405EP_CPU_CLK].opaque =3D env; + + ppc_dcr_init(env, NULL, NULL); =20 /* CPU control */ ppc405ep_cpc_init(env, clk_setup, s->sysclk); @@ -1464,16 +1478,16 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) /* Universal interrupt controller */ s->uic =3D qdev_new(TYPE_PPC_UIC); =20 - object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(s->cpu), + object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu), &error_fatal); if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) { return; } =20 sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT, - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_INT)); + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT)= ); sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT, - qdev_get_gpio_in(DEVICE(s->cpu), PPC40x_INPUT_CINT)= ); + qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT= )); =20 /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ @@ -1562,6 +1576,7 @@ static const TypeInfo ppc405_types[] =3D { .name =3D TYPE_PPC405_SOC, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(Ppc405SoCState), + .instance_init =3D ppc405_soc_instance_init, .class_init =3D ppc405_soc_class_init, } }; diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 737c0896b4f8..f20098cf417c 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -37,7 +37,7 @@ #include "qapi/error.h" #include "trace.h" =20 -static void ppc4xx_reset(void *opaque) +void ppc4xx_reset(void *opaque) { PowerPCCPU *cpu =3D opaque; =20 --=20 2.37.1