From nobody Mon Feb 9 22:38:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659956345353682.4546065311096; Mon, 8 Aug 2022 03:59:05 -0700 (PDT) Received: from localhost ([::1]:49260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oL0TP-0002ri-AZ for importer@patchew.org; Mon, 08 Aug 2022 06:59:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oL00E-0006cC-MQ; Mon, 08 Aug 2022 06:28:55 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:46857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oL00C-0001Uj-M2; Mon, 08 Aug 2022 06:28:54 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4M1XV7545gz4xXh; Mon, 8 Aug 2022 20:28:31 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4M1XV54njCz4xVB; Mon, 8 Aug 2022 20:28:29 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v3 19/22] ppc/ppc405: QOM'ify FPGA Date: Mon, 8 Aug 2022 12:27:31 +0200 Message-Id: <20220808102734.133084-20-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220808102734.133084-1-clg@kaod.org> References: <20220808102734.133084-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=c6th=YM=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1659956346390100003 Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 5ba12d60bc00..195aa58c35ad 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -71,18 +71,23 @@ struct Ppc405MachineState { * - NVRAM (0xF0000000) * - FPGA (0xF0300000) */ -typedef struct ref405ep_fpga_t ref405ep_fpga_t; -struct ref405ep_fpga_t { + +#define TYPE_PPC405_FPGA "ppc405-fpga" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA); +struct Ppc405FpgaState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint8_t reg0; uint8_t reg1; }; =20 static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned si= ze) { - ref405ep_fpga_t *fpga; + Ppc405FpgaState *fpga =3D PPC405_FPGA(opaque); uint32_t ret; =20 - fpga =3D opaque; switch (addr) { case 0x0: ret =3D fpga->reg0; @@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwadd= r addr, unsigned size) static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ref405ep_fpga_t *fpga; + Ppc405FpgaState *fpga =3D PPC405_FPGA(opaque); =20 - fpga =3D opaque; switch (addr) { case 0x0: /* Read only */ @@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void ref405ep_fpga_reset (void *opaque) +static void ref405ep_fpga_reset(DeviceState *dev) { - ref405ep_fpga_t *fpga; + Ppc405FpgaState *fpga =3D PPC405_FPGA(dev); =20 - fpga =3D opaque; fpga->reg0 =3D 0x00; fpga->reg1 =3D 0x0F; } =20 -static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp) { - ref405ep_fpga_t *fpga; - MemoryRegion *fpga_memory =3D g_new(MemoryRegion, 1); + Ppc405FpgaState *s =3D PPC405_FPGA(dev); =20 - fpga =3D g_new0(ref405ep_fpga_t, 1); - memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s, "fpga", 0x00000100); - memory_region_add_subregion(sysmem, base, fpga_memory); - qemu_register_reset(&ref405ep_fpga_reset, fpga); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ref405ep_fpga_realize; + dc->user_creatable =3D false; + dc->reset =3D ref405ep_fpga_reset; } =20 +static const TypeInfo ref405ep_fpga_type =3D { + .name =3D TYPE_PPC405_FPGA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405FpgaState), + .class_init =3D ref405ep_fpga_class_init, +}; + /* * CPU reset handler when booting directly from a loaded kernel */ @@ -332,7 +348,11 @@ static void ref405ep_init(MachineState *machine) memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); =20 /* Register FPGA */ - ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE); + dev =3D qdev_new(TYPE_PPC405_FPGA); + object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE); + /* Register NVRAM */ dev =3D qdev_new("sysbus-m48t08"); qdev_prop_set_int32(dev, "base-year", 1968); @@ -377,6 +397,7 @@ static void ppc405_machine_init(void) { type_register_static(&ppc405_machine_type); type_register_static(&ref405ep_type); + type_register_static(&ref405ep_fpga_type); } =20 type_init(ppc405_machine_init) --=20 2.37.1