From nobody Mon Feb 9 23:04:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165995541457861.0373368269411; Mon, 8 Aug 2022 03:43:34 -0700 (PDT) Received: from localhost ([::1]:56828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oL0EN-0005Cd-Je for importer@patchew.org; Mon, 08 Aug 2022 06:43:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKzzi-0005cl-Dm; Mon, 08 Aug 2022 06:28:28 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:39621) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKzzg-0001TT-4K; Mon, 08 Aug 2022 06:28:22 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4M1XTt6rYrz4xV5; Mon, 8 Aug 2022 20:28:18 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4M1XTr6bQbz4xVB; Mon, 8 Aug 2022 20:28:16 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v3 14/22] ppc/ppc405: QOM'ify EBC Date: Mon, 8 Aug 2022 12:27:26 +0200 Message-Id: <20220808102734.133084-15-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220808102734.133084-1-clg@kaod.org> References: <20220808102734.133084-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=c6th=YM=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1659955415701100001 EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405.h | 17 +++++++++++++- hw/ppc/ppc405_uc.c | 56 +++++++++++++++++++++++----------------------- hw/ppc/sam460ex.c | 4 +++- 3 files changed, 47 insertions(+), 30 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c75e4c7cb50a..82bf8dae931f 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* Peripheral controller */ +#define TYPE_PPC405_EBC "ppc405-ebc" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC); +struct Ppc405EbcState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t addr; + uint32_t bcr[8]; + uint32_t bap[8]; + uint32_t bear; + uint32_t besr0; + uint32_t besr1; + uint32_t cfg; +}; + /* DMA controller */ #define TYPE_PPC405_DMA "ppc405-dma" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); @@ -192,12 +207,12 @@ struct Ppc405SoCState { Ppc405OcmState ocm; Ppc405GpioState gpio; Ppc405DmaState dma; + Ppc405EbcState ebc; }; =20 /* PowerPC 405 core */ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); =20 void ppc4xx_plb_init(CPUPPCState *env); -void ppc405_ebc_init(CPUPPCState *env); =20 #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 49405e610dc1..732b05156715 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -393,17 +393,6 @@ static void ppc4xx_opba_init(hwaddr base) =20 /*************************************************************************= ****/ /* Peripheral controller */ -typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; -struct ppc4xx_ebc_t { - uint32_t addr; - uint32_t bcr[8]; - uint32_t bap[8]; - uint32_t bear; - uint32_t besr0; - uint32_t besr1; - uint32_t cfg; -}; - enum { EBC0_CFGADDR =3D 0x012, EBC0_CFGDATA =3D 0x013, @@ -411,10 +400,9 @@ enum { =20 static uint32_t dcr_read_ebc (void *opaque, int dcrn) { - ppc4xx_ebc_t *ebc; + Ppc405EbcState *ebc =3D PPC405_EBC(opaque); uint32_t ret; =20 - ebc =3D opaque; switch (dcrn) { case EBC0_CFGADDR: ret =3D ebc->addr; @@ -496,9 +484,8 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn) =20 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) { - ppc4xx_ebc_t *ebc; + Ppc405EbcState *ebc =3D PPC405_EBC(opaque); =20 - ebc =3D opaque; switch (dcrn) { case EBC0_CFGADDR: ebc->addr =3D val; @@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, ui= nt32_t val) } } =20 -static void ebc_reset (void *opaque) +static void ppc405_ebc_reset(DeviceState *opaque) { - ppc4xx_ebc_t *ebc; + Ppc405EbcState *ebc =3D PPC405_EBC(opaque); int i; =20 - ebc =3D opaque; ebc->addr =3D 0x00000000; ebc->bap[0] =3D 0x7F8FFE80; ebc->bcr[0] =3D 0xFFE28000; @@ -572,16 +558,21 @@ static void ebc_reset (void *opaque) ebc->cfg =3D 0x80400000; } =20 -void ppc405_ebc_init(CPUPPCState *env) +static void ppc405_ebc_realize(DeviceState *dev, Error **errp) +{ + Ppc4xxDcrDeviceState *dcr =3D PPC4xx_DCR_DEVICE(dev); + + ppc4xx_dcr_register(dcr, EBC0_CFGADDR, &dcr_read_ebc, &dcr_write_ebc); + ppc4xx_dcr_register(dcr, EBC0_CFGDATA, &dcr_read_ebc, &dcr_write_ebc); +} + +static void ppc405_ebc_class_init(ObjectClass *oc, void *data) { - ppc4xx_ebc_t *ebc; - - ebc =3D g_new0(ppc4xx_ebc_t, 1); - qemu_register_reset(&ebc_reset, ebc); - ppc_dcr_register(env, EBC0_CFGADDR, - ebc, &dcr_read_ebc, &dcr_write_ebc); - ppc_dcr_register(env, EBC0_CFGDATA, - ebc, &dcr_read_ebc, &dcr_write_ebc); + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_ebc_realize; + dc->user_creatable =3D false; + dc->reset =3D ppc405_ebc_reset; } =20 /*************************************************************************= ****/ @@ -1367,6 +1358,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); =20 object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); + + object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); } =20 static void ppc405_soc_realize(DeviceState *dev, Error **errp) @@ -1427,7 +1420,9 @@ static void ppc405_soc_realize(DeviceState *dev, Erro= r **errp) s->do_dram_init); =20 /* External bus controller */ - ppc405_ebc_init(env); + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) { + return; + } =20 /* DMA controller */ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) { @@ -1509,6 +1504,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_EBC, + .parent =3D TYPE_PPC4xx_DCR_DEVICE, + .instance_size =3D sizeof(Ppc405EbcState), + .class_init =3D ppc405_ebc_class_init, + }, { .name =3D TYPE_PPC405_DMA, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405DmaState), diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 0357ee077f0c..320c61a7f36c 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -371,7 +371,9 @@ static void sam460ex_init(MachineState *machine) qdev_get_gpio_in(uic[0], 3)); =20 /* External bus controller */ - ppc405_ebc_init(env); + dev =3D qdev_new(TYPE_PPC405_EBC); + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal); + object_unref(OBJECT(dev)); =20 /* CPR */ ppc4xx_cpr_init(env); --=20 2.37.1