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([2602:ae:154e:e201:e1d0:6bbf:50d3:62d0]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c20d00b0016e808dbe55sm5222766pll.96.2022.08.06.10.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Aug 2022 10:08:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GNCb7Nz2ROh9PYMnAnCH9XpQC6SfEV8gH3g11a7bINA=; b=loGuB94lNIr5/O+i/kNZHiVxSG1ITqiFgCpRYamEUK7bwNpQb0N1PvJfkYYwQ+iud3 YAGmB6XHceRwGdfh2FD6DtqXVATztlU0+YjbrWRMfGAmLhIYW/BPbVTuYJkzSgWWo1pv /NrrtlvdrD9Gqgc25sYSwntQCFG02wJ7UcW9SMaknaSevhCXCsBFcWZEW4yzI7Q9AWwJ 1xYiqzRHcLldU2QboDCNV4LFHz40Xc3be4D05/KZOGb2PBtT3W/2duW3DdoyuYCKHc/G qGuf3ZDCaUR4FPXNXa/L8Y56sYtkrN37YkMfr6Dlm8xlrXPQvJpDyuqrNXCtFIeWd/Mx B5hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GNCb7Nz2ROh9PYMnAnCH9XpQC6SfEV8gH3g11a7bINA=; b=Q3XO3wcfry+7HimCeMYFGXJg9q73CCLa/X8gU2EZWmhqOYFMZ+WqgPmio3gXWQ3zjD QlO5r+5Sb7yK0FuYBOEGdu9MR6g8953ACaB+Vk5kS5yzUUL7LSWq/QKyHFkOuk6TltOu ZWVv96N5gWaP+PTjRuhOz+USSUcgiBL2cOeFIeKXs0dIBv8bxlOp9Eawx2VpbznQ+2NY /WxdDfNNrcQUkHPVJ/CDY5O6SUdAWk8P/0JteL+Y6ignheFZgqT48EIs9zpfc4nVrMkH +vJY7azxoWwLgr8VRgINs5bW0Qwh/1YglH8w/jti0/NLA62Ucx3dZV4thUIr085Oy+Nu BqZA== X-Gm-Message-State: ACgBeo2YVqgrXQChuhZDd/oQeySqOiJAyw6bfLHlTyuEU1CWywLKICCx e0e/UsEnZo8K4AFey5sqZ8PC14qffysOLg== X-Google-Smtp-Source: AA6agR5N8G/2cf6ZD78B2RipSLy7Ul91OWNFc23032WuAA9roak7/IHsQKHbopJWBgp2KMr8sajUpA== X-Received: by 2002:a05:6a02:183:b0:41a:8177:9c3 with SMTP id bj3-20020a056a02018300b0041a817709c3mr10089659pgb.157.1659805682224; Sat, 06 Aug 2022 10:08:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Qi Hu , Song Gao , Feiyang Chen Subject: [PATCH] target/loongarch: Remove cpu_fcsr0 Date: Sat, 6 Aug 2022 10:08:00 -0700 Message-Id: <20220806170800.373219-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1659805758387100001 Content-Type: text/plain; charset="utf-8" All of the fpu operations are defined with TCG_CALL_NO_WG, but they all modify FCSR0. The most efficient way to fix this is to remove cpu_fcsr0, and instead use explicit load and store operations for the two instructions that manipulate that value. Cc: Qi Hu Cc: Song Gao Reported-by: Feiyang Chen Signed-off-by: Richard Henderson Acked-by: Qi Hu Reviewed-by: Song Gao --- target/loongarch/helper.h | 2 +- target/loongarch/fpu_helper.c | 4 +-- target/loongarch/translate.c | 3 -- tests/tcg/loongarch64/test_fcsr.c | 15 +++++++++ target/loongarch/insn_trans/trans_fmov.c.inc | 33 ++++++++++---------- tests/tcg/loongarch64/Makefile.target | 1 + 6 files changed, 36 insertions(+), 22 deletions(-) create mode 100644 tests/tcg/loongarch64/test_fcsr.c diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index cbbe008f32..9c01823a26 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -91,7 +91,7 @@ DEF_HELPER_2(ftint_w_d, i64, env, i64) DEF_HELPER_2(frint_s, i64, env, i64) DEF_HELPER_2(frint_d, i64, env, i64) =20 -DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_1(set_rounding_mode, TCG_CALL_NO_RWG, void, env) =20 DEF_HELPER_1(rdtime_d, i64, env) =20 diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c index bd76529219..4b9637210a 100644 --- a/target/loongarch/fpu_helper.c +++ b/target/loongarch/fpu_helper.c @@ -872,8 +872,8 @@ uint64_t helper_ftint_w_d(CPULoongArchState *env, uint6= 4_t fj) return fd; } =20 -void helper_set_rounding_mode(CPULoongArchState *env, uint32_t fcsr0) +void helper_set_rounding_mode(CPULoongArchState *env) { - set_float_rounding_mode(ieee_rm[(fcsr0 >> FCSR0_RM) & 0x3], + set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], &env->fp_status); } diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index c9afd11420..51ba291430 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -22,7 +22,6 @@ /* Global register indices */ TCGv cpu_gpr[32], cpu_pc; static TCGv cpu_lladdr, cpu_llval; -TCGv_i32 cpu_fcsr0; TCGv_i64 cpu_fpr[32]; =20 #include "exec/gen-icount.h" @@ -266,8 +265,6 @@ void loongarch_translate_init(void) } =20 cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc)= , "pc"); - cpu_fcsr0 =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPULoongArchState, fcsr0), "fcsr0"); cpu_lladdr =3D tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, lladdr), "lladdr"); cpu_llval =3D tcg_global_mem_new(cpu_env, diff --git a/tests/tcg/loongarch64/test_fcsr.c b/tests/tcg/loongarch64/test= _fcsr.c new file mode 100644 index 0000000000..ad3609eb99 --- /dev/null +++ b/tests/tcg/loongarch64/test_fcsr.c @@ -0,0 +1,15 @@ +#include + +int main() +{ + unsigned fcsr; + + asm("movgr2fcsr $r0,$r0\n\t" + "movgr2fr.d $f0,$r0\n\t" + "fdiv.d $f0,$f0,$f0\n\t" + "movfcsr2gr %0,$r0" + : "=3Dr"(fcsr) : : "f0"); + + assert(fcsr & (16 << 16)); /* Invalid */ + return 0; +} diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarc= h/insn_trans/trans_fmov.c.inc index 24753d4568..5537e3dd35 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -60,38 +60,39 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_mov= gr2fcsr *a) TCGv Rj =3D gpr_src(ctx, a->rj, EXT_NONE); =20 if (mask =3D=3D UINT32_MAX) { - tcg_gen_extrl_i64_i32(cpu_fcsr0, Rj); + tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0)); } else { + TCGv_i32 fcsr0 =3D tcg_temp_new_i32(); TCGv_i32 temp =3D tcg_temp_new_i32(); =20 + tcg_gen_ld_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_extrl_i64_i32(temp, Rj); tcg_gen_andi_i32(temp, temp, mask); - tcg_gen_andi_i32(cpu_fcsr0, cpu_fcsr0, ~mask); - tcg_gen_or_i32(cpu_fcsr0, cpu_fcsr0, temp); + tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); + tcg_gen_or_i32(fcsr0, fcsr0, temp); + tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); + tcg_temp_free_i32(temp); - - /* - * Install the new rounding mode to fpu_status, if changed. - * Note that FCSR3 is exactly the rounding mode field. - */ - if (mask !=3D FCSR0_M3) { - return true; - } + tcg_temp_free_i32(fcsr0); } - gen_helper_set_rounding_mode(cpu_env, cpu_fcsr0); =20 + /* + * Install the new rounding mode to fpu_status, if changed. + * Note that FCSR3 is exactly the rounding mode field. + */ + if (mask & FCSR0_M3) { + gen_helper_set_rounding_mode(cpu_env); + } return true; } =20 static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a) { - TCGv_i32 temp =3D tcg_temp_new_i32(); TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); =20 - tcg_gen_andi_i32(temp, cpu_fcsr0, fcsr_mask[a->fcsrs]); - tcg_gen_ext_i32_i64(dest, temp); + tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); + tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free_i32(temp); =20 return true; } diff --git a/tests/tcg/loongarch64/Makefile.target b/tests/tcg/loongarch64/= Makefile.target index 0115de78ef..00030a1026 100644 --- a/tests/tcg/loongarch64/Makefile.target +++ b/tests/tcg/loongarch64/Makefile.target @@ -15,5 +15,6 @@ LOONGARCH64_TESTS +=3D test_div LOONGARCH64_TESTS +=3D test_fclass LOONGARCH64_TESTS +=3D test_fpcom LOONGARCH64_TESTS +=3D test_pcadd +LOONGARCH64_TESTS +=3D test_fcsr =20 TESTS +=3D $(LOONGARCH64_TESTS) --=20 2.34.1