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([2602:ae:154e:e201:abf8:e436:f4c:9089]) by smtp.gmail.com with ESMTPSA id h13-20020a170902f70d00b0016f0c2ea158sm3393048plo.157.2022.08.05.12.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 12:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XoU1ivq664BvtVyoqP3w9U5Cy8Z2Wrd2UTjf3IBy+og=; b=FkgaMo+C+6HJ7MZqb7CEjwD5SBayfdFuUK2Scu2quYO3o4FKx3jXcYa9ud0WAgCSin ySmjj6lMnALnumdmlEALj2IwyIZajl53PSrIqnlV0Wyy1BQpWvdjLVRGMipxLOQwH92q KzKtJMluVe3x/4NwQKX/9jpeMlI7kU2p2NbX6oZqFqR4J6n8X97gZbMH0gZddhUAXZKy HYkyIzgUH0Qj9+1BucFb7pj3dFHvoUOPDsO4CXNHAYi5bO26z1Dfze2A+MlsAlVgtuhg Y1PDhYCCH5wbuteTn4xLZGeCUsweXExqwMYPxaQsUv+FD8K7gDR8OjD0XDJurCAEJJ7U C8BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XoU1ivq664BvtVyoqP3w9U5Cy8Z2Wrd2UTjf3IBy+og=; b=pT8JXNMTs/AoAhltQhS6covNN8lE5fSPjYX8RICcisNSmjEBP0iXb7VMM75+o8adNb MaEVJjO0cg3KNDSEvxodieCnXKV/kKbod4iRs4Bb/dkxeq50aEFXh7Ur7ZjxFLcGoSX0 yZIllzExIV46WpC27QWOrDotMNmp8y7AaX+SwVtgEcLNqyS8YFub9Wst1dK8v5URHXbT QOz2bhPQv6RGdfnKh5cZyI0M73TFUthSi6uMMgiXu/y8Dz/FccVCnsgFpTzLKUZegrYg dnBtanCgMKSMvNT2zN4p46av4y1D0kQQEw32qtPd8hEHfaR9/4lG9WuHtaqe6OusMqOw pVbg== X-Gm-Message-State: ACgBeo1Ts/sf1/bp5McZ6hc7KSeoPMjhnjJm7PuSSbqfDSseaiUkUG6I CcxXlT6otC+IfBs0AVrK7TNX3pC4C0hTHA== X-Google-Smtp-Source: AA6agR6HGWlkXQjYCp4wVYVTWW8rzrS9pS9gmbzfqZevMwJp6SIOtHv6Q5s8w1PuGbx2CGIGLCII2w== X-Received: by 2002:a17:90b:4f42:b0:1f5:6976:7021 with SMTP id pj2-20020a17090b4f4200b001f569767021mr9472482pjb.30.1659729318421; Fri, 05 Aug 2022 12:55:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Qi Hu , Song Gao Subject: [PULL 1/7] target/loongarch: Fix macros SET_FPU_* in cpu.h Date: Fri, 5 Aug 2022 12:55:09 -0700 Message-Id: <20220805195515.349768-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220805195515.349768-1-richard.henderson@linaro.org> References: <20220805195515.349768-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1659729492079100001 Content-Type: text/plain; charset="utf-8" From: Qi Hu The macros SET_FPU_* are used to set corresponding bits of fcsr. Unfortunately it forgets to set the result and it causes fcsr's "CAUSE" never being updated. This patch is to fix this bug. Signed-off-by: Qi Hu Reviewed-by: Song Gao Message-Id: <20220804132450.314329-1-huqi@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index a36349df83..dce999aaac 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5) FIELD(FCSR0, CAUSE, 24, 5) =20 #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) -#define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR0, CAUSE, V) +#define SET_FP_CAUSE(REG, V) \ + do { \ + (REG) =3D FIELD_DP32(REG, FCSR0, CAUSE, V); \ + } while (0) + #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) -#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V) +#define SET_FP_ENABLES(REG, V) \ + do { \ + (REG) =3D FIELD_DP32(REG, FCSR0, ENABLES, V); \ + } while (0) + #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) -#define SET_FP_FLAGS(REG, V) FIELD_DP32(REG, FCSR0, FLAGS, V) +#define SET_FP_FLAGS(REG, V) \ + do { \ + (REG) =3D FIELD_DP32(REG, FCSR0, FLAGS, V); \ + } while (0) + #define UPDATE_FP_FLAGS(REG, V) \ do { \ (REG) |=3D FIELD_DP32(0, FCSR0, FLAGS, V); \ --=20 2.34.1