From nobody Fri Apr 19 16:44:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1659638950; cv=none; d=zohomail.com; s=zohoarc; b=T9kB/F39/GAOOZzEKIMhHoLF9YqJdAAsfEfxAWA0oUb8qRyU6CARl/dDDIk7iIsmVK4zoKTUASLEwNnL5hj45u+uHiZdPaiNEgE8tK3wznip1z/3NgcLj9tEkkdQ9YpA+nI8WZveIviHf3jixJvA+1rdDfkOuEQQD6pJqiFIIXk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659638950; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KxfbJ3EzVkwLUvNVsw3iZ9/Tak/DHkZlr/bFzpTRW/4=; b=TTkUg85jqKGliWPinbxavL9qJeTdKi5aDqU+7o9j1XglE0kXrrhkMZZgxMV97s0RVCquE5UL7rLSIGOaNCaOyMEC/zQgEd4UA9OnwCHoynXZGcU1qeHI3lHvQcChbus4tfm/benGUCzb8ds0MttwtM4RKekq+/K+UbQ2cL6wASw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659638950182138.084249910866; Thu, 4 Aug 2022 11:49:10 -0700 (PDT) Received: from localhost ([::1]:50938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oJfu9-000617-2I for importer@patchew.org; Thu, 04 Aug 2022 14:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJfWE-0007rL-PY; Thu, 04 Aug 2022 14:24:30 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:47166) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJfWB-0002NP-M3; Thu, 04 Aug 2022 14:24:26 -0400 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 274ICDVV014436; Thu, 4 Aug 2022 18:24:09 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hrk658avj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 18:24:09 +0000 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 274IED7w031486; Thu, 4 Aug 2022 18:24:08 GMT Received: from ppma01fra.de.ibm.com (46.49.7a9f.ip4.static.sl-reverse.com [159.122.73.70]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hrk658auf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 18:24:08 +0000 Received: from pps.filterd (ppma01fra.de.ibm.com [127.0.0.1]) by ppma01fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 274IMKxR009166; Thu, 4 Aug 2022 18:24:05 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma01fra.de.ibm.com with ESMTP id 3hrf2188dr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 18:24:05 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 274IO2pP22544732 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 4 Aug 2022 18:24:02 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2203B5204E; Thu, 4 Aug 2022 18:24:02 +0000 (GMT) Received: from heavy.lan (unknown [9.171.2.232]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 8FDBD52050; Thu, 4 Aug 2022 18:24:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=KxfbJ3EzVkwLUvNVsw3iZ9/Tak/DHkZlr/bFzpTRW/4=; b=PHkdJ2bxeiySzbfLxJcKHOkg5yv4FEJpV8is3xb/PR/qZg79nGi8bQLH0YnZ4aU2OAOt +Kc+PzFV2cWfT0yew0qW7O/Mu/Xek0ggpl+soC2f6aIuOhtvsf9WS9wXJwbdLCKPSPde cS3PLiOeyrkvI4bTVOroPyrMThrHdgk5I44aM4guV5AJjY0IawV1NuxojfGiHSJCcl8n M2nfRFkDvaEUSQr0L6P/ntQFYdhz1kmn+1/GgE/yGLIRQTyG5VoaGDVfmF6EtdzDK6H9 Y417/DGv7Xg6BR7lYT45GK822mITMcBpgbiREbhs8JcHdQVp4mIziDoC86pICYGD2r9d ew== From: Ilya Leoshkevich To: Laurent Vivier , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Richard Henderson , Paolo Bonzini , David Hildenbrand Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, Christian Borntraeger , Ilya Leoshkevich Subject: [PATCH 1/2] linux-user: Fix siginfo_t contents when jumping to non-readable pages Date: Thu, 4 Aug 2022 20:23:58 +0200 Message-Id: <20220804182359.830058-2-iii@linux.ibm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220804182359.830058-1-iii@linux.ibm.com> References: <20220804182359.830058-1-iii@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tIGd8rS9RfGSK-sf5ZnTaTPpy19kzEAl X-Proofpoint-GUID: M4047UbIBCsYmNdqKwYu3PWPonqDN1ym X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-04_03,2022-08-04_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2208040077 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1659638950748100001 Content-Type: text/plain; charset="utf-8" When the first instruction of a translation block is located in a non-readable page, qemu-user fills siginfo_t correctly. For the other instructions the result is as if it were the first instruction, which is not correct. The reason is that the current logic expects translate_insn() hook to stop at the page boundary. This way only the first instruction can cause a SEGV. However, this is quite difficult to properly implement when the problematic instruction crosses a page boundary, and indeed the actual implementations do not do this. Note that this can also break self-modifying code detection when only bytes on the second page are modified, but this is outside of the scope of this patch. Instead of chaning all the translators, do a much simpler thing: when such a situation is detected, start from scratch and stop right before the problematic instruction. Signed-off-by: Ilya Leoshkevich --- accel/tcg/translate-all.c | 16 +++++++++++----- accel/tcg/translator.c | 25 +++++++++++++++++++++++++ include/hw/core/cpu.h | 2 ++ linux-user/signal.c | 5 +++++ 4 files changed, 43 insertions(+), 5 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ef62a199c7..b4766f4661 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2295,12 +2295,18 @@ void page_set_flags(target_ulong start, target_ulon= g end, int flags) len !=3D 0; len -=3D TARGET_PAGE_SIZE, addr +=3D TARGET_PAGE_SIZE) { PageDesc *p =3D page_find_alloc(addr >> TARGET_PAGE_BITS, 1); + bool invalidate; =20 - /* If the write protection bit is set, then we invalidate - the code inside. */ - if (!(p->flags & PAGE_WRITE) && - (flags & PAGE_WRITE) && - p->first_tb) { + /* + * If the write protection bit is set, then we invalidate the code + * inside. For qemu-user, we need to do this when PAGE_READ is cl= eared + * as well, in order to force a SEGV when trying to run this code. + */ + invalidate =3D !(p->flags & PAGE_WRITE) && (flags & PAGE_WRITE); +#ifdef CONFIG_USER_ONLY + invalidate |=3D (p->flags & PAGE_READ) && !(flags & PAGE_READ); +#endif + if (invalidate && p->first_tb) { tb_invalidate_phys_page(addr, 0); } if (reset_target_data) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index fe7af9b943..e444c17515 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -57,6 +57,18 @@ void translator_loop(const TranslatorOps *ops, DisasCont= extBase *db, uint32_t cflags =3D tb_cflags(tb); bool plugin_enabled; =20 + /* + * In case translate_insn hook touched an unreadable page, redo the + * translation until the problematic instruction. We cannot just throw + * away the trailing ops, because the hook could have changed DisasCon= text. + */ + tcg_debug_assert(!cpu->translator_jmp); + if (sigsetjmp(cpu->translator_jmp_env, 1) !=3D 0) { + cpu->translator_jmp =3D false; + tcg_remove_ops_after(NULL); + max_insns =3D db->num_insns - 1; + } + /* Initialize DisasContext */ db->tb =3D tb; db->pc_first =3D tb->pc; @@ -122,8 +134,21 @@ void translator_loop(const TranslatorOps *ops, DisasCo= ntextBase *db, db->is_jmp =3D DISAS_TOO_MANY; break; } + + /* + * Propagate SEGVs from the first instruction to the guest and han= dle + * the rest. This way guest's siginfo_t gets accurate pc and si_ad= dr. + */ + cpu->translator_jmp =3D true; } =20 + /* + * Clear translator_jmp on all ways out of this function, otherwise + * instructions that fetch code as part of their operation will be + * confused. + */ + cpu->translator_jmp =3D false; + /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); gen_tb_end(db->tb, db->num_insns); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 500503da13..6c1829b7f5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -349,6 +349,8 @@ struct CPUState { int64_t icount_extra; uint64_t random_seed; sigjmp_buf jmp_env; + bool translator_jmp; + sigjmp_buf translator_jmp_env; =20 QemuMutex work_mutex; QSIMPLEQ_HEAD(, qemu_work_item) work_list; diff --git a/linux-user/signal.c b/linux-user/signal.c index 8d29bfaa6b..f7e77c8d2e 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -833,6 +833,11 @@ static void host_signal_handler(int host_sig, siginfo_= t *info, void *puc) abi_ptr guest_addr; bool is_write; =20 + /* Translator wants to handle this. */ + if (helper_retaddr =3D=3D 1 && cpu->translator_jmp) { + siglongjmp(cpu->translator_jmp_env, 1); + } + host_addr =3D (uintptr_t)info->si_addr; =20 /* --=20 2.35.3 From nobody Fri Apr 19 16:44:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1659637725; cv=none; d=zohomail.com; s=zohoarc; b=FJ1NawgjGnjfWWW9lwDQLjKK36Xy1UvNaRRe2Z52NohxHkpGb73f1Fn5ODd7PPHLwbu0jbsOm0FCWBGSyG3vhAm4j+rSljCu7/BcK8ncOVI4kekM1nIRtLwPW1hI8BCVERcGBJlxo6rNnxrNvGUNlATseJEY6Hj1he/tQGYOaBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1659637725; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mx7WE3EFJlt9psuq5N3BY5Dfy8FVWWpe1R1MZOF6Jm8=; b=ChKMqYpn6i1A3sJ7ICgGbTBedQe/DfCCd4qK47kphFAX1CXdnR/JXpobRMt/KzOdhS7SOj+hZ1aIdJf8saLMa9PRQcYTaqdzVCgsmSYzethhJ7VSqzNWTZ2q+4Qz4OlLjxgYGvQAnlxAl38HwscAVCHwMvkeg2ENqHnWLXVPV0s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659637725085451.81291932959107; Thu, 4 Aug 2022 11:28:45 -0700 (PDT) Received: from localhost ([::1]:46976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oJfaO-00068u-0w for importer@patchew.org; Thu, 04 Aug 2022 14:28:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34018) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJfWE-0007q7-3M; Thu, 04 Aug 2022 14:24:26 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:44826) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJfWB-0002NW-Qn; Thu, 04 Aug 2022 14:24:25 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 274IAIir028509; Thu, 4 Aug 2022 18:24:08 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hrjx9rjth-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 18:24:08 +0000 Received: from m0098421.ppops.net (m0098421.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 274IGXeX022012; Thu, 4 Aug 2022 18:24:08 GMT Received: from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com [149.81.74.108]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hrjx9rjsm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 18:24:07 +0000 Received: from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1]) by ppma05fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 274ILKNf002017; Thu, 4 Aug 2022 18:24:06 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma05fra.de.ibm.com with ESMTP id 3hmv994u7r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 18:24:06 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 274IO26W20316564 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 4 Aug 2022 18:24:02 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B30AC5204F; Thu, 4 Aug 2022 18:24:02 +0000 (GMT) Received: from heavy.lan (unknown [9.171.2.232]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 2D19F52052; Thu, 4 Aug 2022 18:24:02 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=mx7WE3EFJlt9psuq5N3BY5Dfy8FVWWpe1R1MZOF6Jm8=; b=slNkp+XNO7rd6BFpJHOhyH8HtjjPw9YGcEXId4m/HoijR/FeZ8tPGwJkhuQIhkdJ1o4L uV0ePD12eOaTxZQxWqsVrMVk2GbJIl8TwxFU+ckMz9CUWtWOs3wjIBIYxuL8yAw1kzMB vvwyh5xJG6mMIpEhXPYE2jOZO4BagoEG84Qcwmxf8nluKqlBCihlNwOlWB8s0qu625yD SuUTDv4lOspc0mQFlUDoDcWylx20IjLMbFF0furLcA6qtP/bw41HUOrKlQhB4yqBAWZT mnfrvhi/1wkOrkEJo4T0qQ/Lm4DZo0JtLEOI85rxLSw+ggIGNtD0Efm3o+76AJ6u1tNt Mg== From: Ilya Leoshkevich To: Laurent Vivier , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Richard Henderson , Paolo Bonzini , David Hildenbrand Cc: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, Christian Borntraeger , Ilya Leoshkevich Subject: [PATCH 2/2] tests/tcg: Test siginfo_t contents when jumping to non-readable pages Date: Thu, 4 Aug 2022 20:23:59 +0200 Message-Id: <20220804182359.830058-3-iii@linux.ibm.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220804182359.830058-1-iii@linux.ibm.com> References: <20220804182359.830058-1-iii@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: g6u86Yf-aQ0FV3NlveMvEASpH3auaj4H X-Proofpoint-GUID: y2GAHl6vs4NpXacMzwiRbAxoAL4DWlb1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-04_03,2022-08-04_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2208040077 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1659637725813100001 Content-Type: text/plain; charset="utf-8" Add x86_64 and s390x tests to prevent regressions. Signed-off-by: Ilya Leoshkevich --- tests/tcg/multiarch/noexec.h | 114 ++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + tests/tcg/s390x/noexec.c | 145 +++++++++++++++++++++++++++++++ tests/tcg/x86_64/Makefile.target | 3 +- tests/tcg/x86_64/noexec.c | 116 +++++++++++++++++++++++++ 5 files changed, 378 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/multiarch/noexec.h create mode 100644 tests/tcg/s390x/noexec.c create mode 100644 tests/tcg/x86_64/noexec.c diff --git a/tests/tcg/multiarch/noexec.h b/tests/tcg/multiarch/noexec.h new file mode 100644 index 0000000000..a76e0aa9ea --- /dev/null +++ b/tests/tcg/multiarch/noexec.h @@ -0,0 +1,114 @@ +/* + * Common code for arch-specific MMU_INST_FETCH fault testing. + * + * Declare struct arch_noexec_test before including this file and define + * arch_check_mcontext() after that. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Forward declarations. */ + +static void arch_check_mcontext(const struct arch_noexec_test *test, + const mcontext_t *ctx); + +/* Utility functions. */ + +static void safe_print(const char *s) +{ + write(0, s, strlen(s)); +} + +static void safe_puts(const char *s) +{ + safe_print(s); + safe_print("\n"); +} + +#define PAGE_ALIGN(p) (void *)((unsigned long)(p) & ~0xfffUL) + +/* Testing infrastructure. */ + +struct noexec_test { + const char *name; + void (*func)(int); + void *page; + void *expected_si_addr; + struct arch_noexec_test arch; +}; + +static const struct noexec_test *current_noexec_test; + +static void handle_segv(int sig, siginfo_t *info, void *ucontext) +{ + int err; + + if (current_noexec_test =3D=3D NULL) { + safe_puts("[ FAILED ] unexpected SEGV"); + _exit(1); + } + + if (info->si_addr !=3D current_noexec_test->expected_si_addr) { + safe_puts("[ FAILED ] wrong si_addr"); + _exit(1); + } + + arch_check_mcontext(¤t_noexec_test->arch, + &((ucontext_t *)ucontext)->uc_mcontext); + + err =3D mprotect(current_noexec_test->page, 0x1000, PROT_READ | PROT_E= XEC); + if (err !=3D 0) { + safe_puts("[ FAILED ] mprotect() failed"); + _exit(1); + } + + current_noexec_test =3D NULL; +} + +static void test_noexec_1(const struct noexec_test *test) +{ + int ret; + + /* Trigger TB creation in order to test invalidation. */ + test->func(0); + + ret =3D mprotect(test->page, 0x1000, PROT_NONE); + assert(ret =3D=3D 0); + + /* Trigger SEGV and check that handle_segv() ran. */ + current_noexec_test =3D test; + test->func(0); + assert(current_noexec_test =3D=3D NULL); +} + +static int test_noexec(struct noexec_test *tests, size_t n_tests) +{ + struct sigaction act; + size_t i; + int err; + + memset(&act, 0, sizeof(act)); + act.sa_sigaction =3D handle_segv; + act.sa_flags =3D SA_SIGINFO; + err =3D sigaction(SIGSEGV, &act, NULL); + assert(err =3D=3D 0); + + for (i =3D 0; i < n_tests; i++) { + struct noexec_test *test =3D &tests[i]; + + safe_print("[ RUN ] "); + safe_puts(test->name); + test_noexec_1(test); + safe_puts("[ OK ]"); + } + + safe_puts("[ PASSED ]"); + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 1a7a4a2f59..5e13a41c3f 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -16,6 +16,7 @@ TESTS+=3Dshift TESTS+=3Dtrap TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long +TESTS+=3Dnoexec =20 Z14_TESTS=3Dvfminmax vfminmax: LDFLAGS+=3D-lm diff --git a/tests/tcg/s390x/noexec.c b/tests/tcg/s390x/noexec.c new file mode 100644 index 0000000000..2dfc9ee817 --- /dev/null +++ b/tests/tcg/s390x/noexec.c @@ -0,0 +1,145 @@ +#define _GNU_SOURCE + +struct arch_noexec_test { + void *expected_pswa; + unsigned long expected_r2; +}; + +#include "../multiarch/noexec.h" + +static void arch_check_mcontext(const struct arch_noexec_test *test, + const mcontext_t *ctx) { + if (ctx->psw.addr !=3D (unsigned long)test->expected_pswa) { + safe_puts("[ FAILED ] wrong psw.addr"); + _exit(1); + } + + if (ctx->gregs[2] !=3D test->expected_r2) { + safe_puts("[ FAILED ] wrong r2"); + _exit(1); + } +} + +#define DEFINE_NX(name, offset) \ + void name ## _1(int); \ + void name ## _2(int); \ + void name ## _exrl(int); \ + extern const short name ## _end[]; \ + asm(/* Go to the specified page offset. */ \ + ".align 0x1000\n" \ + ".org .+" #offset "\n" \ + /* %r2 is 0 on entry, overwrite it with 1. */ \ + ".globl " #name "_1\n" \ + #name "_1:\n" \ + ".cfi_startproc\n" \ + "lgfi %r2,1\n" \ + /* Overwrite %2 with 2. */ \ + ".globl " #name "_2\n" \ + #name "_2:\n" \ + "lgfi %r2,2\n" \ + "br %r14\n" \ + /* End of code. */ \ + ".globl " #name "_end\n" \ + #name "_end:\n" \ + ".cfi_endproc\n" \ + /* Go to the next page. */ \ + ".align 0x1000\n" \ + /* Break alignment. */ \ + "nopr %r7\n" \ + ".globl " #name "_exrl\n" \ + #name "_exrl:\n" \ + ".cfi_startproc\n" \ + "exrl %r0," #name "_2\n" \ + "br %r14\n" \ + ".cfi_endproc"); + +/* noexec_1 is executable, noexec_2 is non-executable. */ +DEFINE_NX(noexec, 0xffa); + +/* + * noexec_cross_1 is executable, noexec_cross_2 crosses non-executable page + * boundary. + */ +DEFINE_NX(noexec_cross, 0xff8); + +/* noexec_full_1 and noexec_full_2 are non-executable. */ +DEFINE_NX(noexec_full, 0x322); + +int main(void) +{ + struct noexec_test noexec_tests[] =3D { + { + .name =3D "Fallthrough", + .func =3D noexec_1, + .page =3D noexec_2, + .expected_si_addr =3D noexec_2, + .arch =3D { + .expected_pswa =3D noexec_2, + .expected_r2 =3D 1, + }, + }, + { + .name =3D "Jump", + .func =3D noexec_2, + .page =3D noexec_2, + .expected_si_addr =3D noexec_2, + .arch =3D { + .expected_pswa =3D noexec_2, + .expected_r2 =3D 0, + }, + }, + { + .name =3D "EXRL", + .func =3D noexec_exrl, + .page =3D noexec_2, + .expected_si_addr =3D PAGE_ALIGN(noexec_end), + .arch =3D { + .expected_pswa =3D noexec_exrl, + .expected_r2 =3D 0, + }, + }, + { + .name =3D "Fallthrough [cross]", + .func =3D noexec_cross_1, + .page =3D PAGE_ALIGN(noexec_cross_end), + .expected_si_addr =3D PAGE_ALIGN(noexec_cross_end), + .arch =3D { + .expected_pswa =3D noexec_cross_2, + .expected_r2 =3D 1, + }, + }, + { + .name =3D "Jump [cross]", + .func =3D noexec_cross_2, + .page =3D PAGE_ALIGN(noexec_cross_end), + .expected_si_addr =3D PAGE_ALIGN(noexec_cross_end), + .arch =3D { + .expected_pswa =3D noexec_cross_2, + .expected_r2 =3D 0, + }, + }, + { + .name =3D "EXRL [cross]", + .func =3D noexec_cross_exrl, + .page =3D PAGE_ALIGN(noexec_cross_end), + .expected_si_addr =3D PAGE_ALIGN(noexec_cross_end), + .arch =3D { + .expected_pswa =3D noexec_cross_exrl, + .expected_r2 =3D 0, + }, + }, + { + .name =3D "Jump [full]", + .func =3D noexec_full_1, + .page =3D PAGE_ALIGN(noexec_full_1), + .expected_si_addr =3D PAGE_ALIGN(noexec_full_1), + .arch =3D { + .expected_pswa =3D noexec_full_1, + .expected_r2 =3D 0, + }, + }, + }; + + return test_noexec(noexec_tests, + sizeof(noexec_tests) / sizeof(noexec_tests[0])); +} diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.t= arget index b71a6bcd5e..c0e7e5b005 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -10,6 +10,7 @@ include $(SRC_PATH)/tests/tcg/i386/Makefile.target =20 ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET)) X86_64_TESTS +=3D vsyscall +X86_64_TESTS +=3D noexec TESTS=3D$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 else TESTS=3D$(MULTIARCH_TESTS) @@ -20,5 +21,5 @@ test-x86_64: LDFLAGS+=3D-lm -lc test-x86_64: test-i386.c test-i386.h test-i386-shift.h test-i386-muldiv.h $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) =20 -vsyscall: $(SRC_PATH)/tests/tcg/x86_64/vsyscall.c +%: $(SRC_PATH)/tests/tcg/x86_64/%.c $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) diff --git a/tests/tcg/x86_64/noexec.c b/tests/tcg/x86_64/noexec.c new file mode 100644 index 0000000000..ec07c9f0ba --- /dev/null +++ b/tests/tcg/x86_64/noexec.c @@ -0,0 +1,116 @@ +#define _GNU_SOURCE + +struct arch_noexec_test { + void *expected_rip; + unsigned long expected_rdi; +}; + +#include "../multiarch/noexec.h" + +static void arch_check_mcontext(const struct arch_noexec_test *test, + const mcontext_t *ctx) { + if (ctx->gregs[REG_RIP] !=3D (unsigned long)test->expected_rip) { + safe_puts("[ FAILED ] wrong rip"); + _exit(1); + } + + if (ctx->gregs[REG_RDI] !=3D test->expected_rdi) { + safe_puts("[ FAILED ] wrong rdi"); + _exit(1); + } +} + +#define DEFINE_NX(name, offset) \ + void name ## _1(int); \ + void name ## _2(int); \ + extern const short name ## _end[]; \ + asm(/* Go to the specified page offset. */ \ + ".align 0x1000\n" \ + ".org .+" #offset "\n" \ + /* %rdi is 0 on entry, overwrite it with 1. */ \ + ".globl " #name "_1\n" \ + #name "_1:\n" \ + ".cfi_startproc\n" \ + "movq $1,%rdi\n" \ + /* Overwrite %rdi with 2. */ \ + ".globl " #name "_2\n" \ + #name "_2:\n" \ + "movq $2,%rdi\n" \ + "ret\n" \ + /* End of code. */ \ + ".globl " #name "_end\n" \ + #name "_end:\n" \ + ".cfi_endproc\n" \ + /* Go to the next page. */ \ + ".align 0x1000"); + +/* noexec_1 is executable, noexec_2 is non-executable. */ +DEFINE_NX(noexec, 0xff9); + +/* + * noexec_cross_1 is executable, noexec_cross_2 crosses non-executable page + * boundary. + */ +DEFINE_NX(noexec_cross, 0xff8); + +/* noexec_full_1 and noexec_full_2 are non-executable. */ +DEFINE_NX(noexec_full, 0x321); + +int main(void) +{ + struct noexec_test noexec_tests[] =3D { + { + .name =3D "Fallthrough", + .func =3D noexec_1, + .page =3D noexec_2, + .expected_si_addr =3D noexec_2, + .arch =3D { + .expected_rip =3D noexec_2, + .expected_rdi =3D 1, + }, + }, + { + .name =3D "Jump", + .func =3D noexec_2, + .page =3D noexec_2, + .expected_si_addr =3D noexec_2, + .arch =3D { + .expected_rip =3D noexec_2, + .expected_rdi =3D 0, + }, + }, + { + .name =3D "Fallthrough [cross]", + .func =3D noexec_cross_1, + .page =3D PAGE_ALIGN(noexec_cross_end), + .expected_si_addr =3D PAGE_ALIGN(noexec_cross_end), + .arch =3D { + .expected_rip =3D noexec_cross_2, + .expected_rdi =3D 1, + }, + }, + { + .name =3D "Jump [cross]", + .func =3D noexec_cross_2, + .page =3D PAGE_ALIGN(noexec_cross_end), + .expected_si_addr =3D PAGE_ALIGN(noexec_cross_end), + .arch =3D { + .expected_rip =3D noexec_cross_2, + .expected_rdi =3D 0, + }, + }, + { + .name =3D "Jump [full]", + .func =3D noexec_full_1, + .page =3D PAGE_ALIGN(noexec_full_1), + .expected_si_addr =3D noexec_full_1, + .arch =3D { + .expected_rip =3D noexec_full_1, + .expected_rdi =3D 0, + }, + }, + }; + + return test_noexec(noexec_tests, + sizeof(noexec_tests) / sizeof(noexec_tests[0])); +} --=20 2.35.3