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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1659577490438100001 Content-Type: text/plain; charset="utf-8" Historically, The mtime/mtimecmp has been part of the CPU because they are per hart entities. However, they actually belong to aclint which is a MMIO device. Move them to the ACLINT device. This also emulates the real hardware more closely. Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- hw/intc/riscv_aclint.c | 41 ++++++++++++++++++++++++---------- hw/timer/ibex_timer.c | 18 ++++++--------- include/hw/intc/riscv_aclint.h | 2 ++ include/hw/timer/ibex_timer.h | 2 ++ target/riscv/cpu.h | 2 -- target/riscv/machine.c | 5 ++--- 6 files changed, 42 insertions(+), 28 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e7942c4e5a32..a125c73d535c 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -32,6 +32,7 @@ #include "hw/intc/riscv_aclint.h" #include "qemu/timer.h" #include "hw/irq.h" +#include "migration/vmstate.h" =20 typedef struct riscv_aclint_mtimer_callback { RISCVAclintMTimerState *s; @@ -65,8 +66,8 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclint= MTimerState *mtimer, =20 uint64_t rtc_r =3D cpu_riscv_read_rtc(mtimer); =20 - cpu->env.timecmp =3D value; - if (cpu->env.timecmp <=3D rtc_r) { + mtimer->timecmp[hartid] =3D value; + if (mtimer->timecmp[hartid] <=3D rtc_r) { /* * If we're setting an MTIMECMP value in the "past", * immediately raise the timer interrupt @@ -77,7 +78,7 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclint= MTimerState *mtimer, =20 /* otherwise, set up the future timer interrupt */ qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]); - diff =3D cpu->env.timecmp - rtc_r; + diff =3D mtimer->timecmp[hartid] - rtc_r; /* back to ns (note args switched in muldiv64) */ uint64_t ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_f= req); =20 @@ -102,7 +103,7 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAcli= ntMTimerState *mtimer, next =3D MIN(next, INT64_MAX); } =20 - timer_mod(cpu->env.timer, next); + timer_mod(mtimer->timers[hartid], next); } =20 /* @@ -133,11 +134,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque= , hwaddr addr, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) =3D=3D 0) { /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ - uint64_t timecmp =3D env->timecmp; + uint64_t timecmp =3D mtimer->timecmp[hartid]; return (size =3D=3D 4) ? (timecmp & 0xFFFFFFFF) : timecmp; } else if ((addr & 0x7) =3D=3D 4) { /* timecmp_hi */ - uint64_t timecmp =3D env->timecmp; + uint64_t timecmp =3D mtimer->timecmp[hartid]; return (timecmp >> 32) & 0xFFFFFFFF; } else { qemu_log_mask(LOG_UNIMP, @@ -177,7 +178,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } else if ((addr & 0x7) =3D=3D 0) { if (size =3D=3D 4) { /* timecmp_lo for RV32/RV64 */ - uint64_t timecmp_hi =3D env->timecmp >> 32; + uint64_t timecmp_hi =3D mtimer->timecmp[hartid] >> 32; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, timecmp_hi << 32 | (value & 0xFFFFFFFF)); } else { @@ -188,7 +189,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } else if ((addr & 0x7) =3D=3D 4) { if (size =3D=3D 4) { /* timecmp_hi for RV32/RV64 */ - uint64_t timecmp_lo =3D env->timecmp; + uint64_t timecmp_lo =3D mtimer->timecmp[hartid]; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { @@ -234,7 +235,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), mtimer->hartid_base + i, - env->timecmp); + mtimer->timecmp[i]); } return; } @@ -284,6 +285,8 @@ static void riscv_aclint_mtimer_realize(DeviceState *de= v, Error **errp) s->timer_irqs =3D g_new(qemu_irq, s->num_harts); qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts); =20 + s->timers =3D g_new0(QEMUTimer *, s->num_harts); + s->timecmp =3D g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i =3D 0; i < s->num_harts; i++) { RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); @@ -310,6 +313,18 @@ static void riscv_aclint_mtimer_reset_enter(Object *ob= j, ResetType type) riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); } =20 +static const VMStateDescription vmstate_riscv_mtimer =3D { + .name =3D "riscv_mtimer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(timecmp, RISCVAclintMTimerState, + num_harts, 0, + vmstate_info_uint64, uint64_t), + VMSTATE_END_OF_LIST() + } +}; + static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -317,6 +332,7 @@ static void riscv_aclint_mtimer_class_init(ObjectClass = *klass, void *data) device_class_set_props(dc, riscv_aclint_mtimer_properties); ResettableClass *rc =3D RESETTABLE_CLASS(klass); rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; + dc->vmsd =3D &vmstate_riscv_mtimer; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { @@ -336,6 +352,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, { int i; DeviceState *dev =3D qdev_new(TYPE_RISCV_ACLINT_MTIMER); + RISCVAclintMTimerState *s =3D RISCV_ACLINT_MTIMER(dev); =20 assert(num_harts <=3D RISCV_ACLINT_MAX_HARTS); assert(!(addr & 0x7)); @@ -366,11 +383,11 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, = hwaddr size, riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); } =20 - cb->s =3D RISCV_ACLINT_MTIMER(dev); + cb->s =3D s; cb->num =3D i; - env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + s->timers[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_aclint_mtimer_cb, cb); - env->timecmp =3D 0; + s->timecmp[i] =3D 0; =20 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER)= ); diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 8c2ca364daab..d8b8e4e1f602 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -60,8 +60,6 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) =20 static void ibex_timer_update_irqs(IbexTimerState *s) { - CPUState *cs =3D qemu_get_cpu(0); - RISCVCPU *cpu =3D RISCV_CPU(cs); uint64_t value =3D s->timer_compare_lower0 | ((uint64_t)s->timer_compare_upper0 << 32); uint64_t next, diff; @@ -73,9 +71,9 @@ static void ibex_timer_update_irqs(IbexTimerState *s) } =20 /* Update the CPUs mtimecmp */ - cpu->env.timecmp =3D value; + s->mtimecmp =3D value; =20 - if (cpu->env.timecmp <=3D now) { + if (s->mtimecmp <=3D now) { /* * If the mtimecmp was in the past raise the interrupt now. */ @@ -91,7 +89,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s) qemu_irq_lower(s->m_timer_irq); qemu_set_irq(s->irq, false); =20 - diff =3D cpu->env.timecmp - now; + diff =3D s->mtimecmp - now; next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + muldiv64(diff, NANOSECONDS_PER_SECOND, @@ -99,9 +97,9 @@ static void ibex_timer_update_irqs(IbexTimerState *s) =20 if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { /* We overflowed the timer, just set it as large as we can */ - timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF); + timer_mod(s->mtimer, 0x7FFFFFFFFFFFFFFF); } else { - timer_mod(cpu->env.timer, next); + timer_mod(s->mtimer, next); } } =20 @@ -120,11 +118,9 @@ static void ibex_timer_reset(DeviceState *dev) { IbexTimerState *s =3D IBEX_TIMER(dev); =20 - CPUState *cpu =3D qemu_get_cpu(0); - CPURISCVState *env =3D cpu->env_ptr; - env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + s->mtimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ibex_timer_cb, s); - env->timecmp =3D 0; + s->mtimecmp =3D 0; =20 s->timer_ctrl =3D 0x00000000; s->timer_cfg0 =3D 0x00010000; diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 26d4048687fb..693415eb6def 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -32,6 +32,8 @@ typedef struct RISCVAclintMTimerState { /*< private >*/ SysBusDevice parent_obj; uint64_t time_delta; + uint64_t *timecmp; + QEMUTimer **timers; =20 /*< public >*/ MemoryRegion mmio; diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h index 1a0a28d5fab5..41f5c82a920b 100644 --- a/include/hw/timer/ibex_timer.h +++ b/include/hw/timer/ibex_timer.h @@ -33,6 +33,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER) struct IbexTimerState { /* */ SysBusDevice parent_obj; + uint64_t mtimecmp; + QEMUTimer *mtimer; /* Internal timer for M-mode interrupt */ =20 /* */ MemoryRegion mmio; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4be4b82a837d..0fae1569945c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -308,7 +308,6 @@ struct CPUArchState { /* temporary htif regs */ uint64_t mfromhost; uint64_t mtohost; - uint64_t timecmp; =20 /* physical memory protection */ pmp_table_t pmp_state; @@ -363,7 +362,6 @@ struct CPUArchState { float_status fp_status; =20 /* Fields from here on are preserved across CPU reset. */ - QEMUTimer *timer; /* Internal timer */ =20 hwaddr kernel_addr; hwaddr fdt_addr; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index dc182ca81119..b508b042cb73 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -307,8 +307,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -359,7 +359,6 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), VMSTATE_UINT64(env.mtohost, RISCVCPU), - VMSTATE_UINT64(env.timecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() }, --=20 2.25.1