From nobody Tue Feb 10 01:34:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659534157818929.9988929380423; Wed, 3 Aug 2022 06:42:37 -0700 (PDT) Received: from localhost ([::1]:52586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oJEdv-00046L-PV for importer@patchew.org; Wed, 03 Aug 2022 09:42:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJERH-0003VQ-T2; Wed, 03 Aug 2022 09:29:31 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:57147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJERF-0000X7-OJ; Wed, 03 Aug 2022 09:29:31 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LyXlC5Bvsz4xG9; Wed, 3 Aug 2022 23:29:27 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LyXl96lYjz4xGH; Wed, 3 Aug 2022 23:29:25 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 14/20] ppc/ppc405: QOM'ify POB Date: Wed, 3 Aug 2022 15:28:38 +0200 Message-Id: <20220803132844.2370514-15-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220803132844.2370514-1-clg@kaod.org> References: <20220803132844.2370514-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=fO70=YH=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1659534158388100001 Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405.h | 14 +++++++++++ hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++++++++--------------- 2 files changed, 53 insertions(+), 19 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 808662d81599..8acb90427596 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t { =20 typedef struct Ppc405SoCState Ppc405SoCState; =20 +/* PLB to OPB bridge */ +#define TYPE_PPC405_POB "ppc405-pob" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB); +struct Ppc405PobState { + DeviceState parent_obj; + + PowerPCCPU *cpu; + + uint32_t bear; + uint32_t besr0; + uint32_t besr1; +}; + /* OPB arbitrer */ #define TYPE_PPC405_OPBA "ppc405-opba" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA); @@ -231,6 +244,7 @@ struct Ppc405SoCState { Ppc405DmaState dma; Ppc405EbcState ebc; Ppc405OpbaState opba; + Ppc405PobState pob; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 04f7af0f8f09..ca214ee4d741 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -234,19 +234,11 @@ enum { POB0_BEAR =3D 0x0A4, }; =20 -typedef struct ppc4xx_pob_t ppc4xx_pob_t; -struct ppc4xx_pob_t { - uint32_t bear; - uint32_t besr0; - uint32_t besr1; -}; - static uint32_t dcr_read_pob (void *opaque, int dcrn) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D PPC405_POB(opaque); uint32_t ret; =20 - pob =3D opaque; switch (dcrn) { case POB0_BEAR: ret =3D pob->bear; @@ -268,9 +260,8 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn) =20 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D PPC405_POB(opaque); =20 - pob =3D opaque; switch (dcrn) { case POB0_BEAR: /* Read only */ @@ -286,26 +277,44 @@ static void dcr_write_pob (void *opaque, int dcrn, ui= nt32_t val) } } =20 -static void ppc4xx_pob_reset (void *opaque) +static void ppc405_pob_reset(DeviceState *dev) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D PPC405_POB(dev); =20 - pob =3D opaque; /* No error */ pob->bear =3D 0x00000000; pob->besr0 =3D 0x0000000; pob->besr1 =3D 0x0000000; } =20 -static void ppc4xx_pob_init(CPUPPCState *env) +static void ppc405_pob_realize(DeviceState *dev, Error **errp) { - ppc4xx_pob_t *pob; + Ppc405PobState *pob =3D PPC405_POB(dev); + CPUPPCState *env; + + assert(pob->cpu); + + env =3D &pob->cpu->env; =20 - pob =3D g_new0(ppc4xx_pob_t, 1); ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); - qemu_register_reset(ppc4xx_pob_reset, pob); +} + +static Property ppc405_pob_properties[] =3D { + DEFINE_PROP_LINK("cpu", Ppc405PobState, cpu, TYPE_POWERPC_CPU, + PowerPCCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc405_pob_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_pob_realize; + dc->user_creatable =3D false; + dc->reset =3D ppc405_pob_reset; + device_class_set_props(dc, ppc405_pob_properties); } =20 /*************************************************************************= ****/ @@ -1435,6 +1444,8 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC); =20 object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA); + + object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB); } =20 static void ppc405_soc_realize(DeviceState *dev, Error **errp) @@ -1476,7 +1487,11 @@ static void ppc405_soc_realize(DeviceState *dev, Err= or **errp) ppc4xx_plb_init(env); =20 /* PLB to OPB bridge */ - ppc4xx_pob_init(env); + object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu), + &error_abort); + if (!qdev_realize(DEVICE(&s->pob), NULL, errp)) { + return; + } =20 /* OBP arbitrer */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) { @@ -1600,6 +1615,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_POB, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(Ppc405PobState), + .class_init =3D ppc405_pob_class_init, + }, { .name =3D TYPE_PPC405_OPBA, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405OpbaState), --=20 2.37.1