From nobody Tue Feb 10 15:46:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659533895227151.9904867802917; Wed, 3 Aug 2022 06:38:15 -0700 (PDT) Received: from localhost ([::1]:42540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oJEZi-0005j1-1g for importer@patchew.org; Wed, 03 Aug 2022 09:38:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJER9-00033p-W8; Wed, 03 Aug 2022 09:29:24 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:53853 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJER7-0000Xr-Qy; Wed, 03 Aug 2022 09:29:23 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LyXl45xS4z4xGK; Wed, 3 Aug 2022 23:29:20 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LyXl30Kktz4xGH; Wed, 3 Aug 2022 23:29:18 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v2 11/20] ppc/ppc405: QOM'ify DMA Date: Wed, 3 Aug 2022 15:28:35 +0200 Message-Id: <20220803132844.2370514-12-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220803132844.2370514-1-clg@kaod.org> References: <20220803132844.2370514-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=fO70=YH=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1659533895541100001 Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater --- hw/ppc/ppc405.h | 23 +++++++++++++ hw/ppc/ppc405_uc.c | 80 +++++++++++++++++++++++++++++----------------- 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 36f6fd45217e..1da34a7f10f3 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -65,6 +65,28 @@ struct ppc4xx_bd_info_t { =20 typedef struct Ppc405SoCState Ppc405SoCState; =20 + + +/* DMA controller */ +#define TYPE_PPC405_DMA "ppc405-dma" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA); +struct Ppc405DmaState { + SysBusDevice parent_obj; + + PowerPCCPU *cpu; + + qemu_irq irqs[4]; + uint32_t cr[4]; + uint32_t ct[4]; + uint32_t da[4]; + uint32_t sa[4]; + uint32_t sg[4]; + uint32_t sr; + uint32_t sgc; + uint32_t slp; + uint32_t pol; +}; + /* GPIO */ #define TYPE_PPC405_GPIO "ppc405-gpio" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO); @@ -180,6 +202,7 @@ struct Ppc405SoCState { Ppc405GptState gpt; Ppc405OcmState ocm; Ppc405GpioState gpio; + Ppc405DmaState dma; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index bd018804594a..6bd93c1cb90c 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -613,35 +613,20 @@ enum { DMA0_POL =3D 0x126, }; =20 -typedef struct ppc405_dma_t ppc405_dma_t; -struct ppc405_dma_t { - qemu_irq irqs[4]; - uint32_t cr[4]; - uint32_t ct[4]; - uint32_t da[4]; - uint32_t sa[4]; - uint32_t sg[4]; - uint32_t sr; - uint32_t sgc; - uint32_t slp; - uint32_t pol; -}; - -static uint32_t dcr_read_dma (void *opaque, int dcrn) +static uint32_t dcr_read_dma(void *opaque, int dcrn) { return 0; } =20 -static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) +static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) { } =20 -static void ppc405_dma_reset (void *opaque) +static void ppc405_dma_reset(DeviceState *dev) { - ppc405_dma_t *dma; + Ppc405DmaState *dma =3D PPC405_DMA(dev); int i; =20 - dma =3D opaque; for (i =3D 0; i < 4; i++) { dma->cr[i] =3D 0x00000000; dma->ct[i] =3D 0x00000000; @@ -655,13 +640,20 @@ static void ppc405_dma_reset (void *opaque) dma->pol =3D 0x00000000; } =20 -static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) +static void ppc405_dma_realize(DeviceState *dev, Error **errp) { - ppc405_dma_t *dma; + Ppc405DmaState *dma =3D PPC405_DMA(dev); + CPUPPCState *env; + int i; + + assert(dma->cpu); + + env =3D &dma->cpu->env; + + for (i =3D 0; i < ARRAY_SIZE(dma->irqs); i++) { + sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]); + } =20 - dma =3D g_new0(ppc405_dma_t, 1); - memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); - qemu_register_reset(&ppc405_dma_reset, dma); ppc_dcr_register(env, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma); ppc_dcr_register(env, DMA0_CT0, @@ -712,6 +704,22 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq= irqs[4]) dma, &dcr_read_dma, &dcr_write_dma); } =20 +static Property ppc405_dma_properties[] =3D { + DEFINE_PROP_LINK("cpu", Ppc405DmaState, cpu, TYPE_POWERPC_CPU, + PowerPCCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ppc405_dma_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_dma_realize; + dc->user_creatable =3D false; + dc->reset =3D ppc405_dma_reset; + device_class_set_props(dc, ppc405_dma_properties); +} + /*************************************************************************= ****/ static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { @@ -1408,12 +1416,14 @@ static void ppc405_soc_instance_init(Object *obj) object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM); =20 object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO); + + object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA); } =20 static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - qemu_irq dma_irqs[4], mal_irqs[4]; + qemu_irq mal_irqs[4]; CPUPPCState *env; Error *err =3D NULL; int i; @@ -1483,11 +1493,16 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) ppc405_ebc_init(env); =20 /* DMA controller */ - dma_irqs[0] =3D qdev_get_gpio_in(s->uic, 5); - dma_irqs[1] =3D qdev_get_gpio_in(s->uic, 6); - dma_irqs[2] =3D qdev_get_gpio_in(s->uic, 7); - dma_irqs[3] =3D qdev_get_gpio_in(s->uic, 8); - ppc405_dma_init(env, dma_irqs); + object_property_set_link(OBJECT(&s->dma), "cpu", OBJECT(&s->cpu), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp)) { + return; + } + + for (i =3D 0; i < ARRAY_SIZE(s->dma.irqs); i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, + qdev_get_gpio_in(s->uic, 5 + i)); + } =20 /* I2C controller */ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, @@ -1561,6 +1576,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_DMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405DmaState), + .class_init =3D ppc405_dma_class_init, + }, { .name =3D TYPE_PPC405_GPIO, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(Ppc405GpioState), --=20 2.37.1