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Tsirkin" , Marcel Apfelbaum , Cornelia Huck , Marcelo Tosatti , Laszlo Ersek , Eric Blake Cc: Connor Kuehl , erdemaktas@google.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, seanjc@google.com, xiaoyao.li@intel.com Subject: [PATCH v1 10/40] i386/tdx: Integrate tdx_caps->xfam_fixed0/1 into tdx_cpuid_lookup Date: Tue, 2 Aug 2022 15:47:20 +0800 Message-Id: <20220802074750.2581308-11-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220802074750.2581308-1-xiaoyao.li@intel.com> References: <20220802074750.2581308-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.93; envelope-from=xiaoyao.li@intel.com; helo=mga11.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.998, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1659427229555100001 Content-Type: text/plain; charset="utf-8" KVMM requires userspace to pass XFAM configuration via CPUID leaves 0xDs. Convert tdx_caps->xfam_fixed0/1 into corresponding tdx_cpuid_lookup[].tdx_fixed0/1 field of CPUID leaves 0xD. Thus the requirement can applied naturally. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 3 --- target/i386/cpu.h | 3 +++ target/i386/kvm/tdx.c | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 194b5a31afac..45652bb2fd7c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1418,9 +1418,6 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_NB= _REGS32] =3D { }; #undef REGISTER =20 -/* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) - ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] =3D { [XSTATE_FP_BIT] =3D { /* x87 FP state component is always enabled if XSAVE is supported = */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cc9da9fc4318..90f403aecd8b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -583,6 +583,9 @@ typedef enum X86Seg { XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK |= \ XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA= _MASK) =20 +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index d12b03fa05c9..dffaa533f899 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -395,6 +395,30 @@ static void update_tdx_cpuid_lookup_by_tdx_caps(void) entry->tdx_fixed0 &=3D ~config; entry->tdx_fixed1 &=3D ~config; } + + /* + * Because KVM gets XFAM settings via CPUID leaves 0xD, map + * tdx_caps->xfam_fixed{0, 1} into tdx_cpuid_lookup[].tdx_fixed{0, 1}. + * + * Then the enforment applies in tdx_get_configurable_cpuid() naturall= y. + */ + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_LO].tdx_fixed0 =3D + (uint32_t)~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XCR0_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_LO].tdx_fixed1 =3D + (uint32_t)tdx_caps->xfam_fixed1 & CPUID_XSTATE_XCR0_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_HI].tdx_fixed0 =3D + (~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XCR0_MASK) >> 32; + tdx_cpuid_lookup[FEAT_XSAVE_XCR0_HI].tdx_fixed1 =3D + (tdx_caps->xfam_fixed1 & CPUID_XSTATE_XCR0_MASK) >> 32; + + tdx_cpuid_lookup[FEAT_XSAVE_XSS_LO].tdx_fixed0 =3D + (uint32_t)~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XSS_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XSS_LO].tdx_fixed1 =3D + (uint32_t)tdx_caps->xfam_fixed1 & CPUID_XSTATE_XSS_MASK; + tdx_cpuid_lookup[FEAT_XSAVE_XSS_HI].tdx_fixed0 =3D + (~tdx_caps->xfam_fixed0 & CPUID_XSTATE_XSS_MASK) >> 32; + tdx_cpuid_lookup[FEAT_XSAVE_XSS_HI].tdx_fixed1 =3D + (tdx_caps->xfam_fixed1 & CPUID_XSTATE_XSS_MASK) >> 32; } =20 int tdx_kvm_init(MachineState *ms, Error **errp) --=20 2.27.0