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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=mchitale@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1659375592533100001 Content-Type: text/plain; charset="utf-8" Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 37 ++++ target/riscv/csr.c | 369 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 21 +++ 4 files changed, 431 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4be4b82a83..6bff935c57 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -354,6 +354,9 @@ struct CPUArchState { =20 /* CSRs for execution enviornment configuration */ uint64_t menvcfg; + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; target_ulong senvcfg; uint64_t henvcfg; #endif @@ -427,6 +430,7 @@ struct RISCVCPUConfig { bool ext_ifencei; bool ext_icsr; bool ext_zihintpause; + bool ext_smstateen; bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 6be5a9e9f0..c773e0d310 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -199,6 +199,12 @@ /* Supervisor Configuration CSRs */ #define CSR_SENVCFG 0x10A =20 +/* Supervisor state CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -242,6 +248,16 @@ #define CSR_HENVCFG 0x60A #define CSR_HENVCFGH 0x61A =20 +/* Hypervisor state CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -283,6 +299,27 @@ #define CSR_MENVCFG 0x30A #define CSR_MENVCFGH 0x31A =20 +/* Machine state CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Common defines for all smstateen */ +#define SMSTATEEN_MAX_COUNT 4 +#define SMSTATEEN0_CS (1ULL << 0) +#define SMSTATEEN0_FCSR (1ULL << 1) +#define SMSTATEEN0_HSCONTXT (1ULL << 57) +#define SMSTATEEN0_IMSIC (1ULL << 58) +#define SMSTATEEN0_AIA (1ULL << 59) +#define SMSTATEEN0_SVSLCT (1ULL << 60) +#define SMSTATEEN0_HSENVCFG (1ULL << 62) +#define SMSTATEEN_STATEEN (1ULL << 63) + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0fb042b2fd..ad1642fb9b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -346,6 +346,68 @@ static RISCVException umode32(CPURISCVState *env, int = csrno) return umode(env, csrno); } =20 +static RISCVException mstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + +static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int bas= e) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + +static RISCVException hstateen(CPURISCVState *env, int csrno) +{ + return hstateen_pred(env, csrno, CSR_HSTATEEN0); +} + +static RISCVException hstateenh(CPURISCVState *env, int csrno) +{ + return hstateen_pred(env, csrno, CSR_HSTATEEN0H); +} + +static RISCVException sstateen(CPURISCVState *env, int csrno) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + int index =3D csrno - CSR_SSTATEEN0; + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + return smode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -1706,6 +1768,263 @@ static RISCVException write_henvcfgh(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, + uint64_t wr_mask, uint64_t new_val) +{ + *reg =3D (*reg & ~wr_mask) | (new_val & wr_mask); +} + +static RISCVException read_mstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen(CPURISCVState *env, int csrno, + uint64_t wr_mask, target_ulong new_va= l) +{ + uint64_t *reg; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_mstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_mstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, + uint64_t wr_mask, target_ulong new_v= al) +{ + uint64_t *reg, val; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_mstateenh(env, csrno, wr_mask, new_val); +} + +static RISCVException write_mstateen1h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen2h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen3h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_hstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D csrno - CSR_HSTATEEN0; + + *val =3D env->hstateen[index] & env->mstateen[index]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + int index =3D csrno - CSR_HSTATEEN0; + uint64_t *reg, wr_mask; + + reg =3D &env->hstateen[index]; + wr_mask =3D env->mstateen[index] & mask; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_hstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_hstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D csrno - CSR_HSTATEEN0H; + + *val =3D (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + int index =3D csrno - CSR_HSTATEEN0H; + uint64_t *reg, wr_mask, val; + + reg =3D &env->hstateen[index]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + wr_mask =3D env->mstateen[index] & mask; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_hstateenh(env, csrno, wr_mask, new_val); +} + +static RISCVException write_hstateen1h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen2h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen3h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_sstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + int index =3D csrno - CSR_SSTATEEN0; + + *val =3D env->sstateen[index] & env->mstateen[index]; + if (virt) { + *val &=3D env->hstateen[index]; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + int index =3D csrno - CSR_SSTATEEN0; + uint64_t wr_mask; + uint64_t *reg; + + wr_mask =3D env->mstateen[index] & mask; + if (virt) { + wr_mask &=3D env->hstateen[index]; + } + + reg =3D &env->sstateen[index]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask =3D SMSTATEEN_STATEEN; + + return write_sstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_sstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_sstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_sstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3569,6 +3888,56 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 + /* Smstateen extension CSRs */ + [CSR_MSTATEEN0] =3D { "mstateen0", mstateen, read_mstateen, write_msta= teen0, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN0H] =3D { "mstateen0h", mstateen, read_mstateenh, + write_mstateen0h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1] =3D { "mstateen1", mstateen, read_mstateen, write_msta= teen1, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1H] =3D { "mstateen1h", mstateen, read_mstateenh, + write_mstateen1h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2] =3D { "mstateen2", mstateen, read_mstateen, write_msta= teen2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2H] =3D { "mstateen2h", mstateen, read_mstateenh, + write_mstateen2h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3] =3D { "mstateen3", mstateen, read_mstateen, write_msta= teen3, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3H] =3D { "mstateen3h", mstateen, read_mstateenh, + write_mstateen3h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0] =3D { "hstateen0", hstateen, read_hstateen, write_hsta= teen0, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0H] =3D { "hstateen0h", hstateenh, read_hstateenh, + write_hstateen0h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1] =3D { "hstateen1", hstateen, read_hstateen, write_hsta= teen1, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1H] =3D { "hstateen1h", hstateenh, read_hstateenh, + write_hstateen1h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2] =3D { "hstateen2", hstateen, read_hstateen, write_hsta= teen2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2H] =3D { "hstateen2h", hstateenh, read_hstateenh, + write_hstateen2h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3] =3D { "hstateen3", hstateen, read_hstateen, write_hsta= teen3, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3H] =3D { "hstateen3h", hstateenh, read_hstateenh, + write_hstateen3h, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN0] =3D { "sstateen0", sstateen, read_sstateen, write_ssta= teen0, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN1] =3D { "sstateen1", sstateen, read_sstateen, write_ssta= teen1, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN2] =3D { "sstateen2", sstateen, read_sstateen, write_ssta= teen2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN3] =3D { "sstateen3", sstateen, read_sstateen, write_ssta= teen3, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index dc182ca811..ef418ac19d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -262,6 +262,26 @@ static int riscv_cpu_post_load(void *opaque, int versi= on_id) return 0; } =20 +static bool smstateen_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_smstateen; +} + +static const VMStateDescription vmstate_smstateen =3D { + .name =3D "cpu/smtateen", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D smstateen_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), + VMSTATE_END_OF_LIST() + } +}; + static bool envcfg_needed(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -372,6 +392,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_kvmtimer, &vmstate_envcfg, &vmstate_debug, + &vmstate_smstateen, NULL } }; --=20 2.25.1 From nobody Wed May 8 20:42:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Mon, 01 Aug 2022 10:19:32 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com Subject: [PATCH v7 2/4] target/riscv: smstateen check for h/senvcfg Date: Mon, 1 Aug 2022 22:48:41 +0530 Message-Id: <20220801171843.72986-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220801171843.72986-1-mchitale@ventanamicro.com> References: <20220801171843.72986-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=mchitale@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1659374694226100001 Content-Type: text/plain; charset="utf-8" Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- roms/opensbi | 2 +- target/riscv/csr.c | 83 ++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 77 insertions(+), 8 deletions(-) diff --git a/roms/opensbi b/roms/opensbi index 4489876e93..48f91ee9c9 160000 --- a/roms/opensbi +++ b/roms/opensbi @@ -1 +1 @@ -Subproject commit 4489876e933d8ba0d8bc6c64bae71e295d45faac +Subproject commit 48f91ee9c960f048c4a7d1da4447d31e04931e38 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ad1642fb9b..011d6c5976 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -40,6 +40,38 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *= ops) } =20 /* Predicates */ +#if !defined(CONFIG_USER_ONLY) +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, + uint64_t bit) +{ + bool virt =3D riscv_cpu_virt_enabled(env); + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (env->priv =3D=3D PRV_M || !cpu->cfg.ext_smstateen) { + return RISCV_EXCP_NONE; + } + + if (!(env->mstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if (env->priv =3D=3D PRV_U && riscv_has_ext(env, RVS)) { + if (!(env->sstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return RISCV_EXCP_NONE; +} +#endif + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1715,6 +1747,13 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, static RISCVException read_senvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->senvcfg; return RISCV_EXCP_NONE; } @@ -1723,15 +1762,27 @@ static RISCVException write_senvcfg(CPURISCVState *= env, int csrno, target_ulong val) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + RISCVException ret; =20 - env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } =20 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg; return RISCV_EXCP_NONE; } @@ -1740,6 +1791,12 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D HENVCFG_PBMTE | HENVCFG_STCE; @@ -1753,6 +1810,13 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg >> 32; return RISCV_EXCP_NONE; } @@ -1762,9 +1826,14 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, { uint64_t mask =3D HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh =3D (uint64_t)val << 32; + RISCVException ret; =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); return RISCV_EXCP_NONE; } =20 @@ -1796,7 +1865,7 @@ static RISCVException write_mstateen(CPURISCVState *e= nv, int csrno, static RISCVException write_mstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_mstateen(env, csrno, wr_mask, new_val); } @@ -1843,7 +1912,7 @@ static RISCVException write_mstateenh(CPURISCVState *= env, int csrno, static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_mstateenh(env, csrno, wr_mask, new_val); } @@ -1892,7 +1961,7 @@ static RISCVException write_hstateen(CPURISCVState *e= nv, int csrno, static RISCVException write_hstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_hstateen(env, csrno, wr_mask, new_val); } @@ -1943,7 +2012,7 @@ static RISCVException write_hstateenh(CPURISCVState *= env, int csrno, static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; + uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 return write_hstateenh(env, csrno, wr_mask, new_val); } @@ -2002,7 +2071,7 @@ static RISCVException write_sstateen(CPURISCVState *e= nv, int csrno, static RISCVException write_sstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask =3D SMSTATEEN_STATEEN; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=mchitale@ventanamicro.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1659375123347100001 Content-Type: text/plain; charset="utf-8" If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 23 +++++++++++++ target/riscv/insn_trans/trans_rvf.c.inc | 40 +++++++++++++++++++++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ 3 files changed, 72 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 011d6c5976..0512391220 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -79,6 +79,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -1866,6 +1870,9 @@ static RISCVException write_mstateen0(CPURISCVState *= env, int csrno, target_ulong new_val) { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } =20 return write_mstateen(env, csrno, wr_mask, new_val); } @@ -1914,6 +1921,10 @@ static RISCVException write_mstateen0h(CPURISCVState= *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } =20 @@ -1963,6 +1974,10 @@ static RISCVException write_hstateen0(CPURISCVState = *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_hstateen(env, csrno, wr_mask, new_val); } =20 @@ -2014,6 +2029,10 @@ static RISCVException write_hstateen0h(CPURISCVState= *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_hstateenh(env, csrno, wr_mask, new_val); } =20 @@ -2073,6 +2092,10 @@ static RISCVException write_sstateen0(CPURISCVState = *env, int csrno, { uint64_t wr_mask =3D SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; =20 + if (!riscv_has_ext(env, RVF)) { + wr_mask |=3D SMSTATEEN0_FCSR; + } + return write_sstateen(env, csrno, wr_mask, new_val); } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index a1d3eb52ad..ce8a0cc34b 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -24,9 +24,43 @@ return false; \ } while (0) =20 -#define REQUIRE_ZFINX_OR_F(ctx) do {\ - if (!ctx->cfg_ptr->ext_zfinx) { \ - REQUIRE_EXT(ctx, RVF); \ +#ifndef CONFIG_USER_ONLY +static inline bool smstateen_check(DisasContext *ctx, int index) +{ + CPUState *cpu =3D ctx->cs; + CPURISCVState *env =3D cpu->env_ptr; + uint64_t stateen =3D env->mstateen[index]; + + if (!ctx->cfg_ptr->ext_smstateen || env->priv =3D=3D PRV_M) { + return true; + } + + if (ctx->virt_enabled) { + stateen &=3D env->hstateen[index]; + } + + if (env->priv =3D=3D PRV_U && has_ext(ctx, RVS)) { + stateen &=3D env->sstateen[index]; + } + + if (!(stateen & SMSTATEEN0_FCSR)) { + return false; + } + + return true; +} +#else +#define smstateen_check(ctx, index) (true) +#endif + +#define REQUIRE_ZFINX_OR_F(ctx) do { \ + if (!has_ext(ctx, RVF)) { \ + if (!ctx->cfg_ptr->ext_zfinx) { \ + return false; \ + } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } \ } while (0) =20 diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 5d07150cd0..44d962c920 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -20,18 +20,27 @@ if (!ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) =20 #define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ @@ -39,6 +48,9 @@ ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ return false; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=mchitale@ventanamicro.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1659374856677100001 Content-Type: text/plain; charset="utf-8" Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d4635c7df4..d8a0f4e700 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -99,6 +99,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smstateen, true, PRIV_VERSION_1_12_0, ext_smstateen= ), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), @@ -1001,6 +1002,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), --=20 2.25.1