From nobody Tue Feb 10 07:42:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1659359839463517.1774284936405; Mon, 1 Aug 2022 06:17:19 -0700 (PDT) Received: from localhost ([::1]:42814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oIVIM-0005Xo-AI for importer@patchew.org; Mon, 01 Aug 2022 09:17:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oIVCi-0004ME-RR; Mon, 01 Aug 2022 09:11:29 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:34525 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oIVCg-0007J7-Ir; Mon, 01 Aug 2022 09:11:28 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LxJRJ10wfz4xGF; Mon, 1 Aug 2022 23:11:24 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LxJRF6Gdrz4x1L; Mon, 1 Aug 2022 23:11:21 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 08/19] ppc/ppc405: QOM'ify GPT Date: Mon, 1 Aug 2022 15:10:28 +0200 Message-Id: <20220801131039.1693913-9-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220801131039.1693913-1-clg@kaod.org> References: <20220801131039.1693913-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=LBbo=YF=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1659359842459100003 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Daniel Henrique Barboza --- hw/ppc/ppc405.h | 22 ++++++++++++ hw/ppc/ppc405_uc.c | 90 +++++++++++++++++++++++----------------------- 2 files changed, 67 insertions(+), 45 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index d51fb5094e95..f7c0eb1d0008 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -65,6 +65,27 @@ struct ppc4xx_bd_info_t { =20 typedef struct Ppc405SoCState Ppc405SoCState; =20 +/* General purpose timers */ +#define TYPE_PPC405_GPT "ppc405-gpt" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); +struct Ppc405GptState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + int64_t tb_offset; + uint32_t tb_freq; + QEMUTimer *timer; + qemu_irq irqs[5]; + uint32_t oe; + uint32_t ol; + uint32_t im; + uint32_t is; + uint32_t ie; + uint32_t comp[5]; + uint32_t mask[5]; +}; + #define TYPE_PPC405_CPC "ppc405-cpc" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); =20 @@ -119,6 +140,7 @@ struct Ppc405SoCState { PowerPCCPU cpu; DeviceState *uic; Ppc405CpcState cpc; + Ppc405GptState gpt; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 20a3e5543423..0f5e4ec15f14 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env) =20 /*************************************************************************= ****/ /* General purpose timers */ -typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; -struct ppc4xx_gpt_t { - MemoryRegion iomem; - int64_t tb_offset; - uint32_t tb_freq; - QEMUTimer *timer; - qemu_irq irqs[5]; - uint32_t oe; - uint32_t ol; - uint32_t im; - uint32_t is; - uint32_t ie; - uint32_t comp[5]; - uint32_t mask[5]; -}; - -static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) +static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n) { /* XXX: TODO */ return 0; } =20 -static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) +static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level) { /* XXX: TODO */ } =20 -static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt) { uint32_t mask; int i; @@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) } } =20 -static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) { uint32_t mask; int i; @@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) } } =20 -static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt) { /* XXX: TODO */ } =20 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_gpt_t *gpt =3D opaque; + Ppc405GptState *gpt =3D PPC405_GPT(opaque); uint32_t ret; int idx; =20 @@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr = addr, unsigned size) static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_gpt_t *gpt =3D opaque; + Ppc405GptState *gpt =3D PPC405_GPT(opaque); int idx; =20 trace_ppc4xx_gpt_write(addr, size, value); @@ -1116,20 +1100,18 @@ static const MemoryRegionOps gpt_ops =3D { =20 static void ppc4xx_gpt_cb (void *opaque) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *gpt =3D PPC405_GPT(opaque); =20 - gpt =3D opaque; ppc4xx_gpt_set_irqs(gpt); ppc4xx_gpt_set_outputs(gpt); ppc4xx_gpt_compute_timer(gpt); } =20 -static void ppc4xx_gpt_reset (void *opaque) +static void ppc405_gpt_reset(DeviceState *dev) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *gpt =3D PPC405_GPT(dev); int i; =20 - gpt =3D opaque; timer_del(gpt->timer); gpt->oe =3D 0x00000000; gpt->ol =3D 0x00000000; @@ -1142,21 +1124,28 @@ static void ppc4xx_gpt_reset (void *opaque) } } =20 -static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) +static void ppc405_gpt_realize(DeviceState *dev, Error **errp) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *s =3D PPC405_GPT(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); int i; =20 - trace_ppc4xx_gpt_init(base); + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s); + memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0x0d4); + sysbus_init_mmio(sbd, &s->iomem); =20 - gpt =3D g_new0(ppc4xx_gpt_t, 1); - for (i =3D 0; i < 5; i++) { - gpt->irqs[i] =3D irqs[i]; + for (i =3D 0; i < ARRAY_SIZE(s->irqs); i++) { + sysbus_init_irq(sbd, &s->irqs[i]); } - gpt->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); - memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); - memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); - qemu_register_reset(ppc4xx_gpt_reset, gpt); +} + +static void ppc405_gpt_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_gpt_realize; + dc->user_creatable =3D false; + dc->reset =3D ppc405_gpt_reset; } =20 /*************************************************************************= ****/ @@ -1422,14 +1411,17 @@ static void ppc405_soc_instance_init(Object *obj) =20 object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); + + object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); } =20 static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; + qemu_irq dma_irqs[4], mal_irqs[4]; CPUPPCState *env; Error *err =3D NULL; + int i; =20 /* XXX: fix this ? */ memory_region_init_alias(&s->ram_memories[0], OBJECT(s), @@ -1528,12 +1520,15 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) ppc405_ocm_init(env); =20 /* GPT */ - gpt_irqs[0] =3D qdev_get_gpio_in(s->uic, 19); - gpt_irqs[1] =3D qdev_get_gpio_in(s->uic, 20); - gpt_irqs[2] =3D qdev_get_gpio_in(s->uic, 21); - gpt_irqs[3] =3D qdev_get_gpio_in(s->uic, 22); - gpt_irqs[4] =3D qdev_get_gpio_in(s->uic, 23); - ppc4xx_gpt_init(0xef600000, gpt_irqs); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, 0xef600000); + + for (i =3D 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), i, + qdev_get_gpio_in(s->uic, 19 + i)); + } =20 /* MAL */ mal_irqs[0] =3D qdev_get_gpio_in(s->uic, 11); @@ -1565,6 +1560,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_GPT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405GptState), + .class_init =3D ppc405_gpt_class_init, + }, { .name =3D TYPE_PPC405_CPC, .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(Ppc405CpcState), --=20 2.37.1