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Tsirkin" Subject: [PATCH v3] hw/pci/pci_bridge: ensure PCIe slots have only one slot Date: Wed, 20 Jul 2022 13:25:55 +0300 Message-Id: <20220720102555.874394-1-rvkagan@yandex-team.ru> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:0:1a2d::193; envelope-from=rvkagan@yandex-team.ru; helo=forwardcorp1o.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @yandex-team.ru) X-ZM-MESSAGEID: 1658312890840100001 Content-Type: text/plain; charset="utf-8" It's possible to create non-working configurations by attaching a device to a derivative of PCIe slot (pcie-root-port, ioh3420, etc) and specifying a slot number other that zero, e.g.: -device pcie-root-port,id=3Ds0,... \ -device virtio-blk-pci,bus=3Ds0,addr=3D4,... Make QEMU reject such configurations and only allow addr=3D0 on the secondary bus of a PCIe slot. To verify this new behavior, add two basic qtests for the PCIe bridges that may be affected by change: pcie-root-port and x3130. For the former, two testcases are included, one positive for slot #0 and one negative for (arbitrary) slot #4; for the latter, only a positive testcase for slot #4 is included. Signed-off-by: Roman Kagan Acked-by: Thomas Huth --- v2 -> v3: - do not use qtest-single stuff [Thomas] v1 -> v2: - use object_dynamic_cast (without assert) [Vladimir] - add explaining comment [Michael] - add tests hw/pci/pci_bridge.c | 6 +++ tests/qtest/pcie-root-port-test.c | 75 +++++++++++++++++++++++++++++++ tests/qtest/xio3130-test.c | 52 +++++++++++++++++++++ tests/qtest/meson.build | 2 + 4 files changed, 135 insertions(+) create mode 100644 tests/qtest/pcie-root-port-test.c create mode 100644 tests/qtest/xio3130-test.c diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index da34c8ebcd..23e1701d06 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -33,6 +33,7 @@ #include "qemu/units.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pcie_port.h" #include "qemu/module.h" #include "qemu/range.h" #include "qapi/error.h" @@ -386,6 +387,11 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typ= ename) br->windows =3D pci_bridge_region_init(br); QLIST_INIT(&sec_bus->child); QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); + + /* PCIe slot derivatives are bridges with a single slot; enforce that = */ + if (object_dynamic_cast(OBJECT(dev), TYPE_PCIE_SLOT)) { + sec_bus->slot_reserved_mask =3D ~1u; + } } =20 /* default qdev clean up function for PCI-to-PCI bridge */ diff --git a/tests/qtest/pcie-root-port-test.c b/tests/qtest/pcie-root-port= -test.c new file mode 100644 index 0000000000..c462f03fda --- /dev/null +++ b/tests/qtest/pcie-root-port-test.c @@ -0,0 +1,75 @@ +/* + * QTest testcase for generic PCIe root port + * + * Copyright (c) 2022 Yandex N.V. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +/* + * Let QEMU choose the bus and slot for the device under test. It may eve= n be + * a non-PCIe bus but it's ok for the purpose of the test. + */ +static const char *common_args =3D "-device pcie-root-port,id=3Ds0" + ",port=3D1,chassis=3D1,multifunction=3Don= "; + +static void test_slot0(void) +{ + QTestState *qts; + QDict *resp; + + /* attach a PCIe device into slot0 of the root port */ + qts =3D qtest_init(common_args); + /* PCIe root port is known to be supported, use it as a leaf device to= o */ + resp =3D qtest_qmp(qts, "{'execute': 'device_add', 'arguments': {" + "'driver': 'pcie-root-port', " + "'id': 'port1', " + "'bus': 's0', " + "'chassis': 5, " + "'addr': '0'" + "} }"); + g_assert_nonnull(resp); + g_assert(!qdict_haskey(resp, "event")); + g_assert(!qdict_haskey(resp, "error")); + qobject_unref(resp); + + qtest_quit(qts); +} + +static void test_slot4(void) +{ + QTestState *qts; + QDict *resp; + + /* attach a PCIe device into slot4 of the root port should be rejected= */ + qts =3D qtest_init(common_args); + /* PCIe root port is known to be supported, use it as a leaf device to= o */ + resp =3D qtest_qmp(qts, "{'execute': 'device_add', 'arguments': {" + "'driver': 'pcie-root-port', " + "'id': 'port1', " + "'bus': 's0', " + "'chassis': 5, " + "'addr': '4'" + "} }"); + qmp_expect_error_and_unref(resp, "GenericError"); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/pcie-root-port/slot0", test_slot0); + qtest_add_func("/pcie-root-port/slot4", test_slot4); + + ret =3D g_test_run(); + + return ret; +} diff --git a/tests/qtest/xio3130-test.c b/tests/qtest/xio3130-test.c new file mode 100644 index 0000000000..8306da4aea --- /dev/null +++ b/tests/qtest/xio3130-test.c @@ -0,0 +1,52 @@ +/* + * QTest testcase for TI X3130 PCIe switch + * + * Copyright (c) 2022 Yandex N.V. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +/* + * Let QEMU choose the bus and slot for the device under test. It may eve= n be + * a non-PCIe bus but it's ok for the purpose of the test. + */ +static const char *common_args =3D "-device x3130-upstream,id=3Ds0"; + +static void test_slot4(void) +{ + QTestState *qts; + QDict *resp; + + /* attach a downstream port into slot4 of the upstream port */ + qts =3D qtest_init(common_args); + resp =3D qtest_qmp(qts, "{'execute': 'device_add', 'arguments': {" + "'driver': 'xio3130-downstream', " + "'id': 'port1', " + "'bus': 's0', " + "'chassis': 5, " + "'addr': '4'" + "} }"); + g_assert_nonnull(resp); + g_assert(!qdict_haskey(resp, "event")); + g_assert(!qdict_haskey(resp, "error")); + qobject_unref(resp); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/pcie-root-port/slot4", test_slot4); + + ret =3D g_test_run(); + + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 31287a9173..19cab1bc35 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -54,6 +54,7 @@ qtests_i386 =3D \ (config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : [= ]) + \ (config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) += \ (config_all_devices.has_key('CONFIG_LPC_ICH9') ? ['lpc-ich9-test'] : [])= + \ + (config_all_devices.has_key('CONFIG_PCIE_PORT') ? ['pcie-root-port-test'= ] : []) + \ (config_all_devices.has_key('CONFIG_USB_UHCI') ? ['usb-hcd-uhci-test'] := []) + \ (config_all_devices.has_key('CONFIG_USB_UHCI') and = \ config_all_devices.has_key('CONFIG_USB_EHCI') ? ['usb-hcd-ehci-test'] := []) + \ @@ -63,6 +64,7 @@ qtests_i386 =3D \ (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-test'] : [= ]) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_ISA') ? ['tpm-tis-swtpm-test= '] : []) + \ (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : [= ]) + \ + (config_all_devices.has_key('CONFIG_XIO3130') ? ['xio3130-test'] : []) += \ (config_all_devices.has_key('CONFIG_E1000E_PCI_EXPRESS') ? ['fuzz-e1000e= -test'] : []) + \ (config_all_devices.has_key('CONFIG_MEGASAS_SCSI_PCI') ? ['fuzz-megasas-= test'] : []) + \ (config_all_devices.has_key('CONFIG_LSI_SCSI_PCI') ? ['fuzz-lsi53c895a-t= est'] : []) + \ --=20 2.36.1