From nobody Thu Dec 18 22:17:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154408; cv=none; d=zohomail.com; s=zohoarc; b=e0gLVcBHKtUzs+OgjlJCS8+gOOdQQHiOaP9iDsObdnsi0EccCEmqYqLpWlRdd11BMBHixQcUTUDL4KPfuwxJUyfP6xjI0VDEcb936pwNLOns1xQSuA6FO2Gb4S+oRg/SJ0slzH8ExNiRNGfVWLph6Tn6hO8HtSj0/2X6MVp3n6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154408; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qz69hyjKtHbhmrlIIKDKTwJRVIu5vyxEpPp07fk0Aeo=; b=GdehEGOmYvg5aHaQuJ47lv3BnCQ9mWVgEMrnExc8xv6+ze7yV4qBpN6NfI8Jpt723XNtKd/NOUKC5jM/LsRZhEtS1zVCSAZ2KtMYryLva51zfySFB089izJcRNmSZKlOBIZtbkjSjb8+smhld0IBA7Ma5ZajpmumwG8edZdq79o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154408541759.2235890303006; Mon, 18 Jul 2022 07:26:48 -0700 (PDT) Received: from localhost ([::1]:35732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRhv-0003s1-IE for importer@patchew.org; Mon, 18 Jul 2022 10:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHb-00027e-Sr for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:45859) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHX-0003Ar-EQ for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:34 -0400 Received: by mail-wm1-x331.google.com with SMTP id az2-20020a05600c600200b003a301c985fcso7149135wmb.4 for ; Mon, 18 Jul 2022 06:59:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qz69hyjKtHbhmrlIIKDKTwJRVIu5vyxEpPp07fk0Aeo=; b=r87jyJe4Pwn90SUTszwh466HY4Kw52FlKh/k1MoVBR7TtZQgNMBJ4fhmX9gdEA1aBW cL7I7IS0Lbza3fTsNl72aQX9gk95Y0qV/Ih0nouOAH0sBwVRiwAR4sn/yQpMbH8e5N0c r6E3zMn7f7EehjETS0R8EpuIVKC3n4PHN4vh8/eUVtqdsZBYvbNdO6Y8rGVUbMUKLoPX HOsW+Wuni6W46vXrIvbftDRSn7PR37HXX9I3dZRcdMcJK70ZW1ybZQ2AW8C/tvb87KPN fFJKFy+eXOUsPq4bFhpU7f3cyfWg6wt3r84MtGXfUL9yO4GO0WhwdAIPYT6SERR4Fvzy +uuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qz69hyjKtHbhmrlIIKDKTwJRVIu5vyxEpPp07fk0Aeo=; b=77gxa5FQi8ZiuqEiSAmokGmDd0ySN2w88l4WamNo/bXS7SftXbxvq3KGA13LQ/FEoN rb8m8+w+01tNIWme5RlKVVws/0zTBJDjIsahMLv6HZwQMF+y3bqhN2MtcQNv66pYVWr0 6LlEw2XJagJ/TjiIWu7r74+dAXqDNgc7U0PUKjSTqAk7DjhiiVIWNWeFFoYqbtl5KjQE HKErjeXyrqQPZa2fQcyPHxYstJ7krGRA9LwYYd5xmoImzkzgqsLprNzPYQLN082cEbKX aITaBsprecL8aMyPT01sfWXATuTyE4aoUqcXjqhaJTLw5qH+Oa/PNQthXx00coovbejg AxLg== X-Gm-Message-State: AJIora8T4WUR+lks67gjfcbgM80YeQEiqq5R+H0iitSurzfD3+wsitHH IN9cixlYDG18/glvd9J6tiCbtkVjiov/ag== X-Google-Smtp-Source: AGRyM1tj6DSp0glLHAU7grVLvU8JqXE8GHJBJWJTOVJw02v+eD10qh/3xN9yJZRPZ9G7sHAvIpWFaQ== X-Received: by 2002:a05:600c:1da8:b0:3a3:1969:b0d with SMTP id p40-20020a05600c1da800b003a319690b0dmr6090834wms.172.1658152769790; Mon, 18 Jul 2022 06:59:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/15] target/arm: Fix big-endian host handling of VTCR Date: Mon, 18 Jul 2022 14:59:13 +0100 Message-Id: <20220718135920.13667-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154408905100001 Content-Type: text/plain; charset="utf-8" We have a bug in our handling of accesses to the AArch32 VTCR register on big-endian hosts: we were not adjusting the part of the uint64_t field within TCR that the generated code would access. That can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg struct, or by defining a full set of read/write/reset functions -- the various other TCR cpreg structs used one or another of those strategies, but for VTCR we did not, so on a big-endian host VTCR accesses would touch the wrong half of the register. Use offsetoflow32() in the VTCR register struct. This works even though the field in the CPU struct is currently a struct TCR, because the first field in that struct is the uint64_t raw_tcr. None of the other TCR registers have this bug -- either they are AArch64 only, or else they define resetfn, writefn, etc, and expect to be passed the full struct pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-5-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8847f5b90ad..7461d4091ef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5409,7 +5409,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .type =3D ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vtcr_el2) }, { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, --=20 2.25.1