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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value()
together
Date: Mon, 18 Jul 2022 14:59:12 +0100
Message-Id: <20220718135920.13667-8-peter.maydell@linaro.org>
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The only caller of regime_tcr() is now regime_tcr_value(); fold the
two together, and use the shorter and more natural 'regime_tcr'
name for the new function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220714132303.1287193-4-peter.maydell@linaro.org
---
target/arm/internals.h | 16 +++++-----------
target/arm/helper.c | 6 +++---
target/arm/ptw.c | 6 +++---
target/arm/tlb_helper.c | 2 +-
4 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index fa046124fa8..0a1eb20afce 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -777,26 +777,20 @@ static inline uint64_t regime_sctlr(CPUARMState *env,=
ARMMMUIdx mmu_idx)
return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
}
=20
-/* Return the TCR controlling this translation regime */
-static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
+/* Return the value of the TCR controlling this translation regime */
+static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
- return &env->cp15.vtcr_el2;
+ return env->cp15.vtcr_el2.raw_tcr;
}
if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) {
/*
* Note: Secure stage 2 nominally shares fields from VTCR_EL2, but
* those are not currently used by QEMU, so just return VSTCR_EL2.
*/
- return &env->cp15.vstcr_el2;
+ return env->cp15.vstcr_el2.raw_tcr;
}
- return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
-}
-
-/* Return the raw value of the TCR controlling this translation regime */
-static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_id=
x)
-{
- return regime_tcr(env, mmu_idx)->raw_tcr;
+ return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr;
}
=20
/**
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c245922bb5d..8847f5b90ad 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env)
static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
uint64_t addr)
{
- uint64_t tcr =3D regime_tcr_value(env, mmu_idx);
+ uint64_t tcr =3D regime_tcr(env, mmu_idx);
int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx);
int select =3D extract64(addr, 55, 1);
=20
@@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARM=
MMUIdx mmu_idx)
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
ARMMMUIdx mmu_idx, bool data)
{
- uint64_t tcr =3D regime_tcr_value(env, mmu_idx);
+ uint64_t tcr =3D regime_tcr(env, mmu_idx);
bool epd, hpd, using16k, using64k, tsz_oob, ds;
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
ARMCPU *cpu =3D env_archcpu(env);
@@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState=
*env, int el, int fp_el,
{
CPUARMTBFlags flags =3D {};
ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx);
- uint64_t tcr =3D regime_tcr_value(env, mmu_idx);
+ uint64_t tcr =3D regime_tcr(env, mmu_idx);
uint64_t sctlr;
int tbii, tbid;
=20
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 16226d14233..e9959848d88 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -315,7 +315,7 @@ static bool get_level1_table_address(CPUARMState *env, =
ARMMMUIdx mmu_idx,
uint32_t *table, uint32_t address)
{
/* Note that we can only get here for an AArch32 PL0/PL1 lookup */
- uint64_t tcr =3D regime_tcr_value(env, mmu_idx);
+ uint64_t tcr =3D regime_tcr(env, mmu_idx);
int maskshift =3D extract32(tcr, 0, 3);
uint32_t mask =3D ~(((uint32_t)0xffffffffu) >> maskshift);
uint32_t base_mask;
@@ -824,7 +824,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_i=
dx, bool is_aa64,
static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
ARMMMUIdx mmu_idx)
{
- uint64_t tcr =3D regime_tcr_value(env, mmu_idx);
+ uint64_t tcr =3D regime_tcr(env, mmu_idx);
uint32_t el =3D regime_el(env, mmu_idx);
int select, tsz;
bool epd, hpd;
@@ -998,7 +998,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64=
_t address,
uint32_t attrs;
int32_t stride;
int addrsize, inputsize, outputsize;
- uint64_t tcr =3D regime_tcr_value(env, mmu_idx);
+ uint64_t tcr =3D regime_tcr(env, mmu_idx);
int ap, ns, xn, pxn;
uint32_t el =3D regime_el(env, mmu_idx);
uint64_t descaddrmask;
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index a2f87a5042d..5a709eab56f 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx=
mmu_idx)
return true;
}
if (arm_feature(env, ARM_FEATURE_LPAE)
- && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) {
+ && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
return true;
}
return false;
--=20
2.25.1