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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g31dAkBLolR3SL5v/DI1MbBtClQOVCoYrNY5ZlsV5yY=; b=iEaFOklepheezgTq/Wn03rk43ss/ChlyQrKpyMfd/xG9ucchYp/X4KpohG2C+blG5o v6760B7NILWYxU4V1Iyq6EdIgm0dxVp+lkpzMXc2PxeVxU+M8XWYH8ncojoBAjWJR61P 2l+6n3KZLdWHtQId5YsHgGuiDfHNUTwcdL6KOS7k+6rB3f2DBXDO97WNk/bouKiE/h3m HG44qGFX6pDpPGeNoJAUU6M6qmD09e90ESIwfgCYtH5O8pxOdqdi+7ypHa6CkK9rjDbM /YVBqI3WK05k6hCegpZ9TSLMOSPVqqCxvInOeLy5aRr9YnM/1CnMfJu/ij9Cz94icipI gRsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g31dAkBLolR3SL5v/DI1MbBtClQOVCoYrNY5ZlsV5yY=; b=69o1T/hocZij1Eryu4XTq6K377cKTHF9ZGxeTcPOkdKbHZbE8nudrr1ZmlIL8+hHQJ OlgMwu6gMNTtgRMDWpyKxfihx6mzVg5b0Ban95jTupu9CerEqZz0GG9Va7TmDGUAaLtU ngLZNzmziZiU6uMvdL7HU8HOa6UuFqyubcvUBy+rrn2t9BjMosH77gE6i8WbBv2OD6vt aCSQAXtQkHBHX+8q8FpurkPSLK2zcfSiOBXlWAokCD590Vj+8v/kBtsO99k9N4eZo1E7 YYtATcRaORCqlT5GSD2I2uSxL3h8OgcmmoWlTkK1ZeBsVhQruhNxXh52YmNJjNrml8xp Th8g== X-Gm-Message-State: AJIora890WRpr7e2UXJs50nKf5+AXLJbh58ts/1REgsFnkmch2c8+Clo CbudL0qhTKZN9xJWaqbrNYaB7aLIWoEFJw== X-Google-Smtp-Source: AGRyM1smSYx8T2sm1V2xl2ekjeYxhqIWOepxHRTq0jbtHyKCm3GfgXgREkHjXiQpjdEWi9dtMgtpog== X-Received: by 2002:a05:600c:a4c:b0:39c:34d0:fd25 with SMTP id c12-20020a05600c0a4c00b0039c34d0fd25mr27126466wmq.172.1658152771376; Mon, 18 Jul 2022 06:59:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t Date: Mon, 18 Jul 2022 14:59:15 +0100 Message-Id: <20220718135920.13667-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154412962100001 Content-Type: text/plain; charset="utf-8" Change the representation of the TCR_EL* registers in the CPU state struct from struct TCR to uint64_t. This allows us to drop the custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0" checks to their more usual location in the writefn vmsa_ttbcr_write(). We also don't need the resetfn any more. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-7-peter.maydell@linaro.org --- target/arm/cpu.h | 8 +---- target/arm/internals.h | 6 ++-- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 75 +++++++++++---------------------------- target/arm/ptw.c | 2 +- 6 files changed, 27 insertions(+), 68 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b14c7c3eec3..b43083c5ef5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -166,12 +166,6 @@ typedef struct ARMGenericTimer { #define GTIMER_HYPVIRT 4 #define NUM_GTIMERS 5 =20 -typedef struct { - uint64_t raw_tcr; - uint32_t mask; - uint32_t base_mask; -} TCR; - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -339,7 +333,7 @@ typedef struct CPUArchState { uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ - TCR tcr_el[4]; + uint64_t tcr_el[4]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 9f654b12cea..742135ef146 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -252,9 +252,9 @@ unsigned int arm_pamax(ARMCPU *cpu); */ static inline bool extended_addresses_enabled(CPUARMState *env) { - TCR *tcr =3D &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; + uint64_t tcr =3D env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; return arm_el_is_aa64(env, 1) || - (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); + (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); } =20 /* Update a QEMU watchpoint based on the information the guest has set in = the @@ -790,7 +790,7 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARM= MMUIdx mmu_idx) */ return env->cp15.vstcr_el2; } - return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } =20 /** diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5de7e097e9b..1b7b3d76bb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -226,7 +226,7 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr =3D 5 | (1ULL << 37); + env->cp15.tcr_el[1] =3D 5 | (1ULL << 37); =20 /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index d09fccb0a4f..c21739242c5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -439,7 +439,7 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) using_lpae =3D true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { using_lpae =3D true; } } diff --git a/target/arm/helper.c b/target/arm/helper.c index ea541e4b0c9..1a8b06410e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3606,19 +3606,21 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, }; =20 -static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - TCR *tcr =3D raw_ptr(env, ri); - int maskshift =3D extract32(value, 0, 3); + ARMCPU *cpu =3D env_archcpu(env); =20 if (!arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ + /* + * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-descriptor translation table format + */ value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* In an implementation that includes the Security Extensions + /* + * In an implementation that includes the Security Extensions * TTBCR has additional fields PD0 [4] and PD1 [5] for * Short-descriptor translation table format. */ @@ -3628,55 +3630,23 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, = const ARMCPRegInfo *ri, } } =20 - /* Update the masks corresponding to the TCR bank being written - * Note that we always calculate mask and base_mask, but - * they are only used for short-descriptor tables (ie if EAE is 0); - * for long-descriptor tables the TCR fields are used differently - * and the mask and base_mask values are meaningless. - */ - tcr->raw_tcr =3D value; - tcr->mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); - tcr->base_mask =3D ~((uint32_t)0x3fffu >> maskshift); -} - -static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); - if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); } - /* Preserve the high half of TCR_EL1, set via TTBCR2. */ - value =3D deposit64(tcr->raw_tcr, 0, 32, value); - vmsa_ttbcr_raw_write(env, ri, value); -} - -static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - TCR *tcr =3D raw_ptr(env, ri); - - /* Reset both the TCR as well as the masks corresponding to the bank of - * the TCR being reset. - */ - tcr->raw_tcr =3D 0; - tcr->mask =3D 0; - tcr->base_mask =3D 0xffffc000u; + raw_write(env, ri, value); } =20 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); =20 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; + raw_write(env, ri, value); } =20 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3780,15 +3750,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .writefn =3D vmsa_tcr_el12_write, - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, + .raw_writefn =3D raw_write, + .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_write, - .raw_writefn =3D vmsa_ttbcr_raw_write, - /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.tcr_el[3]), - offsetof(CPUARMState, cp15.tcr_el[1])} }, + .raw_writefn =3D raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), + offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, }; =20 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3799,8 +3769,8 @@ static const ARMCPRegInfo ttbcr2_reginfo =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_ALIAS, .bank_fieldoffsets =3D { - offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), - offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), + offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]), }, }; =20 @@ -5403,7 +5373,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, - /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -5643,12 +5612,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL3_RW, - /* no .writefn needed as this can't cause an ASID change; - * we must provide a .raw_writefn and .resetfn because we handle - * reset and migration for the AArch32 TTBCR(S), which might be - * using mask and base_mask. - */ - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D vmsa_ttbcr_raw_write, + /* no .writefn needed as this can't cause an ASID change */ + .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8049c67f039..3261039d93a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2466,7 +2466,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, int r_el =3D regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr; + uint64_t tcr =3D env->cp15.tcr_el[r_el]; int addrtop, tbi; =20 tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); --=20 2.25.1