From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658153091; cv=none; d=zohomail.com; s=zohoarc; b=dhwjBZZmywq/siKElcQBGeUWXDF5eEXQhjFXjlLAjN2oM4lxR8saQ9sH+menOWPqc0wV42LK7It1vlPh3qfBvlyMRK3fcsxbaqI+CL4/S4stWV1KUbdM6Phcm/I6tP5olBv25QjPHoKaDMzRU2NesEemT4NBTKaL+yOa4JRK88g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658153091; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4XCUImSLdHKkyI8geHYTH1ofyLU9VSFDcDRAFOqUvzE=; b=GS7eyTz8MFHxGCU0CBBztpwAJ0+C6kuZhiuIdH3DSrz4jFAyJEgQtXWVuJiKxmjEjVdrPOEXbrotKPkkx2YGJCyU9czZE8AxNtfphopxYECW2rkQwRr+MY6HYKEpVxcFc0dFXJdtS1whWrgJGO/k7Ho3+Hshv2qPzYlhOcZJ9mU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658153091661937.2837423339902; Mon, 18 Jul 2022 07:04:51 -0700 (PDT) Received: from localhost ([::1]:37598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRMg-00080q-Ln for importer@patchew.org; Mon, 18 Jul 2022 10:04:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHU-00023v-84 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:29 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:41967) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHS-00039t-KY for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:27 -0400 Received: by mail-wr1-x433.google.com with SMTP id n12so4335839wrc.8 for ; Mon, 18 Jul 2022 06:59:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4XCUImSLdHKkyI8geHYTH1ofyLU9VSFDcDRAFOqUvzE=; b=Uz0iQXzehnlIPq2NrFZu/wrxZjSvY5RsdfpS8Q1d7P1memboTsMpQgQG5DtlBOX0qa 9gb5kqfRW2mfzxoC/T3tiHmLrYpHqLtLVhcYBBf1jAGTr1gLT6iPOyvqA9L1xHE7cRNT 0VydP1nwY0901ouUYNUXwGsNz4PI0vVrJBSWWxq/28ED1pMC/5Lyvgm7Kkw09fUd0gu2 G4bNqgUiKKcyrwizjz/hY769F5CmtQOoURkUaB9A8Q7/3dVgZnuRzhMq9XQsXN+012OI UGZ1D/ecpBeHfgco+renZH2+0YzaGBNEUFiYlZ3Y0Xhf8tmUqdmwA07qiXCPUgY2157C 6+JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4XCUImSLdHKkyI8geHYTH1ofyLU9VSFDcDRAFOqUvzE=; b=IM4OmWpYuZNQ34m/JH2CddKDh+kF39vfsKZQ5v3Zy3IaxgugYLq85ABqTBhdpjsfEH 6tdRKZNMSO5w5QUJIIDLI2hC1Ns0sCDa5HyTig1DNgVujOupyiUAYHy38I8vuPAHzoJv GdLQxkCwQb6eJEYstI8MGusyIuzlPiwUXYSEoiMc6XMLgqgcameM7YE5hqvYSnJRf3uk eatAwcFyV8Bu4GGMfKp/82xgT1B4rxiQ9bUGNPl+QYsxtEjv6A4Nah3CSOeLhaF7wy+G IFAMqUmiV6Lh+0pJPE6evUhrcdbmUFUtNrFrKlk3GkdYThPHFHx9AkxZRVPpnGOgzYXM gAyA== X-Gm-Message-State: AJIora9VOJ6CmGRG/46Ve5NVYBhZOv7BtgxgbQ5ZGnQPQARs9VbDNeG0 8gtqwcUYWro1BLqpy0Z6MHEwD1tmZMxIjA== X-Google-Smtp-Source: AGRyM1vNtlARFa0LmGUN9Yb5OJxa3G/yGPpeMK9SpyLovU3LioSTojOwhYRiWqstj1AS7zyMI92TkA== X-Received: by 2002:a05:6000:1e04:b0:21d:7ec3:fe5a with SMTP id bj4-20020a0560001e0400b0021d7ec3fe5amr23319088wrb.116.1658152764826; Mon, 18 Jul 2022 06:59:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high Date: Mon, 18 Jul 2022 14:59:06 +0100 Message-Id: <20220718135920.13667-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658153093268100001 In the M-profile Arm ARM, rule R_CVJS defines when an interrupt should be set to the Pending state: A) when the input line is high and the interrupt is not Active B) when the input line transitions from low to high and the interrupt is Active (Note that the first of these is an ongoing condition, and the second is a point-in-time event.) This can be rephrased as: 1 when the line goes from low to high, set Pending 2 when Active goes from 1 to 0, if line is high then set Pending 3 ignore attempts to clear Pending when the line is high and Active is 0 where 1 covers both B and one of the "transition into condition A" cases, 2 deals with the other "transition into condition A" possibility, and 3 is "don't drop Pending if we're already in condition A". Transitions out of condition A don't affect Pending state. We handle case 1 in set_irq_level(). For an interrupt (as opposed to other kinds of exception) the only place where we clear Active is in armv7m_nvic_complete_irq(), where we handle case 2 by checking for whether we need to re-pend the exception. For case 3, the only places where we clear Pending state on an interrupt are in armv7m_nvic_acknowledge_irq() (where we are setting Active so it doesn't count) and for writes to NVIC_ICPRn. It is the "write to NVIC_ICPRn" case that we missed: we must ignore this if the input line is high and the interrupt is not Active. (This required behaviour is differently and perhaps more clearly stated in the v7M Arm ARM, which has pseudocode in section B3.4.1 that implies it.) Reported-by: Igor Kotrasi=C5=84ski Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20220628154724.3297442-1-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 13df002ce4d..1f7763964c3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2389,8 +2389,15 @@ static MemTxResult nvic_sysreg_write(void *opaque, h= waddr addr, startvec =3D 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ =20 for (i =3D 0, end =3D size * 8; i < end && startvec + i < s->num_i= rq; i++) { + /* + * Note that if the input line is still held high and the inte= rrupt + * is not active then rule R_CVJS requires that the Pending st= ate + * remains set; in that case we mustn't let it be cleared. + */ if (value & (1 << i) && - (attrs.secure || s->itns[startvec + i])) { + (attrs.secure || s->itns[startvec + i]) && + !(setval =3D=3D 0 && s->vectors[startvec + i].level && + !s->vectors[startvec + i].active)) { s->vectors[startvec + i].pending =3D setval; } } --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658153290; cv=none; d=zohomail.com; s=zohoarc; b=i4kvgxZb0FJUO3CNZJE/A3DRQymGanrH+viz+kRQvRWt54DpW4V+JJkyyN+SYEVuAjaeLljrUTYU58cQ85dqb1VxZ2G7IHXXsp0En1DVkCIDE1zEF8nho6CA19mtAZeK+e+9OsODNll4J7GJmBPFgmKWwCcEN9uGwuaJzlvZx5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658153290; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NsboqJpMKAMO89QQrdUhOCnjGLwfFQBesnrYOdMQBAo=; b=hBlds+Jm85QdnraRf5kleWfsULyk3HHhczqF2/EXxdSGw98YX6xn4fK8s8jxcdhX6kkw+j4jws6HerUs+HnI7Z5OsBP6MIMykMMmD9l1QXPrgR71tt+U2DAVxJxBZ3XQIvHb8ovGHpIw64AGmHanAJclByfikD88Xr604Pivv6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658153290559351.3604526243412; Mon, 18 Jul 2022 07:08:10 -0700 (PDT) Received: from localhost ([::1]:45874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRPs-0005Gz-Lc for importer@patchew.org; Mon, 18 Jul 2022 10:08:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHW-00026V-9y for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:33 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:36464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHT-00039y-Jz for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:29 -0400 Received: by mail-wr1-x42f.google.com with SMTP id r2so16171812wrs.3 for ; Mon, 18 Jul 2022 06:59:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NsboqJpMKAMO89QQrdUhOCnjGLwfFQBesnrYOdMQBAo=; b=HkEFlE6Txn+bMsrHiVPvLYMTaS5QJUZBXQaX+YjkAH7MHLrqgwejvKkEFdp3xnFzu5 Ch+BgFRgz+ZZZyKLrdanlagQGFgcdRPzQ/I0nzbd3TiFccvr79RcoBIejA5+QN8ChvI/ SP2IL1dTu77fgDcGqVFCjbk9GATZEtlUN0Gn/UJcF+W1UASFz1rlRFCgcNoO6n8BeQdb 9ShR59Q2RJ2dPms/6wWZkGZPv+qFGSoK8HITQPbphxgKGbJ/zKZywvbyrZzygWK5qMEv 1WOlmtIeFQlRDGC8DVvaTPtadRUz9jeJhWKgSAfNv6X3sJ9WsA/vo+9cDZVm+JD1f3v/ n5ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NsboqJpMKAMO89QQrdUhOCnjGLwfFQBesnrYOdMQBAo=; b=FWpMULss9WDYdEah0t/NF0i5IL74fAMWEQ7GCdAD6llZG4ltGFkqpBq4zCQtppPaUw Q07teAwcHiXG7aZX7egmsXPKgPon64oDDoTAFydvGuesOPqwOoCA9B6BvEIiMr9hFjEf GH0/mQPEbgfQW5dlvzoV/4aeMtLXijN81yYI+fWCyvt1nmxO1S7Vp6xMYfxwIBhOQz65 cPOqc2kSOqvNsJeYGs/7qaQ0uOXgB2Aw2Rml7j5vDUcSvVtO2DJa4D888enjaKBuXjuP YFkHuN+EECc22jO+Z0l+E8cmvwGIY7wmoOeGgaJ98y4tAv/pA89ltGiHSG6kpf+FQif8 7c5Q== X-Gm-Message-State: AJIora/GaXkq+QyO0c/ngRKtKznIL2ZjN7bfaBQMq2bgxCE3h48LkBBm PJaqITHUNVlQiggNcfHpyVwgvxeBmaSEBg== X-Google-Smtp-Source: AGRyM1vTu36vovbzmQA0BACv6ePrAS++xBM0sjDk6zZ8+/0l0W+mgtLD16VdwhPCl0cl/Yt5YxLa5Q== X-Received: by 2002:a5d:4e0f:0:b0:21d:8ca4:2563 with SMTP id p15-20020a5d4e0f000000b0021d8ca42563mr22872447wrt.272.1658152765531; Mon, 18 Jul 2022 06:59:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled Date: Mon, 18 Jul 2022 14:59:07 +0100 Message-Id: <20220718135920.13667-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658153292453100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson When PSTATE.SM, VL =3D SVL even if SVE is disabled. This is visible in kselftest ssve-test. Reported-by: Mark Brown Signed-off-by: Richard Henderson Message-id: 20220713045848.217364-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cfcad97ce07..6fff7fc64fd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10882,13 +10882,19 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMSta= te *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { int sme_el =3D sme_exception_el(env, el); + bool sm =3D FIELD_EX64(env->svcr, SVCR, SM); =20 DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); if (sme_el =3D=3D 0) { /* Similarly, do not compute SVL if SME is disabled. */ - DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + int svl =3D sve_vqm1_for_el_sm(env, el, true); + DP_TBFLAG_A64(flags, SVL, svl); + if (sm) { + /* If SVE is disabled, we will not have set VL above. */ + DP_TBFLAG_A64(flags, VL, svl); + } } - if (FIELD_EX64(env->svcr, SVCR, SM)) { + if (sm) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)= ); } --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154214; cv=none; d=zohomail.com; s=zohoarc; b=MVDoVA/Vzgx3sDrIYYlmRw02g4EMIMpRcQcrl+Bv9yO8JQ53QzS1CElzsDfaA4Ncxhcjg8IY/VXVbN5anOhVtDxaOT/EVaQuTkAZJxpsRGkWKEcasLLvJKDCaULGQCLalceWyj3zVxBeVPphpXmHITs61ObdlXxhB1Jw6SHFzGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154214; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jUzTz5s5zsxreDDQya4YCpzbBiN04ee02WSt0TzEGbo=; b=GK8fm2pm3rDUegiyqCrUnswRtsKFs2h1cZfQHMXb+DRPIHyOVwHQjW/tTbCRBTxI2LG+Fr/ahfGdbUSNT8TUDb9hDMpGYqBarja2aK8SP6QAKlpc7BGLNhefBD+Msr+bCan79FwsIGaUufNWenkT1gqT8qQD5FDkjBRXhn0lkCA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154214569143.62444625615876; Mon, 18 Jul 2022 07:23:34 -0700 (PDT) Received: from localhost ([::1]:55950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRel-0006go-JO for importer@patchew.org; Mon, 18 Jul 2022 10:23:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHW-00026W-AF for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:33 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42786) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHT-0003A4-K4 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:29 -0400 Received: by mail-wr1-x432.google.com with SMTP id bu1so17166499wrb.9 for ; Mon, 18 Jul 2022 06:59:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jUzTz5s5zsxreDDQya4YCpzbBiN04ee02WSt0TzEGbo=; b=eaOPIy9/HReAEhFwDTbs+kBLOGSrlLv3Q1A+LuwuTfCxmfWtdmjG3xh7F0MMaFt8k5 ZmDXv265ipb0z9lLjm3nIp7veqrRM7bDrkF4FGj3PZjLD7I9IWpQa/t96MXRnojxcICT W2S6hUqIK50jeg4aC8DDj5VBx/aqSPg23A4wkGZ7dbClrZPZl6IYcXme7ZlyL278FjEK Skxs/dwpbpP8/RaShOKbftrK6gfh2PjuB0dC/6pnGcgkMrqpHdPKaozoBjVaMTRfRXL4 r9GLyKXHoValPdxdBdhIlNISTW5AeyEVaJNgkShOJbwyfoz1T8eM096BD5Vvi7811AZj PNjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jUzTz5s5zsxreDDQya4YCpzbBiN04ee02WSt0TzEGbo=; b=yPKhEurJqzwQFb4VcrelpRy84B/86o2qwGDjfDhtkOjaxA2FsHeAB6Ku65yEpSh+5g 4lJJ8RXbGwtP3Phq48iw73elxFcf9oD8gK5clahItE8N9Za5v1EJ24PzPEBFOfe/D2VY OZGsAYpDlbcmY9I87v2K+Ov9llP11+t1x0Mzkr86EAhlbSUIMpdZucM1zSrp7Wmki+XH GRTnWhGAs/KvOhj2Q8lMkOloEA7QU7M/TKwUgUkDgmalq5fP1a3kHVCpe2zxSIc3uZau AiDKRXuIRst7243QOVxbDMuwYo16SkkwAcASQXbWEk4L5cO0n8uSjCoUu5VlpmIxgK/k P3aA== X-Gm-Message-State: AJIora+JuFFY+W1wHO48k7nKatuYrcBsWrFw2svvZglpY8oCprJGwPMp GXpF4Y6zvuXMPbAJ+MmLBiAx6D1ZuUwXpw== X-Google-Smtp-Source: AGRyM1uEJubVUbx139wvBt3Mm91v+XC6YkJTNRFQOeUjQvek7NfvlaElBr8dHroi1yUeLOLG6duMNA== X-Received: by 2002:a5d:5586:0:b0:21e:294d:6003 with SMTP id i6-20020a5d5586000000b0021e294d6003mr1177366wrv.595.1658152766212; Mon, 18 Jul 2022 06:59:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME Date: Mon, 18 Jul 2022 14:59:08 +0100 Message-Id: <20220718135920.13667-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154215960100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We were only checking for SVE disabled and not taking into account PSTATE.SM to check SME disabled, which resulted in vectors being incorrectly truncated. Signed-off-by: Richard Henderson Message-id: 20220713045848.217364-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6fff7fc64fd..24c45a9bf31 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11228,6 +11228,21 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsig= ned vq) } } =20 +static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) +{ + int exc_el; + + if (sm) { + exc_el =3D sme_exception_el(env, el); + } else { + exc_el =3D sve_exception_el(env, el); + } + if (exc_el) { + return 0; /* disabled */ + } + return sve_vqm1_for_el_sm(env, el, sm); +} + /* * Notice a change in SVE vector size when changing EL. */ @@ -11236,7 +11251,7 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, { ARMCPU *cpu =3D env_archcpu(env); int old_len, new_len; - bool old_a64, new_a64; + bool old_a64, new_a64, sm; =20 /* Nothing to do if no SVE. */ if (!cpu_isar_feature(aa64_sve, cpu)) { @@ -11256,7 +11271,8 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, * invoke ResetSVEState when taking an exception from, or * returning to, AArch32 state when PSTATE.SM is enabled. */ - if (old_a64 !=3D new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + sm =3D FIELD_EX64(env->svcr, SVCR, SM); + if (old_a64 !=3D new_a64 && sm) { arm_reset_sve_state(env); return; } @@ -11273,10 +11289,13 @@ void aarch64_sve_change_el(CPUARMState *env, int = old_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_vqm1_for_el(env, old_el) : 0); - new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_vqm1_for_el(env, new_el) : 0); + old_len =3D new_len =3D 0; + if (old_a64) { + old_len =3D sve_vqm1_for_el_sm_ena(env, old_el, sm); + } + if (new_a64) { + new_len =3D sve_vqm1_for_el_sm_ena(env, new_el, sm); + } =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154209; cv=none; d=zohomail.com; s=zohoarc; b=QOwHVcG69hCdoBBw3oQ7FutXeaTmBoX9xSR1B6enL8eTNkt+6TLfMsGY1Is+mDDfTIv0Hpp+YDvf3sbI1IsQZ5XRkTyhEoud9QAnafggW4v1XjUo/Ga3RI8RV0VIMWfoq05CU5zI/oQ70+v50F+c1oiLPVrn+sZHKqSY+OGeUt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154209; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oX0cz/UuX4deysfpkWLa72UX1jaFnIUFPBqr5lkXZCA=; b=IsX3P4hJZ2ZwUMEmK0APkh/F5P5NBqskyhCDoBvTbKum19yr3ZE9oHOSHGtk8ycieheC7AWy4exFYV752arobEUk5iJlbHqChlTSxGoC8oUox+zCbwqZnOKIi3FVispToS0chwNZV9q/9KLMEpdXtgHTA2ZAA5IrbzDEQimAyeU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154209770562.3369259138341; Mon, 18 Jul 2022 07:23:29 -0700 (PDT) Received: from localhost ([::1]:55654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRei-0006UG-Om for importer@patchew.org; Mon, 18 Jul 2022 10:23:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHW-00026U-A3 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:33 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:36623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHU-0003AA-Cv for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:29 -0400 Received: by mail-wm1-x333.google.com with SMTP id p26-20020a1c545a000000b003a2fb7c1274so5282746wmi.1 for ; Mon, 18 Jul 2022 06:59:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oX0cz/UuX4deysfpkWLa72UX1jaFnIUFPBqr5lkXZCA=; b=GyY+vccb5hxLsP7HyMVCGmdSxyX/tPTRKGMEBVpPwdknpykBiXvnenkFOmOlxnQTZS 8L5aWIDFJqMsYGxg8gNuk5equrCYbIxD7J3VWVh/b7tZs3HwSSCSzntageJsPIo1+OC+ w5ZMSfd1o5YRfmSA88onxXOWQZbt/AENRrwlYDw9ThAMLR8geaGc/b7aR5zs1AMo6iil V/STIlRxwGdNnIWWqZ/RikncIvLa5NqJpwgpJa89Pzpc1z8TwSxLU+w642adsWOrvZqU 2iktkl6koSkWf2iHHkVKp0WrkedPkm5Pcvleam3xw8Gs3hkXqU0FkB8tQm5hm6C5V17h W4NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oX0cz/UuX4deysfpkWLa72UX1jaFnIUFPBqr5lkXZCA=; b=nUcLBgbiNTNgg0lD7YQdP4HF84tJTLwBxASgY0NtFMEFiDV6aJRxVFT0BLmdfEz3FY MKdDj3Tibr861DqDP6hVWi7T7qMb8DHrcwPTWk4J9814s+O8GTK+jCAl82GYs8Odm+K8 BTLfrO647xEQy5F3unL1pFbn2CPpw+DhdxU/3Wb+nLCfQSXq1fsPYSj6f62T5eoceNqW FWECzYdBZzEEA+0sJnnKrSG5T4jfcqApaEBB2iT+NITPUq54IDL85XQqwRCdGLf6l5TJ Tfjo18pkH8pIezeSfbU1U+68snoDi+YoCS9IU1wwct/BLZfW04cHS4x4gen6VJy72XEC j+mA== X-Gm-Message-State: AJIora9Nga0YCXVivc3sNgqUt9o/BPNQxojXqxwDy0uXJ1n/dB5mujSH 8QIDOwUJjBjmCs30ckqFP9G98C+t6NHLCw== X-Google-Smtp-Source: AGRyM1uHDpuq1hkU7d/TLvjrxqh1ubNEQeUNilB+l7ydZ44uFMiLmFltvHvc1Oa1G8FR5JROoXPXDw== X-Received: by 2002:a05:600c:3b29:b0:3a3:1fa6:768 with SMTP id m41-20020a05600c3b2900b003a31fa60768mr2004296wms.193.1658152766918; Mon, 18 Jul 2022 06:59:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect Date: Mon, 18 Jul 2022 14:59:09 +0100 Message-Id: <20220718135920.13667-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154212074100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The documentation for PROT_MTE says that it cannot be cleared by mprotect. Further, the implementation of the VM_ARCH_CLEAR bit, contains PROT_BTI confiming that bit should be cleared. Introduce PAGE_TARGET_STICKY to allow target/arch/cpu.h to control which bits may be reset during page_set_flags. This is sort of the opposite of VM_ARCH_CLEAR, but works better with qemu's PAGE_* bits that are separate from PROT_* bits. Reported-by: Vitaly Buka Signed-off-by: Richard Henderson Message-id: 20220711031420.17820-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++-- accel/tcg/translate-all.c | 13 +++++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e36a839ee4..6afcc882f2c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3392,9 +3392,12 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTx= Attrs *x) =20 /* * AArch64 usage of the PAGE_TARGET_* bits for linux-user. + * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect + * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. */ -#define PAGE_BTI PAGE_TARGET_1 -#define PAGE_MTE PAGE_TARGET_2 +#define PAGE_BTI PAGE_TARGET_1 +#define PAGE_MTE PAGE_TARGET_2 +#define PAGE_TARGET_STICKY PAGE_MTE =20 #ifdef TARGET_TAGGED_ADDRESSES /** diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8fd23a9d05f..ef62a199c7d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2256,6 +2256,15 @@ int page_get_flags(target_ulong address) return p->flags; } =20 +/* + * Allow the target to decide if PAGE_TARGET_[12] may be reset. + * By default, they are not kept. + */ +#ifndef PAGE_TARGET_STICKY +#define PAGE_TARGET_STICKY 0 +#endif +#define PAGE_STICKY (PAGE_ANON | PAGE_TARGET_STICKY) + /* Modify the flags of a page and invalidate the code if necessary. The flag PAGE_WRITE_ORG is positioned automatically depending on PAGE_WRITE. The mmap_lock should already be held. */ @@ -2299,8 +2308,8 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) p->target_data =3D NULL; p->flags =3D flags; } else { - /* Using mprotect on a page does not change MAP_ANON. */ - p->flags =3D (p->flags & PAGE_ANON) | flags; + /* Using mprotect on a page does not change sticky bits. */ + p->flags =3D (p->flags & PAGE_STICKY) | flags; } } } --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658153505; cv=none; d=zohomail.com; s=zohoarc; b=GO+IUZH0wsK/dFLAQWnz/N9thwpqYoftSp9UQs/s5R2QsXsUDN74mTDs/pYhG69ZgT77IraWQL+9SYS5uZtME9I2dZbjZCduVKfTT6VXYg6IOMshOJebNLBgMzfI4gP0s9pE/j6b622jpz7+QJeUbBptVhGKO/QlrJFrCQMmrLc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658153505; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WkWJRj26wPeTo9qIJ3RW2bntJqHKbO7FETgRMM6GtVw=; b=C1FUYxADwz14b44fSEyilrssqOfA9kDzgxYPtuqqGC+ACs57GcrP2MvSOrO3ZHuli+93Bdb6cP+8Bw5CCK2o/IkHj+G1fm8wHVb8SE5mScxK+BaWPymD+I1Hw3vPxk8SoMcO+gAcA6ZRZ09De4FC//CTO0Pxgh4BWdSIDIoy2Fo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658153505910932.671395032344; Mon, 18 Jul 2022 07:11:45 -0700 (PDT) Received: from localhost ([::1]:54284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRTM-0002i4-Pk for importer@patchew.org; Mon, 18 Jul 2022 10:11:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHZ-000278-Vr for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:35 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:33498) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHW-0003AM-2C for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:32 -0400 Received: by mail-wr1-x429.google.com with SMTP id h17so17240268wrx.0 for ; Mon, 18 Jul 2022 06:59:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WkWJRj26wPeTo9qIJ3RW2bntJqHKbO7FETgRMM6GtVw=; b=rrgHgSfhHZ8me/+lLXDe91BUPvEL+IDcZmMOj0LH2aFeVlI3E7RDLYlmsLBj7+4sEI qBoTSGnofzKvH3PSoGNx2EBmSDOmOuBvkUafhjB/zteVvXqz0p2ZUAPa6vigOz3No6na 3uZja5RgfhM4JqSTRpcA+2iXZWvngvk4mXQtasZGcFhfXartQS+c/sGJK1vN/dNtfP4o Jm6JxYyF88SLVIhreJm3Rq3kN07YreENkbBmv6XBL/ABfG91XyFFVGoP/fDZW1eeX/jp B107PJ8x6NNCdZ8vA1JpYRF6MlFInk0ese8k4E53lcEv5yS3vsx2DgwJ1kLvM0BbSscd K2UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WkWJRj26wPeTo9qIJ3RW2bntJqHKbO7FETgRMM6GtVw=; b=kQBNkHX4bVmUzWbxrgcmBWF8UEZ4lzVNyKmWrCOtJGhYFZe9JfIRHRkFKrITWLx7+/ HhLpET8AnAL1dVmkMr328i9q6rhiVYs8SrE1BlT9aIGxobZYXOuZa/9lbl5E7H9MrboK O+lyA3mht62yL5H0nNHRBzbOBzC03SNWh01FAccEWcZlWsCYYJ52Do7Igo5u4vxuRcB2 XkG4bSprnvgeuklvV5/VucDYbqusFoDHRVRI/ZpDwWEcvhOI1gCRvBmJ2Ckw5/n7pCjn DsC8EKmU+cKbVV7Qv1W+8grB01HNPLIzFDCZf6q7YZX+Cy9F29EFSX/TSkbXm7+idDrt lUeQ== X-Gm-Message-State: AJIora8lg90LTleu+k2VwGYp284Ith8p0DM3I+YDgx29+JU3qByi8LwC DynGNmRnwRm8oYR/HwMgNRgHuX+9T55OZA== X-Google-Smtp-Source: AGRyM1sMgo3rNH51Z12JoAQwbjyrOO5JReJC2I+Rf28TWihXsRVSGrQDFJLznrbw+nAP46Dvi7Bjfw== X-Received: by 2002:a05:6000:90c:b0:21e:1565:8179 with SMTP id bz12-20020a056000090c00b0021e15658179mr4579680wrb.717.1658152767707; Mon, 18 Jul 2022 06:59:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/15] target/arm: Define and use new regime_tcr_value() function Date: Mon, 18 Jul 2022 14:59:10 +0100 Message-Id: <20220718135920.13667-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658153507848100001 Content-Type: text/plain; charset="utf-8" The regime_tcr() function returns a pointer to a struct TCR corresponding to the TCR controlling a translation regime. The struct TCR has the raw value of the register, plus two fields mask and base_mask which are used as a small optimization in the case of 32-bit short-descriptor lookups. Almost all callers of regime_tcr() only want the raw register value. Define and use a new regime_tcr_value() function which returns only the raw 64-bit register value. This is a preliminary to removing the 32-bit short descriptor optimization -- it only saves a handful of bit operations, which is tiny compared to the overhead of doing a page table walk at all, and the TCR struct is awkward and makes fixing https://gitlab.com/qemu-project/qemu/-/issues/1103 unnecessarily difficult. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-2-peter.maydell@linaro.org --- target/arm/internals.h | 6 ++++++ target/arm/helper.c | 6 +++--- target/arm/ptw.c | 8 ++++---- target/arm/tlb_helper.c | 2 +- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 00e2e710f6c..fa046124fa8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -793,6 +793,12 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMU= Idx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } =20 +/* Return the raw value of the TCR controlling this translation regime */ +static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_id= x) +{ + return regime_tcr(env, mmu_idx)->raw_tcr; +} + /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/helper.c b/target/arm/helper.c index 24c45a9bf31..c245922bb5d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env) static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) { - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr =3D regime_tcr_value(env, mmu_idx); int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); int select =3D extract64(addr, 55, 1); =20 @@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARM= MMUIdx mmu_idx) ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr =3D regime_tcr_value(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu =3D env_archcpu(env); @@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, { CPUARMTBFlags flags =3D {}; ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr =3D regime_tcr_value(env, mmu_idx); uint64_t sctlr; int tbii, tbid; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e71fc1f4293..0d7e8ffa41b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -820,7 +820,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_i= dx, bool is_aa64, static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint64_t tcr =3D regime_tcr_value(env, mmu_idx); uint32_t el =3D regime_el(env, mmu_idx); int select, tsz; bool epd, hpd; @@ -994,7 +994,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64= _t address, uint32_t attrs; int32_t stride; int addrsize, inputsize, outputsize; - TCR *tcr =3D regime_tcr(env, mmu_idx); + uint64_t tcr =3D regime_tcr_value(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; @@ -1112,8 +1112,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * For stage 2 translations the starting level is specified by the * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) */ - uint32_t sl0 =3D extract32(tcr->raw_tcr, 6, 2); - uint32_t sl2 =3D extract64(tcr->raw_tcr, 33, 1); + uint32_t sl0 =3D extract32(tcr, 6, 2); + uint32_t sl2 =3D extract64(tcr, 33, 1); uint32_t startlevel; bool ok; =20 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7d8a86b3c45..a2f87a5042d 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx= mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) { return true; } return false; --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154760; cv=none; d=zohomail.com; s=zohoarc; b=hb+QgDEsEwDhpNTKFFCjodtS7Ab2VAMJm36Tl/ZOsIIejyTC2itSsRWfHej25XNNrHZ9dYePhUdu1cm3bWJhwPBFiwKd1B61ekfE6LG5ozePp9YwRni2spz0c89Pr8Kbo+sB/vWwc6LILidR3NdtYYL9MEyVbTCQNSfb/9atQS8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154760; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xMitL12ZlGpIhoJpUfgkcxUiDFlIMjfw25ZQQiFUOWg=; b=O7hwgqV3C3iiSE/nQSKSqubkEt2fleEMulujydUvWcnpC9rS6+tXkHYAyVUxRUeItTeRnXTRaEGezhGNAKnlUPZ7LvrismSOHLwLsK3ZSQwtTBnaKKlyaAmqg9S4ezWqG1+Hi8bX9wygi8/3JJDh2SfhF5TpXjS16DHBS8ofLFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165815476059464.45273004274304; Mon, 18 Jul 2022 07:32:40 -0700 (PDT) Received: from localhost ([::1]:51060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRna-000641-7S for importer@patchew.org; Mon, 18 Jul 2022 10:32:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHb-00027g-TL for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:43535) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHW-0003AV-2I for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:34 -0400 Received: by mail-wm1-x334.google.com with SMTP id j29-20020a05600c1c1d00b003a2fdafdefbso7397796wms.2 for ; Mon, 18 Jul 2022 06:59:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xMitL12ZlGpIhoJpUfgkcxUiDFlIMjfw25ZQQiFUOWg=; b=xWSUP0WISETDYST6Q8ZHYGhYUmF4hsbrNNWwQ5ndmeULWOKWINiv6JeLpmGZjpRrm7 nlAtvNMkslhryVzMh7Gn6fPJNUKrm3Sm3ZJjLzBGTjUbqunENdGK7Y3jpotiC90MtJNZ nZel2ENtxfnq2FX5NhHOIHvUuCFIVCBbcr/lyIgWu1GiTi69Gi60aZI3MsoemIWYUAa7 92wLJUAErb9mVi5JoYjFrp8aWqu14aNo5OBhJnd2nfmXmLzfkpJUEwpu2dfzq26LFbih fjGFE/hxkM1Oq9cEGupbf3aJ3etlnT4D6Fq1DJfMzebvAOAyCvulZbdpe30osK7yYQm9 FxrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xMitL12ZlGpIhoJpUfgkcxUiDFlIMjfw25ZQQiFUOWg=; b=YGEl2eThsHgw9sKroicOH0Dg6u3qiVbt5QnnHsn8XYgvXna8eRaakeAbRLQKlFBgZl lceCA64GeZ4rfnwP5qbcPZUWqy23tR2qpcVnwv7DofxiGGvWpK7c+gYjTk9+uNt00Wsh fPKsMOvJdBuIqY4YSH19rbRP7kAxZcHpgiyb1VlzTC6QusYJNQy4MMky31H6cd2PQXR4 F5ulhLV+2fqjEbnr7nQFjb2Fw0GXkvax3D3vYVGn7b7sM5xAbku8WHgUZAUxb9U37RwX lQHMrbGqzFhRZYYqijCH4UVG5Gkti39b+gjwuOh3oh/KqgvzmG3DEHgrXrxYisiu2ez0 57qw== X-Gm-Message-State: AJIora/c+3yZ7P4sVJ3AbG6kLH+4uZxf2ZFN4ogG4xBAGZBHva/8zFKD ltAH3hAbvG0iAkBkqPMo2YGJuhDnj7SK4Q== X-Google-Smtp-Source: AGRyM1uGDiBrDHD5B7fwP1qXgmcv7wL7SVLpBI5waHunayzaXOP5MVYBlHFlsCNqrHh29ARjY/Y/PQ== X-Received: by 2002:a05:600c:3b1d:b0:3a3:1fda:efcf with SMTP id m29-20020a05600c3b1d00b003a31fdaefcfmr1811505wms.49.1658152768376; Mon, 18 Jul 2022 06:59:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address() Date: Mon, 18 Jul 2022 14:59:11 +0100 Message-Id: <20220718135920.13667-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154761812100003 Content-Type: text/plain; charset="utf-8" In get_level1_table_address(), instead of using precalculated values of mask and base_mask from the TCR struct, calculate them directly (in the same way we currently do in vmsa_ttbcr_raw_write() to populate the TCR struct fields). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-3-peter.maydell@linaro.org --- target/arm/ptw.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0d7e8ffa41b..16226d14233 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,20 +315,24 @@ static bool get_level1_table_address(CPUARMState *env= , ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - TCR *tcr =3D regime_tcr(env, mmu_idx); + uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + int maskshift =3D extract32(tcr, 0, 3); + uint32_t mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); + uint32_t base_mask; =20 - if (address & tcr->mask) { - if (tcr->raw_tcr & TTBCR_PD1) { + if (address & mask) { + if (tcr & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; } *table =3D regime_ttbr(env, mmu_idx, 1) & 0xffffc000; } else { - if (tcr->raw_tcr & TTBCR_PD0) { + if (tcr & TTBCR_PD0) { /* Translation table walk disabled for TTBR0 */ return false; } - *table =3D regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; + base_mask =3D ~((uint32_t)0x3fffu >> maskshift); + *table =3D regime_ttbr(env, mmu_idx, 0) & base_mask; } *table |=3D (address >> 18) & 0x3ffc; return true; --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154581; cv=none; d=zohomail.com; s=zohoarc; b=lCz7EH4uYjBx6EwL+bi3q5oMLLzG9UPe/Cg5jGJdONTeTrqIVm+8paPcL8M6lajIzatALQEFxxqxzVtdI61im6s0REA0iW+yr+p/2EbbKuSNyrJQeKAvjLYIQhNzsYexEAba8igVkUlqzBiy/+v5GKTcCmOpoXFK0perQ2+/4Tk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154581; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ocRTy264UImfHohmga9Mhs3jVom81Fw75OT8Y228IS4=; b=bK6I9YiF5nnPdEzry+b2owY12bfYGtrd2veR0t7evk3vNS8ejozV0XxETKM5xZWh6m48uZfusuh1mZiqFPUPhFFDSnpHmRUCn5lU4/+gZiAFWcZbzpNarsyu0DrUuiLctEeJyCSWtcAvkIibJpXR/SIhW/+JJpN0XH40zB3sMCU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154581895953.5492569731606; Mon, 18 Jul 2022 07:29:41 -0700 (PDT) Received: from localhost ([::1]:43880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRki-0001E3-Sf for importer@patchew.org; Mon, 18 Jul 2022 10:29:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHb-00027h-Ta for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:55997) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHX-0003Ac-EI for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:34 -0400 Received: by mail-wm1-x335.google.com with SMTP id b6so6659574wmq.5 for ; Mon, 18 Jul 2022 06:59:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ocRTy264UImfHohmga9Mhs3jVom81Fw75OT8Y228IS4=; b=zYdB1K1D8Mgxy1mZjmn/7C+MGLXOeGr5OxavMRBG7Aikr5TA7nSb7x4J9fV7LxFnmw Q5y4DXO+ie0uIZnONtTaMi4o5VXEq96Incb2aHpJe/NJ39voXx1xwfN27ewQF9G3XhXb yeI6vb0r0KrOaRFTROt5/J+TP6/rilqjQV0Mg1cYaRm0t35+LyK5G82Ny75cjOuiu0yX o4Dl6ZTxvd2dormwaR7r/MzSHNRBthLtxrX1Df3H+6rLvBkDQp25XkJJOlfFVGdO2c9g EvOK4YQ9fQzn528GEvlLoUE24g5D4Y3nQiOkFp+c9ZRlXakc2//IqkIt8dIFJQ+qTfoZ LuaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ocRTy264UImfHohmga9Mhs3jVom81Fw75OT8Y228IS4=; b=lxViFgCF56a9iCLXvinabkaspf9VAbh6eNhAUvRA4AZ7tVWiY0n5HJ7dt6P+T6l/GZ 6k7NPFjKqaP+WUInAEOdSc5P4AH4btlFVK64cT2nIrGa0Lz358sll1JGfjvsUWuvcfn4 GT9n5XiPv4UBifQd23r7/9KdPdcY7mxG4jG/9Ho30bVXL5z7wFjvq3KYCJQupBrx0HK5 3DtdyRWoHgLirfyvOyPvwwMUYbaVNzcs+BJbKpKO+mYm15ACSj5PIvSFMMxv+SkZJ50Y 7kccoqY5x4hLbjDrbc9dQcjo9IAPoxhgTwXe8pb1YRWrGpWa/ZevvopVyFHhxW7Q7uN9 lcaQ== X-Gm-Message-State: AJIora9ohlXVAAJR0pmSR1V4NfiJ/oHUQ04TP5S0oiLyZkvZFSzbq6ZX V57lkaMdCTgcnsKmJHNinxt15+dak4uSJA== X-Google-Smtp-Source: AGRyM1vXbiYvOXl2e6bp+Eibh1wldJAef25R2MXyga+FmUv640+4sK4UDImjGBAY0l7yeAVmCs73WQ== X-Received: by 2002:a05:600c:5128:b0:3a3:2160:7a7b with SMTP id o40-20020a05600c512800b003a321607a7bmr4045wms.204.1658152769127; Mon, 18 Jul 2022 06:59:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value() together Date: Mon, 18 Jul 2022 14:59:12 +0100 Message-Id: <20220718135920.13667-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154582993100001 Content-Type: text/plain; charset="utf-8" The only caller of regime_tcr() is now regime_tcr_value(); fold the two together, and use the shorter and more natural 'regime_tcr' name for the new function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-4-peter.maydell@linaro.org --- target/arm/internals.h | 16 +++++----------- target/arm/helper.c | 6 +++--- target/arm/ptw.c | 6 +++--- target/arm/tlb_helper.c | 2 +- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fa046124fa8..0a1eb20afce 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -777,26 +777,20 @@ static inline uint64_t regime_sctlr(CPUARMState *env,= ARMMMUIdx mmu_idx) return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } =20 -/* Return the TCR controlling this translation regime */ -static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) +/* Return the value of the TCR controlling this translation regime */ +static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - return &env->cp15.vtcr_el2; + return env->cp15.vtcr_el2.raw_tcr; } if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { /* * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but * those are not currently used by QEMU, so just return VSTCR_EL2. */ - return &env->cp15.vstcr_el2; + return env->cp15.vstcr_el2.raw_tcr; } - return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; -} - -/* Return the raw value of the TCR controlling this translation regime */ -static inline uint64_t regime_tcr_value(CPUARMState *env, ARMMMUIdx mmu_id= x) -{ - return regime_tcr(env, mmu_idx)->raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; } =20 /** diff --git a/target/arm/helper.c b/target/arm/helper.c index c245922bb5d..8847f5b90ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4216,7 +4216,7 @@ static int vae1_tlbmask(CPUARMState *env) static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) { - uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); int select =3D extract64(addr, 55, 1); =20 @@ -10158,7 +10158,7 @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARM= MMUIdx mmu_idx) ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data) { - uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); bool epd, hpd, using16k, using64k, tsz_oob, ds; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu =3D env_archcpu(env); @@ -10849,7 +10849,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, { CPUARMTBFlags flags =3D {}; ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); uint64_t sctlr; int tbii, tbid; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 16226d14233..e9959848d88 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -315,7 +315,7 @@ static bool get_level1_table_address(CPUARMState *env, = ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); int maskshift =3D extract32(tcr, 0, 3); uint32_t mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); uint32_t base_mask; @@ -824,7 +824,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_i= dx, bool is_aa64, static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { - uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); uint32_t el =3D regime_el(env, mmu_idx); int select, tsz; bool epd, hpd; @@ -998,7 +998,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64= _t address, uint32_t attrs; int32_t stride; int addrsize, inputsize, outputsize; - uint64_t tcr =3D regime_tcr_value(env, mmu_idx); + uint64_t tcr =3D regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index a2f87a5042d..5a709eab56f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,7 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx= mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr_value(env, mmu_idx) & TTBCR_EAE)) { + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { return true; } return false; --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154408; cv=none; d=zohomail.com; s=zohoarc; b=e0gLVcBHKtUzs+OgjlJCS8+gOOdQQHiOaP9iDsObdnsi0EccCEmqYqLpWlRdd11BMBHixQcUTUDL4KPfuwxJUyfP6xjI0VDEcb936pwNLOns1xQSuA6FO2Gb4S+oRg/SJ0slzH8ExNiRNGfVWLph6Tn6hO8HtSj0/2X6MVp3n6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154408; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qz69hyjKtHbhmrlIIKDKTwJRVIu5vyxEpPp07fk0Aeo=; b=GdehEGOmYvg5aHaQuJ47lv3BnCQ9mWVgEMrnExc8xv6+ze7yV4qBpN6NfI8Jpt723XNtKd/NOUKC5jM/LsRZhEtS1zVCSAZ2KtMYryLva51zfySFB089izJcRNmSZKlOBIZtbkjSjb8+smhld0IBA7Ma5ZajpmumwG8edZdq79o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154408541759.2235890303006; Mon, 18 Jul 2022 07:26:48 -0700 (PDT) Received: from localhost ([::1]:35732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRhv-0003s1-IE for importer@patchew.org; Mon, 18 Jul 2022 10:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHb-00027e-Sr for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:45859) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHX-0003Ar-EQ for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:34 -0400 Received: by mail-wm1-x331.google.com with SMTP id az2-20020a05600c600200b003a301c985fcso7149135wmb.4 for ; Mon, 18 Jul 2022 06:59:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qz69hyjKtHbhmrlIIKDKTwJRVIu5vyxEpPp07fk0Aeo=; b=r87jyJe4Pwn90SUTszwh466HY4Kw52FlKh/k1MoVBR7TtZQgNMBJ4fhmX9gdEA1aBW cL7I7IS0Lbza3fTsNl72aQX9gk95Y0qV/Ih0nouOAH0sBwVRiwAR4sn/yQpMbH8e5N0c r6E3zMn7f7EehjETS0R8EpuIVKC3n4PHN4vh8/eUVtqdsZBYvbNdO6Y8rGVUbMUKLoPX HOsW+Wuni6W46vXrIvbftDRSn7PR37HXX9I3dZRcdMcJK70ZW1ybZQ2AW8C/tvb87KPN fFJKFy+eXOUsPq4bFhpU7f3cyfWg6wt3r84MtGXfUL9yO4GO0WhwdAIPYT6SERR4Fvzy +uuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qz69hyjKtHbhmrlIIKDKTwJRVIu5vyxEpPp07fk0Aeo=; b=77gxa5FQi8ZiuqEiSAmokGmDd0ySN2w88l4WamNo/bXS7SftXbxvq3KGA13LQ/FEoN rb8m8+w+01tNIWme5RlKVVws/0zTBJDjIsahMLv6HZwQMF+y3bqhN2MtcQNv66pYVWr0 6LlEw2XJagJ/TjiIWu7r74+dAXqDNgc7U0PUKjSTqAk7DjhiiVIWNWeFFoYqbtl5KjQE HKErjeXyrqQPZa2fQcyPHxYstJ7krGRA9LwYYd5xmoImzkzgqsLprNzPYQLN082cEbKX aITaBsprecL8aMyPT01sfWXATuTyE4aoUqcXjqhaJTLw5qH+Oa/PNQthXx00coovbejg AxLg== X-Gm-Message-State: AJIora8T4WUR+lks67gjfcbgM80YeQEiqq5R+H0iitSurzfD3+wsitHH IN9cixlYDG18/glvd9J6tiCbtkVjiov/ag== X-Google-Smtp-Source: AGRyM1tj6DSp0glLHAU7grVLvU8JqXE8GHJBJWJTOVJw02v+eD10qh/3xN9yJZRPZ9G7sHAvIpWFaQ== X-Received: by 2002:a05:600c:1da8:b0:3a3:1969:b0d with SMTP id p40-20020a05600c1da800b003a319690b0dmr6090834wms.172.1658152769790; Mon, 18 Jul 2022 06:59:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/15] target/arm: Fix big-endian host handling of VTCR Date: Mon, 18 Jul 2022 14:59:13 +0100 Message-Id: <20220718135920.13667-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154408905100001 Content-Type: text/plain; charset="utf-8" We have a bug in our handling of accesses to the AArch32 VTCR register on big-endian hosts: we were not adjusting the part of the uint64_t field within TCR that the generated code would access. That can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg struct, or by defining a full set of read/write/reset functions -- the various other TCR cpreg structs used one or another of those strategies, but for VTCR we did not, so on a big-endian host VTCR accesses would touch the wrong half of the register. Use offsetoflow32() in the VTCR register struct. This works even though the field in the CPU struct is currently a struct TCR, because the first field in that struct is the uint64_t raw_tcr. None of the other TCR registers have this bug -- either they are AArch64 only, or else they define resetfn, writefn, etc, and expect to be passed the full struct pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-5-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8847f5b90ad..7461d4091ef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5409,7 +5409,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .type =3D ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vtcr_el2) }, { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154401; cv=none; d=zohomail.com; s=zohoarc; b=YpxLCgXWamnWBNy7pSriPZJm2ciMllOvCNDIhUK3vGRiI2WU0H2xeHn2uB8MWsvr2rvKXgdlVKC1+x71wJKxjOghQknY9S0umBP6hjByau4zPGYnhJHkAU6pQrZBUiOJii4YYzosMDoSKAS1SZTefF4zcR2yG6QAs0KLPenQ1PI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154401; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S9521uPJSfVMIBW00AoA0V1zvlCEYyKqf8sTNG4dyxo=; b=FFAc/CqbCnH7cgYYL5DsM9lQD3LhpTuuw2gn450Iu9y1YnsLUKLkHzhNKI6VX9srodDO3Q6vWNkHOd+0z+7uwO7M0SE3Px3EFZRfbiBLv8ynWAOIvfJ/qW/NoVmP1RP84VqaJIf+hpkE2Jj/O4kbKR1V+iyi4oLUjHtX9xd9p4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154401631710.7012197117407; Mon, 18 Jul 2022 07:26:41 -0700 (PDT) Received: from localhost ([::1]:35564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRho-0003lH-Lb for importer@patchew.org; Mon, 18 Jul 2022 10:26:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHb-00027f-TD for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:44865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHX-0003Az-Q2 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:34 -0400 Received: by mail-wm1-x335.google.com with SMTP id be14-20020a05600c1e8e00b003a04a458c54so7392316wmb.3 for ; Mon, 18 Jul 2022 06:59:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=S9521uPJSfVMIBW00AoA0V1zvlCEYyKqf8sTNG4dyxo=; b=gwkSvpR/Q6z50AyG23b3Pgu8+dim+7d9cVEgIE2SAaqv7FPuPxRFE9cNHYUgplMmCH cM2kIcYYiv6zquSS+Zbw5w9QU/5Y9HnC1TsNU3EpV4OuJXwcXGJgg7WiKoPIvEnxz/5r 5FfjZxqiB35eUQTcF1qwqSTzyQ90XeK1DrPq8y9bB6N4nQhDqrufg3RytdkM+RKWRiHP BGviX/dgPiJI+ZKzpDkQc53Uvl3pBXHFY+CYjQuDIKGz6d+AXvM5gbERU5EKtGba10u7 fgjOL2waz3EBMSljrHRn7icyiXAhA2LLN0mPt7Djks+IicpjH3UtdnsSBsopkC/7tbVH SIUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S9521uPJSfVMIBW00AoA0V1zvlCEYyKqf8sTNG4dyxo=; b=H36iXD2urbU4sTkcB6IlsyaO4P6qtpsY8lioQ5f+dRfFN9ggBNNf8M3K2RjhsDMxpj Y2B50CXbZpEM/u9uC4Mkuy4CWe9q7GaoMJi9C5u1JZwiPM5v5frYRCW81iM/gKOQfHiP DebYsFdwhUCylXnFIlUQdZWfry4dQxtzhME6RifIZGnuMm0gFg/WRl5Q8LyqJNxLFuh0 lH+6/S6Z4Uwiqz4BboYytgBSDNTWBiLC6l2CAVF1yloHMO38Qh8P4veMIaVqVuC9U6rI F7Xska9Tgj/O5jz8WXBIJuTdMLcUWNsyvEgfXXOvPOiZuzOUShdm6p+TNPYUTRUGd0T7 Yu0A== X-Gm-Message-State: AJIora/v6AXg/lkDyutQLIwk/LaEiHsW2hQ/Av+m6qIDBPnPFSYZACK5 mKOhFX47rvr1FcAEnark+V79ETE7Mye4ow== X-Google-Smtp-Source: AGRyM1sUj/2fA+dFvIeA/9EX3TkHuTYxk3rFT9R2/62looozmWNFoY3WDAJPsHre+OGxuhIVpfQ65A== X-Received: by 2002:a05:600c:48a:b0:3a2:ce31:a150 with SMTP id d10-20020a05600c048a00b003a2ce31a150mr25951645wme.48.1658152770572; Mon, 18 Jul 2022 06:59:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t Date: Mon, 18 Jul 2022 14:59:14 +0100 Message-Id: <20220718135920.13667-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154402923100001 Content-Type: text/plain; charset="utf-8" Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in the CPU state struct from struct TCR to uint64_t. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-6-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 4 ++-- target/arm/helper.c | 4 +--- target/arm/ptw.c | 14 +++++++------- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6afcc882f2c..b14c7c3eec3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -340,8 +340,8 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ TCR tcr_el[4]; - TCR vtcr_el2; /* Virtualization Translation Control. */ - TCR vstcr_el2; /* Secure Virtualization Translation Control. */ + uint64_t vtcr_el2; /* Virtualization Translation Control. */ + uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register diff --git a/target/arm/internals.h b/target/arm/internals.h index 0a1eb20afce..9f654b12cea 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -781,14 +781,14 @@ static inline uint64_t regime_sctlr(CPUARMState *env,= ARMMMUIdx mmu_idx) static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - return env->cp15.vtcr_el2.raw_tcr; + return env->cp15.vtcr_el2; } if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { /* * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but * those are not currently used by QEMU, so just return VSTCR_EL2. */ - return env->cp15.vstcr_el2.raw_tcr; + return env->cp15.vstcr_el2; } return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 7461d4091ef..ea541e4b0c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5413,9 +5413,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ + /* no .writefn needed as this can't cause an ASID change */ .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 6, .crm =3D 2, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e9959848d88..8049c67f039 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -241,9 +241,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, if (arm_is_secure_below_el3(env)) { /* Check if page table walk is to secure or non-secure PA spac= e. */ if (*is_secure) { - *is_secure =3D !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + *is_secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - *is_secure =3D !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + *is_secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); } } else { assert(!*is_secure); @@ -2341,9 +2341,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, ipa_secure =3D attrs->secure; if (arm_is_secure_below_el3(env)) { if (ipa_secure) { - attrs->secure =3D !(env->cp15.vstcr_el2.raw_tcr & VSTC= R_SW); + attrs->secure =3D !(env->cp15.vstcr_el2 & VSTCR_SW); } else { - attrs->secure =3D !(env->cp15.vtcr_el2.raw_tcr & VTCR_= NSW); + attrs->secure =3D !(env->cp15.vtcr_el2 & VTCR_NSW); } } else { assert(!ipa_secure); @@ -2385,11 +2385,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, if (arm_is_secure_below_el3(env)) { if (ipa_secure) { attrs->secure =3D - !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_= SW)); + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)); } else { attrs->secure =3D - !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_N= SW)) - || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTC= R_SW))); + !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))); } } return 0; --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154411; cv=none; d=zohomail.com; s=zohoarc; b=mythxVwXtTPPz2onOfBkmV4Dw94rPjQGhn9+fbDl4ODKg3Cv13WLsxiYVrC90//TrkH+3TVkmPo+ER/5MBMdLnZFwUFAxcZw1C7stQFrValMZi47Ska1IIp19qz8ZNKu7vqQ86hFNwhZumnXkvRdTmhdmO1uDjPEuVZ/Z9lxV24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154411; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g31dAkBLolR3SL5v/DI1MbBtClQOVCoYrNY5ZlsV5yY=; b=DqSUfm08k30WFyPBnWpJEZm8CogY0lN71sVzEsAe0JoxzdUGD01hou9v7ZeCItjm5ApvGOXypWvjX3uQC2NuBqr72CZEMwGvZXPEIHY5Kjaa6HtJ2+6feZzrtoF2JOCP8UWWiqYkIybRvEgOQEqaBgD4/KHdG3CI5A6wf5k9VPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154411179735.4711113963427; Mon, 18 Jul 2022 07:26:51 -0700 (PDT) Received: from localhost ([::1]:35902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRhx-0003zn-TL for importer@patchew.org; Mon, 18 Jul 2022 10:26:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHe-00029P-1z for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:38 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:53812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHZ-0003B4-Nl for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: by mail-wm1-x332.google.com with SMTP id a11so1061815wmq.3 for ; Mon, 18 Jul 2022 06:59:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g31dAkBLolR3SL5v/DI1MbBtClQOVCoYrNY5ZlsV5yY=; b=iEaFOklepheezgTq/Wn03rk43ss/ChlyQrKpyMfd/xG9ucchYp/X4KpohG2C+blG5o v6760B7NILWYxU4V1Iyq6EdIgm0dxVp+lkpzMXc2PxeVxU+M8XWYH8ncojoBAjWJR61P 2l+6n3KZLdWHtQId5YsHgGuiDfHNUTwcdL6KOS7k+6rB3f2DBXDO97WNk/bouKiE/h3m HG44qGFX6pDpPGeNoJAUU6M6qmD09e90ESIwfgCYtH5O8pxOdqdi+7ypHa6CkK9rjDbM /YVBqI3WK05k6hCegpZ9TSLMOSPVqqCxvInOeLy5aRr9YnM/1CnMfJu/ij9Cz94icipI gRsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g31dAkBLolR3SL5v/DI1MbBtClQOVCoYrNY5ZlsV5yY=; b=69o1T/hocZij1Eryu4XTq6K377cKTHF9ZGxeTcPOkdKbHZbE8nudrr1ZmlIL8+hHQJ OlgMwu6gMNTtgRMDWpyKxfihx6mzVg5b0Ban95jTupu9CerEqZz0GG9Va7TmDGUAaLtU ngLZNzmziZiU6uMvdL7HU8HOa6UuFqyubcvUBy+rrn2t9BjMosH77gE6i8WbBv2OD6vt aCSQAXtQkHBHX+8q8FpurkPSLK2zcfSiOBXlWAokCD590Vj+8v/kBtsO99k9N4eZo1E7 YYtATcRaORCqlT5GSD2I2uSxL3h8OgcmmoWlTkK1ZeBsVhQruhNxXh52YmNJjNrml8xp Th8g== X-Gm-Message-State: AJIora890WRpr7e2UXJs50nKf5+AXLJbh58ts/1REgsFnkmch2c8+Clo CbudL0qhTKZN9xJWaqbrNYaB7aLIWoEFJw== X-Google-Smtp-Source: AGRyM1smSYx8T2sm1V2xl2ekjeYxhqIWOepxHRTq0jbtHyKCm3GfgXgREkHjXiQpjdEWi9dtMgtpog== X-Received: by 2002:a05:600c:a4c:b0:39c:34d0:fd25 with SMTP id c12-20020a05600c0a4c00b0039c34d0fd25mr27126466wmq.172.1658152771376; Mon, 18 Jul 2022 06:59:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t Date: Mon, 18 Jul 2022 14:59:15 +0100 Message-Id: <20220718135920.13667-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154412962100001 Content-Type: text/plain; charset="utf-8" Change the representation of the TCR_EL* registers in the CPU state struct from struct TCR to uint64_t. This allows us to drop the custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0" checks to their more usual location in the writefn vmsa_ttbcr_write(). We also don't need the resetfn any more. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-7-peter.maydell@linaro.org --- target/arm/cpu.h | 8 +---- target/arm/internals.h | 6 ++-- target/arm/cpu.c | 2 +- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 75 +++++++++++---------------------------- target/arm/ptw.c | 2 +- 6 files changed, 27 insertions(+), 68 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b14c7c3eec3..b43083c5ef5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -166,12 +166,6 @@ typedef struct ARMGenericTimer { #define GTIMER_HYPVIRT 4 #define NUM_GTIMERS 5 =20 -typedef struct { - uint64_t raw_tcr; - uint32_t mask; - uint32_t base_mask; -} TCR; - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW @@ -339,7 +333,7 @@ typedef struct CPUArchState { uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ - TCR tcr_el[4]; + uint64_t tcr_el[4]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 9f654b12cea..742135ef146 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -252,9 +252,9 @@ unsigned int arm_pamax(ARMCPU *cpu); */ static inline bool extended_addresses_enabled(CPUARMState *env) { - TCR *tcr =3D &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; + uint64_t tcr =3D env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; return arm_el_is_aa64(env, 1) || - (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); + (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); } =20 /* Update a QEMU watchpoint based on the information the guest has set in = the @@ -790,7 +790,7 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARM= MMUIdx mmu_idx) */ return env->cp15.vstcr_el2; } - return env->cp15.tcr_el[regime_el(env, mmu_idx)].raw_tcr; + return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } =20 /** diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5de7e097e9b..1b7b3d76bb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -226,7 +226,7 @@ static void arm_cpu_reset(DeviceState *dev) * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr =3D 5 | (1ULL << 37); + env->cp15.tcr_el[1] =3D 5 | (1ULL << 37); =20 /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index d09fccb0a4f..c21739242c5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -439,7 +439,7 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) using_lpae =3D true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { using_lpae =3D true; } } diff --git a/target/arm/helper.c b/target/arm/helper.c index ea541e4b0c9..1a8b06410e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3606,19 +3606,21 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, }; =20 -static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - TCR *tcr =3D raw_ptr(env, ri); - int maskshift =3D extract32(value, 0, 3); + ARMCPU *cpu =3D env_archcpu(env); =20 if (!arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ + /* + * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-descriptor translation table format + */ value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* In an implementation that includes the Security Extensions + /* + * In an implementation that includes the Security Extensions * TTBCR has additional fields PD0 [4] and PD1 [5] for * Short-descriptor translation table format. */ @@ -3628,55 +3630,23 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, = const ARMCPRegInfo *ri, } } =20 - /* Update the masks corresponding to the TCR bank being written - * Note that we always calculate mask and base_mask, but - * they are only used for short-descriptor tables (ie if EAE is 0); - * for long-descriptor tables the TCR fields are used differently - * and the mask and base_mask values are meaningless. - */ - tcr->raw_tcr =3D value; - tcr->mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); - tcr->base_mask =3D ~((uint32_t)0x3fffu >> maskshift); -} - -static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); - if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); } - /* Preserve the high half of TCR_EL1, set via TTBCR2. */ - value =3D deposit64(tcr->raw_tcr, 0, 32, value); - vmsa_ttbcr_raw_write(env, ri, value); -} - -static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - TCR *tcr =3D raw_ptr(env, ri); - - /* Reset both the TCR as well as the masks corresponding to the bank of - * the TCR being reset. - */ - tcr->raw_tcr =3D 0; - tcr->mask =3D 0; - tcr->base_mask =3D 0xffffc000u; + raw_write(env, ri, value); } =20 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); =20 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; + raw_write(env, ri, value); } =20 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3780,15 +3750,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .writefn =3D vmsa_tcr_el12_write, - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, + .raw_writefn =3D raw_write, + .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_write, - .raw_writefn =3D vmsa_ttbcr_raw_write, - /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.tcr_el[3]), - offsetof(CPUARMState, cp15.tcr_el[1])} }, + .raw_writefn =3D raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), + offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, }; =20 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3799,8 +3769,8 @@ static const ARMCPRegInfo ttbcr2_reginfo =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_ALIAS, .bank_fieldoffsets =3D { - offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), - offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), + offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]), }, }; =20 @@ -5403,7 +5373,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, - /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -5643,12 +5612,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL3_RW, - /* no .writefn needed as this can't cause an ASID change; - * we must provide a .raw_writefn and .resetfn because we handle - * reset and migration for the AArch32 TTBCR(S), which might be - * using mask and base_mask. - */ - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D vmsa_ttbcr_raw_write, + /* no .writefn needed as this can't cause an ASID change */ + .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8049c67f039..3261039d93a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2466,7 +2466,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, int r_el =3D regime_el(env, mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr; + uint64_t tcr =3D env->cp15.tcr_el[r_el]; int addrtop, tbi; =20 tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154581; cv=none; d=zohomail.com; s=zohoarc; b=EiT9xSYOKG0sD6IIcOX/dqHuaeAmcz9CxbBWQTwBwoprLpwQ2c2wcqzLseD9wzK7HXFruTsmK1eeh0pkqrbeby7wd//tbnUeK/EbNsz9Eo4Gp7Pon7+411oDog6TFuPFdSFmNdpx+fLIYaPaUigf9gByTIzgheV4TwzP8KcTiok= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154581; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eukvC+6HlCYJEnDc50zk+LTUKV0cWVgf+mK6xiITMuE=; b=NLtfAslBWITueHffWoi/CVAEEHSntDoNU/7rA//1WQGDQNfip+utnn6pxZVxq1JOw/kyWbrA5GJduPPBucYSOOxfK9jT2UmAIgu5aUCluH0i74mjTGHlFsKlsc5EGjJm8U79JY6ko6+XpSozRgNbmV3JXPvg6Fmk4Pjf/6Nw3Ns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154581004406.39798027506856; Mon, 18 Jul 2022 07:29:41 -0700 (PDT) Received: from localhost ([::1]:44036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRkh-0001K7-Ue for importer@patchew.org; Mon, 18 Jul 2022 10:29:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHe-00029Q-43 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:38 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:52208) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHZ-0003B8-OH for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:36 -0400 Received: by mail-wm1-x329.google.com with SMTP id id17so97980wmb.1 for ; Mon, 18 Jul 2022 06:59:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eukvC+6HlCYJEnDc50zk+LTUKV0cWVgf+mK6xiITMuE=; b=X9f206kEoBpc4fjMTey1P0v2URTVdccCh80ZKxCmHcagJBKz4E9NEHUdKkTi6V2Raa 7mMaX8flonuBktLHZMsGuK7c7TRO3xQ9Ns+kpgoO91E0iwDCojQaRlqZSpoWKt43CMBm 2xPj1ij9OWilzOPf0re1Ca9ZRiyOl0tQsrFYH8qXzy0Kes17MfH9lId5+VATaeJoa7ZP 6m7uA+2kQmULmDic8JnnWv6H8WA/KWWEraHfD7G1ou78rKJlUUeuFXD/sxfZHTx6HXg5 dJJM8/tAW14DO6sOke1/UQY8Bmnvf3bdJ3BJqT065Jri14u+V7bN29JPzNgcM+LxVhbI viMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eukvC+6HlCYJEnDc50zk+LTUKV0cWVgf+mK6xiITMuE=; b=aTRTfgqFwjkycRp0+wlj1Zxm1TJKDo3c1Ej9h1GcmmeV9aNRRGgR55tOk3MOvIdxfq 8gTP5jk93Xe0srXq5GMyVmrLG6o4LoWoOGs5lLFBg1bBX4rVeyUTd0zNL8BY0shRK/hb qDwK0AmRqaY0Gej4ijRuxF4Bbkm/l+pi66fow5DWVMBHGiGMvAOgZiA6iM+67n/mjaq0 IWf8e8etfnNSQCo+eo4mXq4b9I93iN3R04oT5Or5RPZTTPJ7DwbLodLnnjVkXoZ7OJZ5 NVF7sSwKdcCD/yoOZADuNlDfC0g+/z9vTnq6dgmvWtQbYD2dnUsmLliAEg+29VMsbDGc X7WQ== X-Gm-Message-State: AJIora8uoNAwZICLYO+Y0LNtNYq3ekmLgq0nI+f69gYEB3A+rGFoc7KR pw7m1DKn1tCFfjbAxbzPdNz3UIdtouTe3A== X-Google-Smtp-Source: AGRyM1srd4gjnAsVblNA4KaVeykh6qBzOriWtI0lcQ6MtwKHl1D/NSKgQqS83vF1T39+REDmwVNpVQ== X-Received: by 2002:a05:600c:3ca2:b0:3a0:1825:2e6b with SMTP id bg34-20020a05600c3ca200b003a018252e6bmr31858625wmb.132.1658152772151; Mon, 18 Jul 2022 06:59:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2 Date: Mon, 18 Jul 2022 14:59:16 +0100 Message-Id: <20220718135920.13667-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154583001100002 Content-Type: text/plain; charset="utf-8" In regime_tcr() we return the appropriate TCR register for the translation regime. For Secure EL2, we return the VSTCR_EL2 value, but in this translation regime some fields that control behaviour are in VTCR_EL2. When this code was originally written (as the comment notes), QEMU didn't care about any of those fields, but we have since added support for features such as LPA2 which do need the values from those fields. Synthesize a TCR value by merging in the relevant VTCR_EL2 fields to the VSTCR_EL2 value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1103 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-8-peter.maydell@linaro.org --- target/arm/cpu.h | 19 +++++++++++++++++++ target/arm/internals.h | 22 +++++++++++++++++++--- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b43083c5ef5..e890ee074d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1412,6 +1412,25 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) =20 +FIELD(VTCR, T0SZ, 0, 6) +FIELD(VTCR, SL0, 6, 2) +FIELD(VTCR, IRGN0, 8, 2) +FIELD(VTCR, ORGN0, 10, 2) +FIELD(VTCR, SH0, 12, 2) +FIELD(VTCR, TG0, 14, 2) +FIELD(VTCR, PS, 16, 3) +FIELD(VTCR, VS, 19, 1) +FIELD(VTCR, HA, 21, 1) +FIELD(VTCR, HD, 22, 1) +FIELD(VTCR, HWU59, 25, 1) +FIELD(VTCR, HWU60, 26, 1) +FIELD(VTCR, HWU61, 27, 1) +FIELD(VTCR, HWU62, 28, 1) +FIELD(VTCR, NSW, 29, 1) +FIELD(VTCR, NSA, 30, 1) +FIELD(VTCR, DS, 32, 1) +FIELD(VTCR, SL2, 33, 1) + /* Bit definitions for ARMv8 SPSR (PSTATE) format. * Only these are valid when in AArch64 mode; in * AArch32 mode SPSRs are basically CPSR-format. diff --git a/target/arm/internals.h b/target/arm/internals.h index 742135ef146..b8fefdff675 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -777,6 +777,16 @@ static inline uint64_t regime_sctlr(CPUARMState *env, = ARMMMUIdx mmu_idx) return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; } =20 +/* + * These are the fields in VTCR_EL2 which affect both the Secure stage 2 + * and the Non-Secure stage 2 translation regimes (and hence which are + * not present in VSTCR_EL2). + */ +#define VTCR_SHARED_FIELD_MASK \ + (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \ + R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \ + R_VTCR_DS_MASK) + /* Return the value of the TCR controlling this translation regime */ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -785,10 +795,16 @@ static inline uint64_t regime_tcr(CPUARMState *env, A= RMMMUIdx mmu_idx) } if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { /* - * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but - * those are not currently used by QEMU, so just return VSTCR_EL2. + * Secure stage 2 shares fields from VTCR_EL2. We merge those + * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 for= mat + * value so the callers don't need to special case this. + * + * If a future architecture change defines bits in VSTCR_EL2 that + * overlap with these VTCR_EL2 fields we may need to revisit this. */ - return env->cp15.vstcr_el2; + uint64_t v =3D env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; + v |=3D env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; + return v; } return env->cp15.tcr_el[regime_el(env, mmu_idx)]; } --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154584; cv=none; d=zohomail.com; s=zohoarc; b=FcxoZBWZAWE+xw2b8/6r75zEZzrUz2Ev4l0iz3Onw1xiWh/Q5220dpxfiZIyF6N3Rl/ifJmMIfgMYKKdrSSLgfWspAb57ycCCw60KhTY9xGrOB3+LbLfJyBijeJ4v8B1lJNWxDarNo971IWnoI46xeUoLGNt2fhUdR+Vewo5Mfo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154584; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bsiTbIieXoyZzsovMov20+PKkWbaKl/whztxxrpGPA0=; b=oD3QNNRq52lpMMkq9jC+lZoOhLArYpxoywnrOmIXtASQP+Zjv1vl7nvIQlL11+tdALX9NfzJX5pwZ536Z1WVSEfHLpEo63H5XQAP7quAEnCApiL8gIFK5wRG7C22c4oFH6ouK+9IlJpqSmcBw6O3Tj+t2KoNW4S3jmXIEyTVSPA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154584283498.2516713334269; Mon, 18 Jul 2022 07:29:44 -0700 (PDT) Received: from localhost ([::1]:44210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRkl-0001RB-7r for importer@patchew.org; Mon, 18 Jul 2022 10:29:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHe-00029O-1f for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:38 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:46667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHa-0003BG-4i for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:35 -0400 Received: by mail-wm1-x333.google.com with SMTP id h14-20020a1ccc0e000000b0039eff745c53so7383709wmb.5 for ; Mon, 18 Jul 2022 06:59:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bsiTbIieXoyZzsovMov20+PKkWbaKl/whztxxrpGPA0=; b=GCEzTYqeKffBnW/GtsNltJaAMM6uleTxXJs5y6kuPq+VMCQE71MiYLhzowM7/7CLm7 FIjSbn3Dni0jIP2lWaIZsYlvTjsblvqV5oCmVw6pBqrNiM1W2sp/eEGPhjgPwyaRyHQG b0VK7NfeOuETFxHxH9CO4FS+L85pgypOgvu/OeBinQEFIEUfis0Ta8kPl2ufna7ZqL0g OTgqLBayHTXgE1dCfbFodrmvSjNlEuWULPV/HMptYp2zRMcnIRkpMxVlhGODyS8UFI82 RjxEUGjAeHkZFaQv1lNTygVnTyuxuSW1qE/laj4glAlA00V/ws6oKRZ3RZIL6zaY8zzl b+NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bsiTbIieXoyZzsovMov20+PKkWbaKl/whztxxrpGPA0=; b=OU8E9BbFNLzVFU5GOu9QjfBzzAFUA/LI5SawX4uVgQsviAxXWm23F+Uex548DLavYU 0aqRyTiGwt1FBfK9dZqcW8hSegsCirG4WPXhiA5gZPG3Wh9kGn8cTqXGYZp83sxmNM8t tcWlJChX2WtppmMOhtu4M3n6drUdnnp2SK/gvYX3R7Tvf4V6VIJ8oWLfks2t2LCGPZSY CyI2Ok64kg9X/tYaObnY/2Cs5F59yn9Gp5Tq/FBSluIU/kdg+FD3HhECswiVzVLWufR0 IDntF5Ql0lL+1lW2gZxFClJ0cyn0r4ckdCVvfGx+Ehv0q9C2Sb4NBl3LS4wdXFuEwY1f 2lQg== X-Gm-Message-State: AJIora9UxO7kZxeAt6iPAz09pFegMW2m/BgQFsMzHF1/ByiOURhHSGTT dNtL47exoe/1A6iiNPmMermUKCMh9OlykQ== X-Google-Smtp-Source: AGRyM1v5Xzcym4YnAD79hL0bh2oy6ae6OswhI3kx+ciXW89Oq79USuQPw9A2J/Gc13D7W+I6/EmxGg== X-Received: by 2002:a05:600c:4f05:b0:3a3:18ed:6cda with SMTP id l5-20020a05600c4f0500b003a318ed6cdamr6609474wmq.34.1658152772811; Mon, 18 Jul 2022 06:59:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register Date: Mon, 18 Jul 2022 14:59:17 +0100 Message-Id: <20220718135920.13667-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154585226100001 Content-Type: text/plain; charset="utf-8" From: Hao Wu The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch fixes that in the module, and also lower the IRQ when the guest is done handling an interrupt event from the ADC module. Signed-off-by: Hao Wu Reviewed-by: Patrick Venture Reviewed-by: Peter Maydell Message-id: 20220714182836.89602-4-wuhaotsh@google.com Signed-off-by: Peter Maydell --- hw/adc/npcm7xx_adc.c | 2 +- tests/qtest/npcm7xx_adc-test.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 0f0a9f63e20..47fb9e5f74c 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4) #define NPCM7XX_ADC_CON_INT BIT(18) #define NPCM7XX_ADC_CON_EN BIT(17) #define NPCM7XX_ADC_CON_RST BIT(16) -#define NPCM7XX_ADC_CON_CONV BIT(14) +#define NPCM7XX_ADC_CON_CONV BIT(13) #define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8) =20 #define NPCM7XX_ADC_MAX_RESULT 1023 diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c index 3fa6d9ece0b..8048044d281 100644 --- a/tests/qtest/npcm7xx_adc-test.c +++ b/tests/qtest/npcm7xx_adc-test.c @@ -50,7 +50,7 @@ #define CON_INT BIT(18) #define CON_EN BIT(17) #define CON_RST BIT(16) -#define CON_CONV BIT(14) +#define CON_CONV BIT(13) #define CON_DIV(rv) extract32(rv, 1, 8) =20 #define FST_RDST BIT(1) --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154897; cv=none; d=zohomail.com; s=zohoarc; b=W6d9ms8xLvMy+Klbv9oS0CcLxsunYNRaK3hfOoRCSMZNhxLs8d87k7Y1gr8u8roUpxcyDRm1d7r//6pX8ITZXqdt73gYNEJ1wrOaNw9cY5cxoeDvMeCUSss4E2lA5iwiaJv7GO1pXi3Nl4mTccbIL+79PK+v1YitVVEPwnPIsHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154897; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WLcuE5tjCtEqKCJRkl1tlMmWsSxVcZNfqF25uGydMws=; b=BLhclcj3zTHRpge/p7wW/xFH2g/IWNRJ1l95hXKj4yuRYI96nUuxjxF/wXAd1doYHFZAD2zQ/053YcaeZOHKKXnti68orbb5Kbus9qmJhUV0vfPCWf14sfkDMJfrLmvJHlu0nO2kXFBmWnwvfOksMoe2lYWkPrw8t9Fj2zl7ejI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154897724571.0388406991877; Mon, 18 Jul 2022 07:34:57 -0700 (PDT) Received: from localhost ([::1]:57560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRpo-00022b-9Z for importer@patchew.org; Mon, 18 Jul 2022 10:34:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHg-0002Aa-2z for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:40 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:46668) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHc-0003BN-K0 for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:39 -0400 Received: by mail-wm1-x334.google.com with SMTP id h14-20020a1ccc0e000000b0039eff745c53so7383727wmb.5 for ; Mon, 18 Jul 2022 06:59:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WLcuE5tjCtEqKCJRkl1tlMmWsSxVcZNfqF25uGydMws=; b=fYKyNHXSBBvyuI4ylw/1BSjyAcT/gtUPYB0/eyxTj4WTnjemB3qyMzif1Ckd8nQQ/S wOItfR1R1Jcyn9RuaFCpqRI0isZpuyvc0nugCgGn5W2wN7dsAJ8vTgcM2lhSrXhOfhJQ +uoo3b7WlJ5npBbnlDtmkYhuoyHjFFetYVijsY+7JFyj+cOEqCPMAQAXTtSI0/ZICROx b9QNd10LIA2fvyZJJTCLuyAEFFvL10MeQoDuSAqwc4w5utrCqIdNcr2iH7bvAK1FwqkE u2e4LuKi6Y28Jc90WOXn6GCj1QPMthin1YdmjCwYKQqUrLAOehn48wMctMlxcRY50NIo idOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WLcuE5tjCtEqKCJRkl1tlMmWsSxVcZNfqF25uGydMws=; b=6pLsrs7NSpE/CP8Ld795DsdGwlN+te22ZAfya+HuQcnMELbimE8ynXDa0T12/zOFjG x8IdIVhY+uWBgGJ0QeQx2f7V214HUFp5BYilGTcwfniNLK31vdGMUeDsCva16Qh3jPwR 7VQnXyMkMPMcrHDDCtzYeCJlVR/NXT8fdcMvRRPCAUERqmRnfnREgTDElDcR3Fe2Klcz ZH6y8AaClG6x+SrfN/Bsic5mIyFaeVYHESz/Ckngf1F7xRg5+g7KW2anh6xpA/tzg7v/ aLiQvmmjZLCPaH8Mdnjw1LvpdAQUvjNT+gB+nhd/nFO/hbvrj5qMJl+KM0A3BqeJpx6Z Tahg== X-Gm-Message-State: AJIora/4RUpXtFOi9tteR/PKDn9Jys9xKHYSBD1S4mcBFPUHWeAod6G+ oPqQ4pwNPcqBnc3EkzTGguGzqdhxSxjG3g== X-Google-Smtp-Source: AGRyM1ukpoeDg3et4ykUry7JCnSiAVEcvVu6WAzp16PfjPwnxLdNpbBI+XqvmavS2fU6l067hJGu2A== X-Received: by 2002:a05:600c:3786:b0:3a3:19d4:293f with SMTP id o6-20020a05600c378600b003a319d4293fmr5745802wmr.116.1658152773460; Mon, 18 Jul 2022 06:59:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/15] hw/adc: Make adci[*] R/W in NPCM7XX ADC Date: Mon, 18 Jul 2022 14:59:18 +0100 Message-Id: <20220718135920.13667-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154898725100001 Content-Type: text/plain; charset="utf-8" From: Hao Wu Our sensor test requires both reading and writing from a sensor's QOM property. So we need to make the input of ADC module R/W instead of write only for that to work. Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Reviewed-by: Peter Maydell Message-id: 20220714182836.89602-5-wuhaotsh@google.com Signed-off-by: Peter Maydell --- hw/adc/npcm7xx_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 47fb9e5f74c..bc6f3f55e64 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -242,7 +242,7 @@ static void npcm7xx_adc_init(Object *obj) =20 for (i =3D 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) { object_property_add_uint32_ptr(obj, "adci[*]", - &s->adci[i], OBJ_PROP_FLAG_WRITE); + &s->adci[i], OBJ_PROP_FLAG_READWRITE); } object_property_add_uint32_ptr(obj, "vref", &s->vref, OBJ_PROP_FLAG_WRITE); --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154758; cv=none; d=zohomail.com; s=zohoarc; b=dzQ3XyEQYMmXMomIVbpLKqkSxWKauAbnSgItqvu8zwiQaeYEvctyoKNA02JJAEdHU/cpkiSdQ9OU3eZYviUOtpM2t4o1cMr6MV+g8tUtqrR9fgzCVsvvKIWyqn8swHyo34xXBmNid2X18s/tM7mPwfzdPdI5vJFcqp7o3uqokd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154758; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QuX4bqrgJsmwtriilRgKBMrcdhU6Sl9wuLdDCeKIqPA=; b=cdfUicKbZnCxvWtaPZqFaz8O/y4CuAN5jXfc6HKg+tsv5tZCX4szMZll9fFDenkQkuDIXw+Fy5CY2RvY5NKFDcXUQ1rT7V91JS+fEEoIIW5pFvvW9yZMy6u3ziXGDk/XINJATbhkGO5BdvBWH1EEOtuo8YZvhgSlqlOZUx1Ji0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154758985545.5654184777012; Mon, 18 Jul 2022 07:32:38 -0700 (PDT) Received: from localhost ([::1]:51204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRnZ-0006As-Nz for importer@patchew.org; Mon, 18 Jul 2022 10:32:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHg-0002Ab-2z for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:40 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:38483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHc-0003BY-KD for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:39 -0400 Received: by mail-wr1-x42f.google.com with SMTP id e15so11928448wro.5 for ; Mon, 18 Jul 2022 06:59:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QuX4bqrgJsmwtriilRgKBMrcdhU6Sl9wuLdDCeKIqPA=; b=yeo4kAbgcRFI2xj8qr1qnEm+LX1spGKQOX8EAsgQYXamXrLPOwo5AniMVL4Hf52+DR ZGnHg3y4INJDBWiyL1KJTHasSHhDYuP2ZuAP11M70BzlCjpu9wO5EPqb6SDM4hpwNSgK XBfMlJKtqn+5klVBCX6J/4wxM+VNqTAOL/ZeXa+RW+xXJN27Dup9izN67v2WLQgS9mSv 0brkD8wyZtlFupPBpT7+DuHu+qZ32W/uZeXaIbQ5zeJpQg5Fw9s+HH4eBD3jECI2HZaQ pNakzN1WGCyfIPveZ+TIyj74yRehPRNYNR/flJmpkvyhmchgfoF4Ip10BElg4FQ/mJlU Hm4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QuX4bqrgJsmwtriilRgKBMrcdhU6Sl9wuLdDCeKIqPA=; b=ZkLE0CSFF0drlqqwnGk5jAstgYybkinbJGbY89kxV0+Tld49m1+3rkYgXHmmurhfWh Uj/lP4/K9FpWoiMQhxR+vSel2/9VjKWq4bLxObKgfEQxlbSXv0WvwKR/mM1cxDIAU543 LC+0rH15/vwDHdihxsxcsJVOuWS54MGWjXTaICz5gqunb6h7vN3kub4CvVf/1MKCOv7w naQ2k6p6N/ovHZds4mpu6Pco3UrjrBGlPe7K7vy+aC+0aiZndnrOntulrbBY/mmVzIy2 Sg2Tke0c8ko4zphju7tCHz71Ecutfp2XKqMYBxEGwrY/Ept7YfZhk7dyGoiByRxZD0qd Eftw== X-Gm-Message-State: AJIora+0kVivwwjqw+ODgBIiZ9LpKoouHYLDnUb07OnVCWu1UTT6UDUF jdbyfuuYPTOiG/sNlVqwtfr5vgIeG/Lm/w== X-Google-Smtp-Source: AGRyM1sK2vSb56MQTc1HV1gpuHD3i9M9Ea+FvzBL3prUu2jKom0WL6+KC+y9dpp3+F0xVhAFhHTplA== X-Received: by 2002:a05:6000:1cc:b0:21d:a352:116b with SMTP id t12-20020a05600001cc00b0021da352116bmr22210409wrx.418.1658152774160; Mon, 18 Jul 2022 06:59:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback Date: Mon, 18 Jul 2022 14:59:19 +0100 Message-Id: <20220718135920.13667-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154759872100001 Content-Type: text/plain; charset="utf-8" The architecture requires that for faults on loads and stores which do writeback, the syndrome information does not have the ISS instruction syndrome information (i.e. ISV is 0). We got this wrong for the load and store instructions covered by disas_ldst_reg_imm9(). Calculate iss_valid correctly so that if the insn is a writeback one it is false. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org --- target/arm/translate-a64.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7b64f73584..163df8c6157 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3138,7 +3138,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool is_store =3D false; bool is_extended =3D false; bool is_unpriv =3D (idx =3D=3D 2); - bool iss_valid =3D !is_vector; + bool iss_valid; bool post_index; bool writeback; int memidx; @@ -3191,6 +3191,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, g_assert_not_reached(); } =20 + iss_valid =3D !is_vector && !writeback; + if (rn =3D=3D 31) { gen_check_sp_alignment(s); } --=20 2.25.1 From nobody Wed Apr 16 05:25:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1658154900; cv=none; d=zohomail.com; s=zohoarc; b=aIYZMCIF9qnr/lXH5PYKkyWX5FULUk5OorZ9O99qkQJUzTzZJlW3R0uRDpcFSOH2qZSWbh+YokVNTZx8y7Me50iFzv1fEwmUvq/Ubv1v5UlJtF9ZMVxXrROH2uZHob0oSGOzSWbswaxdjWjLUoEK5CxgweT+LA3oJIpw8hbZwPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658154900; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O9MWcMSwBbu4CMzo7bCb2HSbS/5shVLaXo9ftmPe+ww=; b=Zvqj7GKMjWzILodjiy9BsXmn91Jp02IB+tcEiTQRRlZ88NPtoTCRhpgL1lW2W5fhOgxjrpaY+8MxM2D5FtMbH7kt87rTD0vvvMsy+kqwarl5mZiQFNO+bRnQhq1KQsRYn1w+XLYQBbuU183BTIn9x/41nzXOTqvKmOTRS9xYChg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658154900359586.8185751299825; Mon, 18 Jul 2022 07:35:00 -0700 (PDT) Received: from localhost ([::1]:57782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDRpr-0002BO-CM for importer@patchew.org; Mon, 18 Jul 2022 10:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDRHh-0002BX-BB for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:42 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:39606) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oDRHd-0003Be-RH for qemu-devel@nongnu.org; Mon, 18 Jul 2022 09:59:41 -0400 Received: by mail-wr1-x42b.google.com with SMTP id v16so1356867wrr.6 for ; Mon, 18 Jul 2022 06:59:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id id15-20020a05600ca18f00b003a31f1edfa7sm1805798wmb.41.2022.07.18.06.59.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 06:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O9MWcMSwBbu4CMzo7bCb2HSbS/5shVLaXo9ftmPe+ww=; b=HeyTXnKydzyjdu4GVNmzN8UEMoqwJbfD0PphBX71PvydJLoxJBMbjq9IOT6EoSWHd0 tMtDAopuF6n3UdYtkgf4h1V8iR0wVLAw0ifOCIeBndQY/Zakbjkp7o6pZIyQxo8zUi0K /E9hinhd2Lv0XvL+/4gNNUIhNMWThzSbF5Qk9V6NqYeMEUmbeJk0lVSt5OWTLfrHHxsZ fh656WOE7EI1NDQ/pqi8CxhDEYbh1QjEVE0wyTSTLf5cUSY3v8L36U/mx+rLWjaO09+k 15ucqGVDrJoLZ6iY1GFeoBtstxVruAKwO51w6SkJ4q4ItaJ/S5ICyunUSNuAFhZ6BjGx DG7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O9MWcMSwBbu4CMzo7bCb2HSbS/5shVLaXo9ftmPe+ww=; b=1EUAjSnXVBSr3g+jmiZjvvZVo6FLj7x2/EV4IJRmHLrNLUTLvBDW8D/vf0HMTsZpOu seD/He0Wf8BtDDH8ZkWKwNC+ts5TL1Dp/ckEepk/GOwE0MAAvR8PUChvET5oa/p9cL4+ suE7AkAH8DQFMwDbz7q1sHxrezV28DF1WVXDCMPJRgygRUp1j8USuVQx7EqDuz0XU2+2 EgedeGuDzQd78GFPU424+hMB6Tx+qCzUbnNSvfYPE+Pp0GCF/adMgiBQ0idiOpnEARAg dxnrkDhvetdw4m++qJSfAZOzp+xo1Kd27KR2v+kiDwmWaqXjcNQVqOzfaouCT0OfKuyY WlLA== X-Gm-Message-State: AJIora/RHx/3BcyMMNh8VEV64jVJa2bOAkeCx7yWI9f4UfLOTx3wyaze YUpbSmCxjnNeKsq90qNO+oiebtzkzc3AHg== X-Google-Smtp-Source: AGRyM1uamPAydzT6x0uy2qyaaKJ6v35TDP1R9mBY/0mdlBW+qNzokFB+FM7vXMfjlCaykf0h9Aa6nQ== X-Received: by 2002:a05:6000:1887:b0:21d:97cf:6b80 with SMTP id a7-20020a056000188700b0021d97cf6b80mr23413594wri.571.1658152775014; Mon, 18 Jul 2022 06:59:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/15] Align Raspberry Pi DMA interrupts with Linux DTS Date: Mon, 18 Jul 2022 14:59:20 +0100 Message-Id: <20220718135920.13667-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718135920.13667-1-peter.maydell@linaro.org> References: <20220718135920.13667-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1658154900655100003 Content-Type: text/plain; charset="utf-8" From: Andrey Makarov There is nothing in the specs on DMA engine interrupt lines: it should have been in the "BCM2835 ARM Peripherals" datasheet but the appropriate "ARM peripherals interrupt table" (p.113) is nearly empty. All Raspberry Pi models 1-3 (based on bcm2835) have Linux device tree (arch/arm/boot/dts/bcm2835-common.dtsi +25): /* dma channel 11-14 share one irq */ This information is repeated in the driver code (drivers/dma/bcm2835-dma.c +1344): /* * in case of channel >=3D 11 * use the 11th interrupt and that is shared */ In this patch channels 0--10 and 11--14 are handled separately. Signed-off-by: Andrey Makarov Message-id: 20220716113210.349153-1-andrey.makarov@auriga.com [PMM: fixed checkpatch nits] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/bcm2835_peripherals.h | 2 + hw/arm/bcm2835_peripherals.c | 26 +++++- tests/qtest/bcm2835-dma-test.c | 118 +++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 4 files changed, 147 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/bcm2835-dma-test.c diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index d864879421a..c9d25d493e0 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -17,6 +17,7 @@ #include "hw/char/bcm2835_aux.h" #include "hw/display/bcm2835_fb.h" #include "hw/dma/bcm2835_dma.h" +#include "hw/or-irq.h" #include "hw/intc/bcm2835_ic.h" #include "hw/misc/bcm2835_property.h" #include "hw/misc/bcm2835_rng.h" @@ -55,6 +56,7 @@ struct BCM2835PeripheralState { BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; + qemu_or_irq orgated_dma_irq; BCM2835ICState ic; BCM2835PropertyState property; BCM2835RngState rng; diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 48538c9360c..3c2a4160cd1 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -23,6 +23,13 @@ /* Capabilities for SD controller: no DMA, high-speed, default clocks etc.= */ #define BCM2835_SDHC_CAPAREG 0x52134b4 =20 +/* + * According to Linux driver & DTS, dma channels 0--10 have separate IRQ, + * while channels 11--14 share one IRQ: + */ +#define SEPARATE_DMA_IRQ_MAX 10 +#define ORGATED_DMA_IRQ_COUNT 4 + static void create_unimp(BCM2835PeripheralState *ps, UnimplementedDeviceState *uds, const char *name, hwaddr ofs, hwaddr size) @@ -101,6 +108,11 @@ static void bcm2835_peripherals_init(Object *obj) /* DMA Channels */ object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA); =20 + object_initialize_child(obj, "orgated-dma-irq", + &s->orgated_dma_irq, TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->orgated_dma_irq), "num-lines", + ORGATED_DMA_IRQ_COUNT, &error_abort); + object_property_add_const_link(OBJECT(&s->dma), "dma-mr", OBJECT(&s->gpu_bus_mr)); =20 @@ -322,12 +334,24 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); =20 - for (n =3D 0; n <=3D 12; n++) { + for (n =3D 0; n <=3D SEPARATE_DMA_IRQ_MAX; n++) { sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_DMA0 + n)); } + if (!qdev_realize(DEVICE(&s->orgated_dma_irq), NULL, errp)) { + return; + } + for (n =3D 0; n < ORGATED_DMA_IRQ_COUNT; n++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), + SEPARATE_DMA_IRQ_MAX + 1 + n, + qdev_get_gpio_in(DEVICE(&s->orgated_dma_irq), n= )); + } + qdev_connect_gpio_out(DEVICE(&s->orgated_dma_irq), 0, + qdev_get_gpio_in_named(DEVICE(&s->ic), + BCM2835_IC_GPU_IRQ, + INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1)); =20 /* THERMAL */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) { diff --git a/tests/qtest/bcm2835-dma-test.c b/tests/qtest/bcm2835-dma-test.c new file mode 100644 index 00000000000..8293d822b94 --- /dev/null +++ b/tests/qtest/bcm2835-dma-test.c @@ -0,0 +1,118 @@ +/* + * QTest testcase for BCM283x DMA engine (on Raspberry Pi 3) + * and its interrupts coming to Interrupt Controller. + * + * Copyright (c) 2022 Auriga LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* Offsets in raspi3b platform: */ +#define RASPI3_DMA_BASE 0x3f007000 +#define RASPI3_IC_BASE 0x3f00b200 + +/* Used register/fields definitions */ + +/* DMA engine registers: */ +#define BCM2708_DMA_CS 0 +#define BCM2708_DMA_ACTIVE (1 << 0) +#define BCM2708_DMA_INT (1 << 2) + +#define BCM2708_DMA_ADDR 0x04 + +#define BCM2708_DMA_INT_STATUS 0xfe0 + +/* DMA Trasfer Info fields: */ +#define BCM2708_DMA_INT_EN (1 << 0) +#define BCM2708_DMA_D_INC (1 << 4) +#define BCM2708_DMA_S_INC (1 << 8) + +/* Interrupt controller registers: */ +#define IRQ_PENDING_BASIC 0x00 +#define IRQ_GPU_PENDING1_AGGR (1 << 8) +#define IRQ_PENDING_1 0x04 +#define IRQ_ENABLE_1 0x10 + +/* Data for the test: */ +#define SCB_ADDR 256 +#define S_ADDR 32 +#define D_ADDR 64 +#define TXFR_LEN 32 +const uint32_t check_data =3D 0x12345678; + +static void bcm2835_dma_test_interrupt(int dma_c, int irq_line) +{ + uint64_t dma_base =3D RASPI3_DMA_BASE + dma_c * 0x100; + int gpu_irq_line =3D 16 + irq_line; + + /* Check that interrupts are silent by default: */ + writel(RASPI3_IC_BASE + IRQ_ENABLE_1, 1 << gpu_irq_line); + int isr =3D readl(dma_base + BCM2708_DMA_INT_STATUS); + g_assert_cmpint(isr, =3D=3D, 0); + uint32_t reg0 =3D readl(dma_base + BCM2708_DMA_CS); + g_assert_cmpint(reg0, =3D=3D, 0); + uint32_t ic_pending =3D readl(RASPI3_IC_BASE + IRQ_PENDING_BASIC); + g_assert_cmpint(ic_pending, =3D=3D, 0); + uint32_t gpu_pending1 =3D readl(RASPI3_IC_BASE + IRQ_PENDING_1); + g_assert_cmpint(gpu_pending1, =3D=3D, 0); + + /* Prepare Control Block: */ + writel(SCB_ADDR + 0, BCM2708_DMA_S_INC | BCM2708_DMA_D_INC | + BCM2708_DMA_INT_EN); /* transfer info */ + writel(SCB_ADDR + 4, S_ADDR); /* source address */ + writel(SCB_ADDR + 8, D_ADDR); /* destination address */ + writel(SCB_ADDR + 12, TXFR_LEN); /* transfer length */ + writel(dma_base + BCM2708_DMA_ADDR, SCB_ADDR); + + writel(S_ADDR, check_data); + for (int word =3D S_ADDR + 4; word < S_ADDR + TXFR_LEN; word +=3D 4) { + writel(word, ~check_data); + } + /* Perform the transfer: */ + writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_ACTIVE); + + /* Check that destination =3D=3D source: */ + uint32_t data =3D readl(D_ADDR); + g_assert_cmpint(data, =3D=3D, check_data); + for (int word =3D D_ADDR + 4; word < D_ADDR + TXFR_LEN; word +=3D 4) { + data =3D readl(word); + g_assert_cmpint(data, =3D=3D, ~check_data); + } + + /* Check that interrupt status is set both in DMA and IC controllers: = */ + isr =3D readl(RASPI3_DMA_BASE + BCM2708_DMA_INT_STATUS); + g_assert_cmpint(isr, =3D=3D, 1 << dma_c); + + ic_pending =3D readl(RASPI3_IC_BASE + IRQ_PENDING_BASIC); + g_assert_cmpint(ic_pending, =3D=3D, IRQ_GPU_PENDING1_AGGR); + + gpu_pending1 =3D readl(RASPI3_IC_BASE + IRQ_PENDING_1); + g_assert_cmpint(gpu_pending1, =3D=3D, 1 << gpu_irq_line); + + /* Clean up, clear interrupt: */ + writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_INT); +} + +static void bcm2835_dma_test_interrupts(void) +{ + /* DMA engines 0--10 have separate IRQ lines, 11--14 - only one: */ + bcm2835_dma_test_interrupt(0, 0); + bcm2835_dma_test_interrupt(10, 10); + bcm2835_dma_test_interrupt(11, 11); + bcm2835_dma_test_interrupt(14, 11); +} + +int main(int argc, char **argv) +{ + int ret; + g_test_init(&argc, &argv, NULL); + qtest_add_func("/bcm2835/dma/test_interrupts", + bcm2835_dma_test_interrupts); + qtest_start("-machine raspi3b"); + ret =3D g_test_run(); + qtest_end(); + return ret; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 31287a91739..3a474010e49 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -218,7 +218,8 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'bcm2835-dma-test'] =20 qtests_s390x =3D \ (slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \ --=20 2.25.1