From nobody Mon Feb 9 23:18:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1658149946708476.3855016142852; Mon, 18 Jul 2022 06:12:26 -0700 (PDT) Received: from localhost ([::1]:43898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDQXx-00062O-EE for importer@patchew.org; Mon, 18 Jul 2022 09:12:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oDQVt-0002JK-Ka; Mon, 18 Jul 2022 09:10:17 -0400 Received: from smtp21.cstnet.cn ([159.226.251.21]:43144 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oDQVo-000308-4Q; Mon, 18 Jul 2022 09:10:17 -0400 Received: from localhost.localdomain (unknown [180.156.173.38]) by APP-01 (Coremail) with SMTP id qwCowABnbweqW9Vi5+hPEQ--.55056S5; Mon, 18 Jul 2022 21:10:05 +0800 (CST) From: Weiwei Li To: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH V3 3/6] target/riscv: Fix checkpatch warning may triggered in csr_ops table Date: Mon, 18 Jul 2022 21:09:52 +0800 Message-Id: <20220718130955.11899-4-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220718130955.11899-1-liweiwei@iscas.ac.cn> References: <20220718130955.11899-1-liweiwei@iscas.ac.cn> X-CM-TRANSID: qwCowABnbweqW9Vi5+hPEQ--.55056S5 X-Coremail-Antispam: 1UD129KBjvAXoWfuF17trWxCrW8Xw17XFy5Arb_yoW5Ar1fKo W5Ja15Zws2kr1jgFyFvFs3Xr43CF15C3WSva1rCF1DGFy8KrWUWr9xCFWUX3WrGF1UuFyU Ww10y3yqkFZagr13n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYm7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUd8n5UUUUU= X-Originating-IP: [180.156.173.38] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1658149947506100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fix the lines with over 80 characters Fix the lines which are obviously misalgined with other lines in the same group Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/csr.c | 441 ++++++++++++++++++++++++--------------------- 1 file changed, 234 insertions(+), 207 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 235f2a011e..7d4b6ceced 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3461,20 +3461,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_FRM] =3D { "frm", fs, read_frm, write_frm }, [CSR_FCSR] =3D { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VL] =3D { "vl", vs, read_vl, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VTYPE] =3D { "vtype", vs, read_vtype, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, - [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VL] =3D { "vl", vs, read_vl, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VTYPE] =3D { "vtype", vs, read_vtype, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, /* User Timers and Counters */ [CSR_CYCLE] =3D { "cycle", ctr, read_hpmcounter }, [CSR_INSTRET] =3D { "instret", ctr, read_hpmcounter }, @@ -3493,10 +3493,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, write_mhpmc= ounter}, - [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, write_mhpmc= ounter}, - [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, write_mhpm= counterh}, - [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, write_mhpm= counterh}, + [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MINSTRET] =3D { "minstret", any, read_hpmcounter, + write_mhpmcounter }, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_hpmcounterh, + write_mhpmcounterh }, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_hpmcounterh, + write_mhpmcounterh }, =20 /* Machine Information Registers */ [CSR_MVENDORID] =3D { "mvendorid", any, read_mvendorid }, @@ -3505,23 +3509,25 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 [CSR_MCONFIGPTR] =3D { "mconfigptr", any, read_zero, - .min_priv_ver =3D PRIV_VERSION_1_1= 2_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, /* Machine Trap Setup */ - [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_m= status, NULL, - read_mstatus_i128 = }, - [CSR_MISA] =3D { "misa", any, read_misa, write_m= isa, NULL, - read_misa_i128 = }, - [CSR_MIDELEG] =3D { "mideleg", any, NULL, NULL, rmw_mid= eleg }, - [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_m= edeleg }, - [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie= }, - [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, - [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, - - [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, + [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_mstat= us, + NULL, read_mstatus_i128 = }, + [CSR_MISA] =3D { "misa", any, read_misa, write_misa, + NULL, read_misa_i128 = }, + [CSR_MIDELEG] =3D { "mideleg", any, NULL, NULL, rmw_mideleg= }, + [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_medel= eg }, + [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie = }, + [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_mtvec= }, + [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, + write_mcounteren = }, + + [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, + write_mstatush = }, =20 /* Machine Trap Handling */ - [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscra= tch, NULL, - read_mscratch_i128, write_mscratc= h_i128 }, + [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch, + NULL, read_mscratch_i128, write_mscratch_i128 }, [CSR_MEPC] =3D { "mepc", any, read_mepc, write_mepc }, [CSR_MCAUSE] =3D { "mcause", any, read_mcause, write_mcause }, [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval }, @@ -3532,12 +3538,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIREG] =3D { "mireg", aia_any, NULL, NULL, rmw_xireg }, =20 /* Machine-Level Interrupts (AIA) */ - [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, - [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, + [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, + [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 /* Virtual Interrupts for Supervisor Level (AIA) */ - [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, - [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, + [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, + [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, =20 /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, @@ -3548,33 +3554,34 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Execution environment configuration */ [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, write_menvcfg, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, write_senvcfg, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HENVCFG] =3D { "henvcfg", hmode, read_henvcfg, write_henvcfg, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, - .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 /* Supervisor Trap Setup */ - [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, - read_sstatus_i128 = }, - [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, - [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, - [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, write_sco= unteren }, + [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, + NULL, read_sstatus_i128 = }, + [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, + [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, + [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, + write_scounteren = }, =20 /* Supervisor Trap Handling */ - [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch,= NULL, - read_sscratch_i128, write_sscrat= ch_i128 }, + [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch, + NULL, read_sscratch_i128, write_sscratch_i128 }, [CSR_SEPC] =3D { "sepc", smode, read_sepc, write_sepc = }, [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause = }, - [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval }, + [CSR_STVAL] =3D { "stval", smode, read_stval, write_stval = }, [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip = }, =20 /* Supervisor Protection and Translation */ - [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, + [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, @@ -3588,87 +3595,100 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, =20 - [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_= hstatus, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_= hedeleg, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_hs= tatus, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_he= deleg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_hide= leg, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_hv= ip, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_hi= p, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_h= ie, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, write= _hcounteren, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTVAL] =3D { "htval", hmode, read_htval, write_= htval, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTINST] =3D { "htinst", hmode, read_htinst, write_= htinst, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_hvip, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_hip, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_hie, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, + write_hcounteren, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, write_hg= eie, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTVAL] =3D { "htval", hmode, read_htval, write_ht= val, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTINST] =3D { "htinst", hmode, read_htinst, write_ht= inst, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_= hgatp, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, write= _htimedelta, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - - [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, write_= vsstatus, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_vs= ip, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie , - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, write_= vstvec, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, write_= vsscratch, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, write_= vsepc, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, write_= vscause, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, write_= vstval, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_= vsatp, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_= mtval2, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, - [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_= mtinst, - .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_hg= atp, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, + write_htimedelta, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, + write_htimedeltah, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + + [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, + write_vsstatus, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_vsi= p, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_vsi= e , + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, write_v= stvec, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, + write_vsscratch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, write_v= sepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, write_v= scause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, write_v= stval, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_v= satp, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + + [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_m= tval2, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_m= tinst, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, - [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_h= victl }, - [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, wri= te_hviprio1 }, - [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, wri= te_hviprio2 }, + [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, + write_hvictl = }, + [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, + write_hviprio1 = }, + [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, + write_hviprio2 = }, =20 /* * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) */ - [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, rmw= _xiselect }, - [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw= _xireg }, + [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, + rmw_xiselect = }, + [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw_xire= g }, =20 /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, =20 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ - [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hi= delegh }, - [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write_i= gnore }, + [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, + rmw_hidelegh = }, + [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, + write_ignore = }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, - [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, wr= ite_hviprio1h }, - [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, wr= ite_hviprio2h }, + [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, + write_hviprio1h = }, + [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, + write_hviprio2h = }, [CSR_VSIEH] =3D { "vsieh", aia_hmode32, NULL, NULL, rmw_vs= ieh }, [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 /* Physical Memory Protection */ [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg, - .min_priv_ver =3D PRIV_VERSION_1_11_0= }, + .min_priv_ver =3D PRIV_VERSION_1_11_0 }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, @@ -3697,17 +3717,23 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, =20 /* User Pointer Masking */ - [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write= _umte }, - [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, write= _upmmask }, - [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, write= _upmbase }, + [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, + [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, + write_upmmask = }, + [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, + write_upmbase = }, /* Machine Pointer Masking */ - [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write= _mmte }, - [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, write= _mpmmask }, - [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, write= _mpmbase }, + [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write_m= mte }, + [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, + write_mpmmask = }, + [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, + write_mpmbase = }, /* Supervisor Pointer Masking */ - [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write= _smte }, - [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, write= _spmmask }, - [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, write= _spmbase }, + [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write_s= mte }, + [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, + write_spmmask = }, + [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, + write_spmbase = }, =20 /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, @@ -3741,125 +3767,126 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_hpmcounter }, =20 [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_hpmcounter, - write_mhpmcounter }, + write_mhpmcounter }, =20 [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_mcountinhibit, - write_mcountinhibit, .min_priv_ver =3D PRIV_VERSION_1_11_0 = }, + write_mcountinhibit, + .min_priv_ver =3D PRIV_VERSION_1_11_0 }, =20 [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, - write_mhpmevent }, + write_mhpmevent }, =20 [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_hpmcounterh = }, [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_hpmcounterh = }, @@ -3892,62 +3919,62 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_hpmcounterh = }, =20 [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", mctr32, read_hpmcounterh, - write_mhpmcounterh = }, + write_mhpmcounterh }, #endif /* !CONFIG_USER_ONLY */ }; --=20 2.17.1