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bh=8nOYtLg5Jy2sttae4V+uWElgxSmPH5mKbfYxmvQxdjo=; b=t7EBt59edtqKgH7kRV9/RbC2aEGpMEHDbMwU9Xome5ilNUA2NUdTRGqz oBevkzQgnsxmsOXZ/c3O0siJj8MxaKhxvimzydbcM1Mj8Xa+vEiHQ2gSW HZmWJEUSSyV5tzPGSoXyTJXJWlhMgDnoMw/yTo/QlsNpYG7d5dF8TKE5c s=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 Date: Mon, 18 Jul 2022 13:54:30 +0200 Message-ID: <20220718115433.802-7-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145443466100001 From: Tobias R=C3=B6hmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/debug_helper.c | 3 ++- target/arm/internals.h | 3 ++- target/arm/tlb_helper.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b18a6bd3a2..44b1e32974 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -434,7 +434,8 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) using_lpae =3D true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + ((env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE) + || arm_feature(env, ARM_FEATURE_V8_R))) { using_lpae =3D true; } } diff --git a/target/arm/internals.h b/target/arm/internals.h index b03049d920..e2a2b03d41 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -254,7 +254,8 @@ static inline bool extended_addresses_enabled(CPUARMSta= te *env) { TCR *tcr =3D &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; return arm_el_is_aa64(env, 1) || - (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); + (arm_feature(env, ARM_FEATURE_LPAE) && ((tcr->raw_tcr & TTBCR_E= AE) + || arm_feature(env, ARM_FEATURE_V8_R))); } =20 /* Update a QEMU watchpoint based on the information the guest has set in = the diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7d8a86b3c4..891326edb8 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,8 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx= mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + && ((regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE) + || arm_feature(env, ARM_FEATURE_V8_R))) { return true; } return false; --=20 2.25.1