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bh=9iMmXkp15BF2ELIjH4bO5J3OaLwLhYbO/G4uvh1e78I=; b=TOfV8IAmHNfvPTHxNJJOBd+gslZs8lqA94qrm05zEJYiSF4bPMVT0WEz Nag41wtYiDpm8CWXtS7j+TJVMq+v8Vc5DUL+2cpVNcYoqBCVYWlBchC7c Z5HFbQh6KDQB+WpfB0+ZSoWrHv9zHP1aDpGZMru8dvkrk9xpTiwWBUEBF o=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R Date: Mon, 18 Jul 2022 13:54:26 +0200 Message-ID: <20220718115433.802-3-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145591860100002 From: Tobias R=C3=B6hmel Cortex-R52 has the MPUIR register which has the same encoding has the MIDR alias with opc2=3D4. So we only add that alias when we are not realizing a Cortex-R. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6457e6301c..03bdc3d149 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8189,9 +8189,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, .access =3D PL1_R, .resetvalue =3D cpu->midr }, @@ -8201,6 +8198,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; + ARMCPRegInfo id_v8_midr_alias_cp_reginfo[] =3D { + { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr }, + }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ { .name =3D "CTR", @@ -8264,8 +8266,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; } + if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_V8_R)) { + define_arm_cp_regs(cpu, id_v8_midr_alias_cp_reginfo); + } } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } --=20 2.25.1