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bh=j6hZ0WNJZLcfk4eENbwZVIjSq1eQDNaDZEXP7hNxr2c=; b=ACYLpX/iRLLg6irTNrSL8Ou3AMV4jvezZ6GoCBOQEU2DJFqHxvSZJbRE azopEdx7rbyz/EEmfH1sbMMzKo84ddO1Rhd5fX8P66rWv2VeQvz4oecfS N++y0hSLa5ioVkkBLEJeqklt8rhqT3Advgu2MhUScVESjk74BgsFqDdmE 4=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 1/9] target/arm: Add ARM_FEATURE_V8_R Date: Mon, 18 Jul 2022 13:54:25 +0200 Message-ID: <20220718115433.802-2-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145855827100001 From: Tobias R=C3=B6hmel This flag is necessary to add features for the Cortex-R52. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df677b2d5d..86e06116a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2287,6 +2287,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + ARM_FEATURE_V8_R, }; =20 static inline int arm_feature(CPUARMState *env, int feature) --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1658145591; cv=none; d=zohomail.com; s=zohoarc; b=K15uQyqh9J3z5IoKmFf8dIvBSQS4PUw36UIZYx+6VEXEzxeW7O3qSfoGkGe5YhPGB1Qbk97phYqwOvQjhtn488na5Sm/iirhIHZHKGATve1yp/ZZhvyybb2IF9wICzayqjlIPkF7Yst4vyhKVtP5/HMoT4nGjyWAemmkq96hqLI= ARC-Message-Signature: i=1; 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Mon, 18 Jul 2022 04:54:52 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Jul 2022 04:54:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658145298; x=1689681298; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9iMmXkp15BF2ELIjH4bO5J3OaLwLhYbO/G4uvh1e78I=; b=TOfV8IAmHNfvPTHxNJJOBd+gslZs8lqA94qrm05zEJYiSF4bPMVT0WEz Nag41wtYiDpm8CWXtS7j+TJVMq+v8Vc5DUL+2cpVNcYoqBCVYWlBchC7c Z5HFbQh6KDQB+WpfB0+ZSoWrHv9zHP1aDpGZMru8dvkrk9xpTiwWBUEBF o=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R Date: Mon, 18 Jul 2022 13:54:26 +0200 Message-ID: <20220718115433.802-3-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145591860100002 From: Tobias R=C3=B6hmel Cortex-R52 has the MPUIR register which has the same encoding has the MIDR alias with opc2=3D4. So we only add that alias when we are not realizing a Cortex-R. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6457e6301c..03bdc3d149 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8189,9 +8189,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, .access =3D PL1_R, .resetvalue =3D cpu->midr }, @@ -8201,6 +8198,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; + ARMCPRegInfo id_v8_midr_alias_cp_reginfo[] =3D { + { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr }, + }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ { .name =3D "CTR", @@ -8264,8 +8266,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; } + if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_V8_R)) { + define_arm_cp_regs(cpu, id_v8_midr_alias_cp_reginfo); + } } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1658145445; cv=none; d=zohomail.com; s=zohoarc; b=SAg2f99oEz8uBXkKgMATM5DVpu9aKWUONi7luucSQnZwOLJGRKvKD4Esp+GxD0BgyHXNghAhs4oi7AifOIT/CFk1Y17gzf02eDyusZx6+BVFvg5Gf0FRazlTC1DIIPhNwd+qfJUKWKAjccbg2lvn37trop+WrkyVGwU6WiveogM= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145447372100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..9007768418 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,6 +258,10 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR, CP11, 3); #endif + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.rvbar =3D cpu->rvbar_prop; + env->regs[15] =3D cpu->rvbar_prop; + } } =20 #if defined(CONFIG_USER_ONLY) @@ -1273,7 +1277,7 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_proper= ty); } =20 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1658145591; cv=none; d=zohomail.com; s=zohoarc; b=W23v2grnX0KAQQif/Ko8yc0+cK/9kNPcg0NtxQ6ugdWqnLpeaP9S3i9FWJ2hlHNrZ/rHz/IDsxwxCjdoti0KcH6m8X4ozC2IDd2wbAIc+gD84quvfzlH6VbeSbnwaegV23QPmSFQPMcUF5erkBX9U9zU7DN3Vzhp5uRV2mLTVng= ARC-Message-Signature: i=1; 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Mon, 18 Jul 2022 04:54:54 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Jul 2022 04:54:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658145299; x=1689681299; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hapmOFEwmUHGSMahVEGMQVUPE796CbuBCALsQKsJHd4=; b=ZvrPkc7a9g8obQlnOi6wppKS0prRW1wf9w+kWjdfpEzF7JC7OyO5euFn w7gtS5Ynq7wIba8ssNB9Dje5SvumWyl5zx+CsnVpwpIbkbcvCuLiNbYZ0 xC69jQHX1lQzQNl332Vh2m/54MKTnZzf/UYq4lMPUjGmY3V2c7zSo5tgY c=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes optional Date: Mon, 18 Jul 2022 13:54:28 +0200 Message-ID: <20220718115433.802-5-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145591845100001 From: Tobias R=C3=B6hmel The Cortex-R52 has a 2 stage MPU translation process but doesn't have the F= EAT_S2FWB feature. This makes it neccessary to allow for the old cache attr= ibut combination. This is facilitated by changing the control path of combine_cacheattrs inst= ead of failing if the second cache attributes struct is not in that format. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/ptw.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4d97a24808..8b037c1f55 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2108,7 +2108,11 @@ static uint8_t combined_attrs_nofwb(CPUARMState *env, { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + if (s2.is_s2_format) { + s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + } else { + s2_mair_attrs =3D s2.attrs; + } =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2166,6 +2170,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) static uint8_t combined_attrs_fwb(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2) { + assert(s2.is_s2_format && !s1.is_s2_format); + switch (s2.attrs) { case 7: /* Use stage 1 attributes */ @@ -2215,7 +2221,6 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, ARMCacheAttrs ret; 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Mon, 18 Jul 2022 04:54:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658145300; x=1689681300; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w5IQxraxoSArUuftBd37e45My2CIyqHLGOT+dh/Y/3U=; b=hjNejSj4rcAfc92RljR6kNEgdwybsqSJWqFIGgfno4NHYcBtlY7yCaoI EyqkLzV1VEjK5Pb4lKTuCRxbnhY8X3ZTzQAUQVoaI3WS3+2ga/1qQej1H Yn9oMSR4yPDSAx4n+nsy1dNfsoEo06StGalH4i4uvmr9o1vHJiSxd/oXf E=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup Date: Mon, 18 Jul 2022 13:54:29 +0200 Message-ID: <20220718115433.802-6-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658146067636100001 From: Tobias R=C3=B6hmel Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the = Cortex-R52 MPU which uses and combines cache attributes of different transl= ation levels. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/internals.h | 13 +++++++------ target/arm/m_helper.c | 3 ++- target/arm/ptw.c | 11 +++++++---- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6f94f3019d..b03049d920 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1109,12 +1109,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t = address, MMUAccessType access_type, ARMMMUIdx mmu_idx, V8M_SAttributes *sattrs); =20 -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); - /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { /* @@ -1126,6 +1120,13 @@ typedef struct ARMCacheAttrs { bool is_s2_format:1; } ARMCacheAttrs; =20 +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion, + ARMCacheAttrs *cacheattrs); + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index a740c3e160..44c80d733a 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2829,10 +2829,11 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) !=3D 0 || alt) { + ARMCacheAttrs cacheattrs =3D {0}; /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, &attrs, &prot, &is_subpage, - &fi, &mregion); + &fi, &mregion, &cacheattrs); if (mregion =3D=3D -1) { mrvalid =3D false; mregion =3D 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b037c1f55..c4f5721012 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1702,7 +1702,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) + ARMMMUFaultInfo *fi, uint32_t *mregion, + ARMCacheAttrs *cacheattrs) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1968,7 +1969,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cache= attrs) { uint32_t secure =3D regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs =3D {}; @@ -2036,7 +2037,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } =20 ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); + txattrs, prot, &mpu_is_subpage, fi, + NULL, cacheattrs); *page_size =3D sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } @@ -2416,7 +2418,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - phys_ptr, attrs, prot, page_size, f= i); + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145443466100001 From: Tobias R=C3=B6hmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/debug_helper.c | 3 ++- target/arm/internals.h | 3 ++- target/arm/tlb_helper.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b18a6bd3a2..44b1e32974 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -434,7 +434,8 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) using_lpae =3D true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + ((env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE) + || arm_feature(env, ARM_FEATURE_V8_R))) { using_lpae =3D true; } } diff --git a/target/arm/internals.h b/target/arm/internals.h index b03049d920..e2a2b03d41 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -254,7 +254,8 @@ static inline bool extended_addresses_enabled(CPUARMSta= te *env) { TCR *tcr =3D &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; return arm_el_is_aa64(env, 1) || - (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); + (arm_feature(env, ARM_FEATURE_LPAE) && ((tcr->raw_tcr & TTBCR_E= AE) + || arm_feature(env, ARM_FEATURE_V8_R))); } =20 /* Update a QEMU watchpoint based on the information the guest has set in = the diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 7d8a86b3c4..891326edb8 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -20,7 +20,8 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx= mmu_idx) return true; } if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + && ((regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE) + || arm_feature(env, ARM_FEATURE_V8_R))) { return true; } return false; --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; 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Mon, 18 Jul 2022 04:54:58 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Jul 2022 04:54:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658145301; x=1689681301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F7R/PnhfvZLI8UBzoiGgX1pK4EOqQ3G+phkVa1Mbv2w=; b=NAyTiDgT8enyYvM1PX2h2tiG6lEV7i6FJJUOp/HV2pA2OmvdkVkLYLrM SDvXrPjuzaoM9k4nLOJ7D3/6tiC/yJvTuG8xg2XKDAmkscT34l+IC4oHt AMkjmdbiASS2d1ccoxAg5QyXKjXjAf2C27eTIrAytwD1/HQ+c5pvxVpDp U=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 7/9] target/arm: Add PMSAv8r registers Date: Mon, 18 Jul 2022 13:54:31 +0200 Message-ID: <20220718115433.802-8-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145443493100003 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.h | 10 +++ target/arm/helper.c | 171 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 181 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 86e06116a9..632d0d13c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -726,8 +726,18 @@ typedef struct CPUArchState { */ uint32_t *rbar[M_REG_NUM_BANKS]; uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t prbarn[255]; + uint32_t prlarn[255]; + uint32_t hprbarn[255]; + uint32_t hprlarn[255]; uint32_t mair0[M_REG_NUM_BANKS]; uint32_t mair1[M_REG_NUM_BANKS]; + uint32_t prbar; + uint32_t prlar; + uint32_t prselr; + uint32_t hprbar; + uint32_t hprlar; + uint32_t hprselr; } pmsav8; =20 /* v8M SAU */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 03bdc3d149..f9ed2bd5c3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7422,6 +7422,78 @@ static CPAccessResult access_joscr_jmcr(CPUARMState = *env, return CP_ACCESS_OK; } =20 +static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.prbarn[env->pmsav8.prselr] =3D value; +} + +static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.prlarn[env->pmsav8.prselr] =3D value; +} + +static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.prbarn[env->pmsav8.prselr]; +} + +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.prlarn[env->pmsav8.prselr]; +} + +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.hprbarn[env->pmsav8.hprselr] =3D value; +} + +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.hprlarn[env->pmsav8.hprselr] =3D value; +} + +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t n; + ARMCPU *cpu =3D env_archcpu(env); + for (n =3D 0; n < (int)cpu->pmsav7_dregion; ++n) { + if (value & (1 << n)) { + env->pmsav8.hprlarn[n] |=3D 0x1; + } else { + env->pmsav8.hprlarn[n] &=3D (~0x1); + } + } +} + +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprbarn[env->pmsav8.hprselr]; +} + +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprlarn[env->pmsav8.hprselr]; +} + +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t n; + uint32_t result =3D 0x0; + ARMCPU *cpu =3D env_archcpu(env); + + for (n =3D 0; n < (int)cpu->pmsav7_dregion; ++n) { + if (env->pmsav8.hprlarn[n] & 0x1) { + result |=3D (0x1 << n); + } + } + return result; +} + static const ARMCPRegInfo jazelle_regs[] =3D { { .name =3D "JIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, @@ -8235,6 +8307,46 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; + /* PMSAv8-R registers*/ + ARMCPRegInfo id_pmsav8_r_reginfo[] =3D { + { .name =3D "HMPUIR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 4, .opc2 =3D 4, + .access =3D PL2_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav7_dregion}, + /* PMSAv8-R registers */ + { .name =3D "PRBAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .readfn =3D prbar_read, .writefn =3D prbar_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prbar)}, + { .name =3D "PRLAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .resetvalue =3D 0, + .readfn =3D prlar_read, .writefn =3D prlar_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prlar)}, + { .name =3D "PRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prselr)}, + { .name =3D "HPRBAR", .resetvalue =3D 0, + .readfn =3D hprbar_read, .writefn =3D hprbar_write, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprbar)}, + { .name =3D "HPRLAR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .readfn =3D hprlar_read, .writefn =3D hprlar_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprlar)}, + { .name =3D "HPRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprselr)}, + { .name =3D "HPRENR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .readfn =3D hprenr_read, .writefn =3D hprenr_write}, + }; static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, @@ -8278,6 +8390,65 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V8_R)) { + uint32_t i =3D 0; + char hprbar_string[] =3D "HPRBAR%u"; + char hprlar_string[] =3D "HPRLAR%u"; + + char prbar_string[] =3D "PRBAR%u"; + char prlar_string[] =3D "PRLAR%u"; + char tmp_string[50]; + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + define_arm_cp_regs(cpu, id_pmsav8_r_reginfo); + for (i =3D 0; i < cpu->pmsav7_dregion; ++i) { + uint8_t crm =3D 0b1000 | ((i & 0b1110) >> 1); + uint8_t opc2 =3D (i & 0x1) << 2; + + sprintf(tmp_string, hprbar_string, i); + ARMCPRegInfo tmp_hprbarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprbarn) + + i * sizeof(env->pmsav8.hprbarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); + + sprintf(tmp_string, prbar_string, i); + ARMCPRegInfo tmp_prbarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prbarn) + + i * sizeof(env->pmsav8.prbarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); + + opc2 =3D (i & 0x1) << 2 | 0x1; + sprintf(tmp_string, hprlar_string, i); + ARMCPRegInfo tmp_hprlarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprlarn) + + i * sizeof(env->pmsav8.hprlarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); + + sprintf(tmp_string, prlar_string, i); + ARMCPRegInfo tmp_prlarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prlarn) + + i * sizeof(env->pmsav8.prlarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1658146198; cv=none; d=zohomail.com; s=zohoarc; b=bEWbHBDMGm+lHegz2dMz71epShl2N4H7DyJAbOpmN+aF/Zp0oNN19GpKmDXPlGkSAZeFUkq2+/HUBP9MNZutebGz326KR3NnI2R555vJE/jJpbWEoDPiLIB7G/GzfmtmM2n4Qz41DyYWWYHCVMuXHAReHUugknRahVZI54PGDe4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1658146198; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Mon, 18 Jul 2022 04:54:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658145301; x=1689681301; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rDDYPyAsKAP+4QMNBSGjqis1xptYRxkRlQgJvjG+XY4=; b=eYogbjVyscVGuAUKo308vZZwc2QjjRISEkFtoaYWzDozLn4FQ4xpgfV5 ln5/grmwboykxhCYHcHk7ouHAd2zPPGeGwJ07+tIYnNN6t+sYW1jZWNZb xYiJhyCLuSOwanK7UFJxgVCjnRU5qSpyMzaqJUYgiI1M6+IOMXx2oYLZI E=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 8/9] target/arm: Add PMSAv8r functionality Date: Mon, 18 Jul 2022 13:54:32 +0200 Message-ID: <20220718115433.802-9-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658146200354100001 From: Tobias R=C3=B6hmel Add PMSAv8r translation that is used by the ARM Cortex-R52. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/ptw.c | 171 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 150 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c4f5721012..c7e37c66d0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -140,6 +140,9 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) */ return true; } + } else if (arm_feature(env, ARM_FEATURE_V8_R)) { + return !(regime_sctlr(env, mmu_idx) & SCTLR_M) || + (!(regime_el(env, mmu_idx) =3D=3D 2) && arm_hcr_el2_eff(env) & HCR= _TGE); } =20 hcr_el2 =3D arm_hcr_el2_eff(env); @@ -1504,6 +1507,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,= ARMMMUIdx mmu_idx, if (arm_feature(env, ARM_FEATURE_M)) { return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + } else if (arm_feature(env, ARM_FEATURE_V8_R)) { + return false; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } @@ -1698,6 +1703,77 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, return !(*prot & (1 << access_type)); } =20 +static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprbarn; + } else { + return env->pmsav8.prbarn; + } + } else { + return env->pmsav8.rbar[secure]; + } +} + +static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprlarn; + } else { + return env->pmsav8.prlarn; + } + } else { + return env->pmsav8.rlar[secure]; + } +} + +static inline void get_phys_addr_pmsav8_default(CPUARMState *env, + ARMMMUIdx mmu_idx, + uint32_t address, int *pro= t) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + *prot =3D PAGE_READ | PAGE_WRITE; + if (address <=3D 0x7FFFFFFF) { + *prot |=3D PAGE_EXEC; + } + if ((regime_el(env, mmu_idx) =3D=3D 2) + && (regime_sctlr(env, mmu_idx) & SCTLR_WXN) + && (regime_sctlr(env, mmu_idx) & SCTLR_M)) { + *prot &=3D ~PAGE_EXEC; + } + } else { + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } +} + +static bool pmsav8_fault(bool hit, CPUARMState *env, ARMMMUIdx mmu_idx) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + if (!hit && (mmu_idx !=3D ARMMMUIdx_E2)) { + return true; + } else if (!hit && (mmu_idx =3D=3D ARMMMUIdx_E2) + &&!(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + return true; + } + } else { + if (!hit && (mmu_idx !=3D ARMMMUIdx_Stage1_E1)) { + return true; + } else if (!hit && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1) + &&!(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + return true; + } + } + return false; + } else { + return !hit; + } +} + bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, @@ -1730,6 +1806,12 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, *mregion =3D -1; } =20 + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + fi->stage2 =3D true; + } + } + /* * Unlike the ARM ARM pseudocode, we don't need to check whether this * was an exception vector read from the vector table (which is always @@ -1746,17 +1828,26 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, hit =3D true; } =20 + uint32_t bitmask; + if (arm_feature(env, ARM_FEATURE_V8_R)) { + bitmask =3D 0x3f; + } else { + bitmask =3D 0x1f; + } + + for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ /* - * Note that the base address is bits [31:5] from the register - * with bits [4:0] all zeroes, but the limit address is bits - * [31:5] from the register with bits [4:0] all ones. + * Note that the base address is bits [31:x] from the register + * with bits [x-1:0] all zeroes, but the limit address is bits + * [31:x] from the register with bits [x:0] all ones. Where x = is + * 5 for Cortex-M and 6 for Cortex-R */ - uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; + uint32_t base =3D regime_rbar(env, mmu_idx, secure)[n] & ~bitm= ask; + uint32_t limit =3D regime_rlar(env, mmu_idx, secure)[n] | bitm= ask; =20 - if (!(env->pmsav8.rlar[secure][n] & 0x1)) { + if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) { /* Region disabled */ continue; } @@ -1799,22 +1890,25 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, } } =20 - if (!hit) { - /* background fault */ - fi->type =3D ARMFault_Background; + if (pmsav8_fault(hit, env, mmu_idx)) { + fi->type =3D ARMFault_Permission; + fi->level =3D 0; return true; } =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav8_default(env, mmu_idx, address, prot); } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + uint32_t ap =3D extract32(regime_rbar(env, + mmu_idx, secure)[matchregion], 1, 2); + uint32_t xn =3D extract32(regime_rbar(env, + mmu_idx, secure)[matchregion], 0, 1); bool pxn =3D false; =20 if (arm_feature(env, ARM_FEATURE_V8_1M)) { - pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + pxn =3D extract32(regime_rlar(env, + mmu_idx, secure)[matchregion], 4, 1); } =20 if (m_is_system_region(env, address)) { @@ -1822,14 +1916,42 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, xn =3D 1; } =20 - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + *prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_E2); + } else { + *prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_Sta= ge1_E1); + } + + if (regime_sctlr(env, mmu_idx) & SCTLR_WXN + && (*prot & PAGE_WRITE)) { + xn =3D 0x1; + } + + if ((regime_el(env, mmu_idx) =3D=3D 1) && regime_sctlr(env, mm= u_idx) + & SCTLR_UWXN && (ap =3D=3D 0x1)) { + xn =3D 0x1; + } + + uint8_t attrindx =3D extract32(regime_rlar(env, + mmu_idx, secure)[matchregion], 1,= 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + uint8_t sh =3D extract32(regime_rlar(env, + mmu_idx, secure)[matchregion], 3, 2); + assert(attrindx <=3D 4); + cacheattrs->is_s2_format =3D false; + cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + cacheattrs->shareability =3D sh; + } else { + *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + } + if (*prot && !xn && !(pxn && !is_user)) { *prot |=3D PAGE_EXEC; } - /* - * We don't need to look the attribute up in the MAIR0/MAIR1 - * registers because that only tells us about cacheability. - */ + if (mregion) { *mregion =3D matchregion; } @@ -2342,9 +2464,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; =20 /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, - phys_ptr, attrs, &s2_prot, - page_size, fi, &cacheattrs2); + if (arm_feature(env, ARM_FEATURE_V8_R)) { + ret =3D get_phys_addr_pmsav8(env, ipa, access_type, s2_mmu= _idx, + phys_ptr, attrs, &s2_prot, page_siz= e, + fi, &cacheattrs2); + } else { + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_i= dx, + is_el0, phys_ptr, attrs, &s2_prot, + page_size, fi, &cacheattrs2); + } + fi->s2addr =3D ipa; /* Combine the S1 and S2 perms. */ *prot &=3D s2_prot; --=20 2.25.1 From nobody Mon Feb 9 18:33:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1658145632; cv=none; d=zohomail.com; s=zohoarc; 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Mon, 18 Jul 2022 04:55:01 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Jul 2022 04:55:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658145304; x=1689681304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=62lc4Ir3nkRJibiUY86ZsR1EcD5JRu+YdTFKmQCKGNE=; b=o3c9s/SBcwbwO9LiYZSHC538Wl9jcvAsczQTBLRh2i42WdS84YtxhTqm 4O5xBLYDGG0bwNSbO0OuRorbsJ8vUMOzOD00A/aW+rAfXlo6a782uRL1x 9ws/GFj9kYY13zA+BSBvpGrVtsqKMGEjc2PgeIXEj0W57VoLpA/WzPFZ7 w=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH v2 9/9] target/arm: Add ARM Cortex-R52 cpu Date: Mon, 18 Jul 2022 13:54:33 +0200 Message-ID: <20220718115433.802-10-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718115433.802-1-quic_trohmel@quicinc.com> References: <20220718115433.802-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1658145635136100001 From: Tobias R=C3=B6hmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b751a19c8a..e0f445dc91 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -843,6 +843,47 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 +static void cortex_r52_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_R); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + cpu->midr =3D 0x411fd133; /* r1p3 */ + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034023; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8144c004; + cpu->reset_sctlr =3D 0x30c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x10111001; + cpu->isar.id_dfr0 =3D 0x03010006; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00211040; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0xf0102211; + cpu->isar.id_mmfr4 =3D 0x00000010; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232142; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x00010001; + cpu->isar.dbgdidr =3D 0x77168000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + + cpu->pmsav7_dregion =3D 16; +} + static void cortex_r5f_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1149,6 +1190,7 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, + { .name =3D "cortex-r52", .initfn =3D cortex_r52_initfn }, { .name =3D "ti925t", .initfn =3D ti925t_initfn }, { .name =3D "sa1100", .initfn =3D sa1100_initfn }, { .name =3D "sa1110", .initfn =3D sa1110_initfn }, --=20 2.25.1