From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657905493; cv=none; d=zohomail.com; s=zohoarc; b=AoWJiLyY//Zhn2M7xXaWRSJ6feuqFO+ruc6HNjGSzKbKzX3wF8BV/B8z26pKBdYbl7p6Qdu1/l+rfnKRsgTOsyO8Qw3o2SQ15bFFUNoJm/DDsbzhj+IjdhWAG1Jld5qHv/xakC0tWon1/rxU53ND0n/InJBLk3eLmmf7+Ryw62c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657905493; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=sq9FFb5aE+/IiMlVeguENCUMCQ8VCOnFTO/apdVoO2I=; b=eMtuM7Kq3Uu9jUxvE/JwUUD/9rJsHxHcGFakNVNm+Kkn6+7JLpQ4Yn+rGjKGMy4KBppqlQmKlfA4Ozykve8EpyvZEQ+0hp+jMjON4aiTBghNRAfNd19jqVGuSXf5VG33UCjwOSATZ/AwNuwHzveLpYsOE+441Fuu0pgBb0r+mzA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657905493852584.5070369816932; Fri, 15 Jul 2022 10:18:13 -0700 (PDT) Received: from localhost ([::1]:36804 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oCOxA-0002MJ-7C for importer@patchew.org; Fri, 15 Jul 2022 13:18:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oCOw1-0000k1-Q2 for qemu-devel@nongnu.org; Fri, 15 Jul 2022 13:17:01 -0400 Received: from mx0b-00069f02.pphosted.com ([205.220.177.32]:57392) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oCOvy-0005aQ-I0 for qemu-devel@nongnu.org; Fri, 15 Jul 2022 13:17:01 -0400 Received: from pps.filterd (m0246631.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26FH4aXW030500; Fri, 15 Jul 2022 17:16:52 GMT Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.appoci.oracle.com [138.1.114.2]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3h71scgq7g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 15 Jul 2022 17:16:52 +0000 Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.16.1.2/8.16.1.2) with SMTP id 26FHBic0039730; Fri, 15 Jul 2022 17:16:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047tytb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 15 Jul 2022 17:16:51 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 26FHGjLv013789; Fri, 15 Jul 2022 17:16:50 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-181-254.vpn.oracle.com [10.175.181.254]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047tyn7-2; Fri, 15 Jul 2022 17:16:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=sq9FFb5aE+/IiMlVeguENCUMCQ8VCOnFTO/apdVoO2I=; b=xrh+vc7xaYLPO4wzz7LTToefVZHiZRgS6aUY/s68hYFoosx1Kw9LyPa681Vk5f4kFwDU uqNFfpm2aVKZdBg92CBVyI4zCEh0uupqdr8WEhU5QGSqapDoqwPOjggnSz7SFqBQOVFg ypYe01b9PHZCLqOPwTionomNCxaHBIba8Zekn1zoaV6TUs7Zmv7jEVdoHbMYVUy13ad2 JqDUUTL4Wyvr+P52KiENmHd99htm31LyeJka0DtRqD9j5Zurcr1YRPoVpjXaCw6A3+M5 GDEnyHPtkWSzUoOdB0HyBBPpbcVvh3sHVfX8/+BxiwBd/uyKHTOenvR2X7L0qECYEA7B /Q== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 01/11] hw/i386: add 4g boundary start to X86MachineState Date: Fri, 15 Jul 2022 18:16:18 +0100 Message-Id: <20220715171628.21437-2-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: auJS7FqJ-vBlAQVh2ixDSonXgobaGAxs X-Proofpoint-ORIG-GUID: auJS7FqJ-vBlAQVh2ixDSonXgobaGAxs Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905495355100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than hardcoding the 4G boundary everywhere, introduce a X86MachineState field @above_4g_mem_start and use it accordingly. This is in preparation for relocating ram-above-4g to be dynamically start at 1T on AMD platforms. Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/acpi-build.c | 2 +- hw/i386/pc.c | 11 ++++++----- hw/i386/sgx.c | 2 +- hw/i386/x86.c | 1 + include/hw/i386/x86.h | 3 +++ 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index cad6f5ac41e9..0355bd3ddaad 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2024,7 +2024,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) build_srat_memory(table_data, mem_base, mem_len, i - 1, MEM_AFFINITY_ENABLED); } - mem_base =3D 1ULL << 32; + mem_base =3D x86ms->above_4g_mem_start; mem_len =3D next_base - x86ms->below_4g_mem_size; next_base =3D mem_base + mem_len; } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8d68295fdaff..1660684d12fd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -850,9 +850,10 @@ void pc_memory_init(PCMachineState *pcms, machine->ram, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size); - memory_region_add_subregion(system_memory, 0x100000000ULL, + memory_region_add_subregion(system_memory, x86ms->above_4g_mem_sta= rt, ram_above_4g); - e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); + e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, + E820_RAM); } =20 if (pcms->sgx_epc.size !=3D 0) { @@ -893,7 +894,7 @@ void pc_memory_init(PCMachineState *pcms, machine->device_memory->base =3D sgx_epc_above_4g_end(&pcms->s= gx_epc); } else { machine->device_memory->base =3D - 0x100000000ULL + x86ms->above_4g_mem_size; + x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 machine->device_memory->base =3D @@ -927,7 +928,7 @@ void pc_memory_init(PCMachineState *pcms, } else if (pcms->sgx_epc.size !=3D 0) { cxl_base =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - cxl_base =3D 0x100000000ULL + x86ms->above_4g_mem_size; + cxl_base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; } =20 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); @@ -1035,7 +1036,7 @@ uint64_t pc_pci_hole64_start(void) } else if (pcms->sgx_epc.size !=3D 0) { hole64_start =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - hole64_start =3D 0x100000000ULL + x86ms->above_4g_mem_size; + hole64_start =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; } =20 return ROUND_UP(hole64_start, 1 * GiB); diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index a44d66ba2afc..09d9c7c73d9f 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) return; } =20 - sgx_epc->base =3D 0x100000000ULL + x86ms->above_4g_mem_size; + sgx_epc->base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; =20 memory_region_init(&sgx_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX); memory_region_add_subregion(get_system_memory(), sgx_epc->base, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 6003b4b2dfea..029264c54fe2 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -1373,6 +1373,7 @@ static void x86_machine_initfn(Object *obj) x86ms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); x86ms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); x86ms->bus_lock_ratelimit =3D 0; + x86ms->above_4g_mem_start =3D 4 * GiB; } =20 static void x86_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 9089bdd99c3a..df82c5fd4252 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -56,6 +56,9 @@ struct X86MachineState { /* RAM information (sizes, addresses, configuration): */ ram_addr_t below_4g_mem_size, above_4g_mem_size; =20 + /* Start address of the initial RAM above 4G */ + uint64_t above_4g_mem_start; + /* CPU and apic information: */ bool apic_xrupt_override; unsigned pci_irq_mask; --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657905496; cv=none; d=zohomail.com; s=zohoarc; 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h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=fRUaM6BoTCnpEt8yk7mTglXXc901MlgM1s5jUyNf8tE=; b=KV7NuDorSkehi3oCEKBcsrasbegqfdpvNissldPGHG7/SbXZRVBEpJTtgwz8VnfQ+0Cr wPh8XettJ4625x7flicwvctsuqK2bOcbPC2THaHu7sGr2Ph20bKKy98fXyobrUfRMD8G Uqw3GOos4eJK6RNdHrhqxz7tyC9ACfN9jQyO794zRBptmFmxE8dOh9wrBx5+4bCEriPU 0X/wMR3i36M2GDmkglu1+ox2gZpzrc+13p4nznQu9w8jWKolRKfaxIS1GQFJJ+CxG7I9 W5ErPNi75t8KQOaI2xg1FFUM1ImSv00AcMVRA6TdHzxJflxVBMDh0FDXj0zMSlUlcbmL tQ== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 02/11] i386/pc: create pci-host qdev prior to pc_memory_init() Date: Fri, 15 Jul 2022 18:16:19 +0100 Message-Id: <20220715171628.21437-3-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: OOwLGQRMX9vLh1m9KisSSVwv6hXuZQeM X-Proofpoint-GUID: OOwLGQRMX9vLh1m9KisSSVwv6hXuZQeM Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905497195100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the start of pc_memory_init() we usually pass a range of 0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or 32G (q35). To get the real user value, we need to get pci-host passed property for default pci_hole64_size. Thus to get that, create the qdev prior to memory init to better make estimations on max used/phys addr. This is in preparation to determine that host-phys-bits are enough and also for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/pc_piix.c | 7 +++++-- hw/i386/pc_q35.c | 6 +++--- hw/pci-host/i440fx.c | 5 ++--- include/hw/pci-host/i440fx.h | 3 ++- 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a234989ac363..6186a1473755 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *pci_memory; MemoryRegion *rom_memory; ram_addr_t lowmem; + DeviceState *i440fx_host; =20 /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -164,9 +165,11 @@ static void pc_init1(MachineState *machine, pci_memory =3D g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory =3D pci_memory; + i440fx_host =3D qdev_new(host_type); } else { pci_memory =3D NULL; rom_memory =3D system_memory; + i440fx_host =3D NULL; } =20 pc_guest_info_init(pcms); @@ -200,8 +203,8 @@ static void pc_init1(MachineState *machine, const char *type =3D xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; =20 - pci_bus =3D i440fx_init(host_type, - pci_type, + pci_bus =3D i440fx_init(pci_type, + i440fx_host, system_memory, system_io, machine->ram_size, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index f96cbd04e284..46ea89e564de 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -203,12 +203,12 @@ static void pc_q35_init(MachineState *machine) pcms->smbios_entry_point_type); } =20 - /* allocate ram and load rom/bios */ - pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); - /* create pci host bus */ q35_host =3D Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); =20 + /* allocate ram and load rom/bios */ + pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); + object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, OBJECT(ram_memory), NULL); diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 1c5ad5f918a2..d5426ef4a53c 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -237,7 +237,8 @@ static void i440fx_realize(PCIDevice *dev, Error **errp) } } =20 -PCIBus *i440fx_init(const char *host_type, const char *pci_type, +PCIBus *i440fx_init(const char *pci_type, + DeviceState *dev, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, @@ -246,7 +247,6 @@ PCIBus *i440fx_init(const char *host_type, const char *= pci_type, MemoryRegion *pci_address_space, MemoryRegion *ram_memory) { - DeviceState *dev; PCIBus *b; PCIDevice *d; PCIHostState *s; @@ -254,7 +254,6 @@ PCIBus *i440fx_init(const char *host_type, const char *= pci_type, unsigned i; I440FXState *i440fx; =20 - dev =3D qdev_new(host_type); s =3D PCI_HOST_BRIDGE(dev); b =3D pci_root_bus_new(dev, NULL, pci_address_space, address_space_io, 0, TYPE_PCI_BUS); diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index 52518dbf08e6..d02bf1ed6b93 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -35,7 +35,8 @@ struct PCII440FXState { =20 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" =20 -PCIBus *i440fx_init(const char *host_type, const char *pci_type, +PCIBus *i440fx_init(const char *pci_type, + DeviceState *dev, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=RyPoFbt3mAI749wa3ojwpKVtkxfRL5XMP85RSHN+/wg=; b=joipw7HJthWahL9eshYyuso3hZwbcANc3vIpIg4x6cc+srxg6J97DLLdPVH2pYyu0wKx zijnTS2DT1E46ikFSJwnrBguws+yCZRJkNm9R5NL4UKBKM7yX3/Be+IFiUA5P71aJh4a CR5qyHV4poyImEPkYdIAkpgvoEpLa873TuGSFtn9ofqCe/yF94wBGMNHu0LVbOfapb4a /GDZkxdB7fDdGZpE5AB+A3tTiaFN8CamEy2zkfy0oZNFbzPzptZSOkYiW8YHO8JiKg6A kumoRZNXbS5II6zpKBMTQVLsM7AIOtljjVca+OvzZmJJoeIpunMEL56+K92TvEWcUQnS qQ== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 03/11] i386/pc: pass pci_hole64_size to pc_memory_init() Date: Fri, 15 Jul 2022 18:16:20 +0100 Message-Id: <20220715171628.21437-4-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: xhCGEWEcXL_RuD8trJ7k6h00W0dYw78E X-Proofpoint-ORIG-GUID: xhCGEWEcXL_RuD8trJ7k6h00W0dYw78E Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905818294100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the pre-initialized pci-host qdev and fetch the pci-hole64-size into pc_memory_init() newly added argument. Use PCI_HOST_PROP_PCI_HOLE64_SIZE pci-host property for fetching pci-hole64-size. This is in preparation to determine that host-phys-bits are enough and for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 3 ++- hw/i386/pc_piix.c | 7 ++++++- hw/i386/pc_q35.c | 10 +++++++++- include/hw/i386/pc.h | 3 ++- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1660684d12fd..e952dc62a12e 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -817,7 +817,8 @@ void xen_load_linux(PCMachineState *pcms) void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, - MemoryRegion **ram_memory) + MemoryRegion **ram_memory, + uint64_t pci_hole64_size) { int linux_boot, i; MemoryRegion *option_rom_mr; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6186a1473755..2a483e8666b4 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *pci_memory; MemoryRegion *rom_memory; ram_addr_t lowmem; + uint64_t hole64_size; DeviceState *i440fx_host; =20 /* @@ -166,10 +167,14 @@ static void pc_init1(MachineState *machine, memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory =3D pci_memory; i440fx_host =3D qdev_new(host_type); + hole64_size =3D object_property_get_uint(OBJECT(i440fx_host), + PCI_HOST_PROP_PCI_HOLE64_SI= ZE, + &error_abort); } else { pci_memory =3D NULL; rom_memory =3D system_memory; i440fx_host =3D NULL; + hole64_size =3D 0; } =20 pc_guest_info_init(pcms); @@ -186,7 +191,7 @@ static void pc_init1(MachineState *machine, /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(pcms, system_memory, - rom_memory, &ram_memory); + rom_memory, &ram_memory, hole64_size); } else { pc_system_flash_cleanup_unused(pcms); if (machine->kernel_filename !=3D NULL) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 46ea89e564de..99ed75371c67 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -138,6 +138,7 @@ static void pc_q35_init(MachineState *machine) MachineClass *mc =3D MACHINE_GET_CLASS(machine); bool acpi_pcihp; bool keep_pci_slot_hpc; + uint64_t pci_hole64_size =3D 0; =20 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping @@ -206,8 +207,15 @@ static void pc_q35_init(MachineState *machine) /* create pci host bus */ q35_host =3D Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); =20 + if (pcmc->pci_enabled) { + pci_hole64_size =3D object_property_get_uint(OBJECT(q35_host), + PCI_HOST_PROP_PCI_HOLE6= 4_SIZE, + &error_abort); + } + /* allocate ram and load rom/bios */ - pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); + pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, + pci_hole64_size); =20 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index b7735dccfc81..568c226d3034 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -159,7 +159,8 @@ void xen_load_linux(PCMachineState *pcms); void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, - MemoryRegion **ram_memory); + MemoryRegion **ram_memory, + uint64_t pci_hole64_size); uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 15 Jul 2022 17:17:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=jJoSn1HmBEMdNOoauqZixXNzsONSuXugygiibVftDf4=; b=vYLJcXgQ9aWcIxVPa+VsdHkwJ9/4DecDD77MhfALnJPrgsPzRVt/ts7XXVNfuxVtbnoK sd23nm7CvD8BvJmcGhcEfVEXYzE2EhbCXbc0oaJOFJyMhpZvSH65jD1gQ5kjUKQ+jzLo AE2EjmpkOMF6mxL2Ov5biZjYTqebtAeUTRjYGbA8W6VyqX7KH9lX9TvnA8324ruJh45r Rxjngb/C26vrs6AOcoMWsOLvmBuzlg8HZbFly2cT0i2M8UyQpkMr865ibLStBFhSJfZU WSczcNnGp9+8JZLD82vWlycMpbDKfk9rZAUXrFJu3346vWvy2BP6X4tFM06D81gJiEmm hw== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 04/11] i386/pc: factor out above-4g end to an helper Date: Fri, 15 Jul 2022 18:16:21 +0100 Message-Id: <20220715171628.21437-5-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: yrLbYA_4qkGmWAgXjix2_i1lx8fh0jnR X-Proofpoint-ORIG-GUID: yrLbYA_4qkGmWAgXjix2_i1lx8fh0jnR Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905675388100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There's a couple of places that seem to duplicate this calculation of RAM size above the 4G boundary. Move all those to a helper function. Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e952dc62a12e..216e38da938e 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -814,6 +814,17 @@ void xen_load_linux(PCMachineState *pcms) #define PC_ROM_ALIGN 0x800 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) =20 +static hwaddr pc_above_4g_end(PCMachineState *pcms) +{ + X86MachineState *x86ms =3D X86_MACHINE(pcms); + + if (pcms->sgx_epc.size !=3D 0) { + return sgx_epc_above_4g_end(&pcms->sgx_epc); + } + + return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -891,15 +902,8 @@ void pc_memory_init(PCMachineState *pcms, exit(EXIT_FAILURE); } =20 - if (pcms->sgx_epc.size !=3D 0) { - machine->device_memory->base =3D sgx_epc_above_4g_end(&pcms->s= gx_epc); - } else { - machine->device_memory->base =3D - x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; - } - machine->device_memory->base =3D - ROUND_UP(machine->device_memory->base, 1 * GiB); + ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); =20 if (pcmc->enforce_aligned_dimm) { /* size device region assuming 1G page max alignment per slot = */ @@ -929,7 +933,7 @@ void pc_memory_init(PCMachineState *pcms, } else if (pcms->sgx_epc.size !=3D 0) { cxl_base =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - cxl_base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; + cxl_base =3D pc_above_4g_end(pcms); } =20 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); @@ -1016,7 +1020,6 @@ uint64_t pc_pci_hole64_start(void) PCMachineState *pcms =3D PC_MACHINE(qdev_get_machine()); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *ms =3D MACHINE(pcms); - X86MachineState *x86ms =3D X86_MACHINE(pcms); uint64_t hole64_start =3D 0; =20 if (pcms->cxl_devices_state.host_mr.addr) { @@ -1034,10 +1037,8 @@ uint64_t pc_pci_hole64_start(void) if (!pcmc->broken_reserved_end) { hole64_start +=3D memory_region_size(&ms->device_memory->mr); } - } else if (pcms->sgx_epc.size !=3D 0) { - hole64_start =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - hole64_start =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; + hole64_start =3D pc_above_4g_end(pcms); } =20 return ROUND_UP(hole64_start, 1 * GiB); --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657905814; cv=none; d=zohomail.com; s=zohoarc; b=dIQkuzFbv0sqvZJUorqk2Js8O0RJ/XDmhQkZ0hiSCv3XIQX7qbtmo9xw37nBGSDxuJ7C0V9a6bA/ivB0qbRGqAB9D3xL5XQMz2AYLLXjBwx3VMUuU28aFCqqYUuJX5IHZdTGLt3jOZnTMGMTRO8qShPDsOgyrHxoEA0H1StskUk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657905814; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Fri, 15 Jul 2022 17:17:05 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 26FHGjM5013789; Fri, 15 Jul 2022 17:17:05 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-181-254.vpn.oracle.com [10.175.181.254]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047tyn7-6; Fri, 15 Jul 2022 17:17:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=hq5mJURNPywV3PpDv35HVSjIBFNdwdX9ZcaGHJwDSZE=; b=w29QE6LCAQW0RlP6lfIP00Hch6xfD4sQR8BQgJGzJpcGTqlNJtSjUx6yHwnkEU23eGLQ ZM3FZOIzHlx6Ri10YDcQHyVfa225Am9s4sFmTTskdzKDWx2YlcyVUVATFA9w3aNclPUo Z9YOtKgOPgfc05W01P25Y1gCYzdn5gCWTnUi08SY4GCca/K2yXNbr38ZcGMdVAVIKcA/ D16BblpDoKXdpc2deEA/Wlm95QKRIECYeGPdSVJbuZEKCAU97aa4AEntTk+/O3CEPcPl iE/dyXAz5zO/IXnJI2RDXjEgeqbcxt3amQGjigifOFsmHw4f40iM12Hhj7gSnyjaZc+W Nw== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v8 05/11] i386/pc: factor out cxl range end to helper Date: Fri, 15 Jul 2022 18:16:22 +0100 Message-Id: <20220715171628.21437-6-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: BFIqLF93EtBLFlP4pJnGauA_jwHZJLfk X-Proofpoint-GUID: BFIqLF93EtBLFlP4pJnGauA_jwHZJLfk Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905816168100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move calculation of CXL memory region end to separate helper. This is in preparation to a future change that removes CXL range dependency on the CXL memory region, with the goal of allowing pc_pci_hole64_start() to be called before any memory region are initialized. Cc: Jonathan Cameron Signed-off-by: Joao Martins Acked-by: Igor Mammedov --- hw/i386/pc.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 216e38da938e..1f42f194d7b7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -825,6 +825,25 @@ static hwaddr pc_above_4g_end(PCMachineState *pcms) return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 +static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) +{ + uint64_t start =3D 0; + + if (pcms->cxl_devices_state.host_mr.addr) { + start =3D pcms->cxl_devices_state.host_mr.addr + + memory_region_size(&pcms->cxl_devices_state.host_mr); + if (pcms->cxl_devices_state.fixed_windows) { + GList *it; + for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { + CXLFixedWindow *fw =3D it->data; + start =3D fw->mr.addr + memory_region_size(&fw->mr); + } + } + } + + return start; +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -1022,16 +1041,8 @@ uint64_t pc_pci_hole64_start(void) MachineState *ms =3D MACHINE(pcms); uint64_t hole64_start =3D 0; =20 - if (pcms->cxl_devices_state.host_mr.addr) { - hole64_start =3D pcms->cxl_devices_state.host_mr.addr + - memory_region_size(&pcms->cxl_devices_state.host_mr); - if (pcms->cxl_devices_state.fixed_windows) { - GList *it; - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { - CXLFixedWindow *fw =3D it->data; - hole64_start =3D fw->mr.addr + memory_region_size(&fw->mr); - } - } + if (pcms->cxl_devices_state.is_enabled) { + hole64_start =3D pc_get_cxl_range_end(pcms); } else if (pcmc->has_reserved_memory && ms->device_memory->base) { hole64_start =3D ms->device_memory->base; if (!pcmc->broken_reserved_end) { --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; 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h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=dZJg5Qqp7i7DCTW/Km8ltqv0w9oagbAspbdK2T1L0Hs=; b=PcoGp9nmoXJ4X6iQfgu85a9hIidwORsGPz4oBZu9hvs4fesT3KJF2By2gi8JxqBZL/Wj BXoJj87WQHHPcOZyQxyTUwe50udgRxGZkZbmjxrABtulFgwCRuWMYOkuPBDwRsd7iNHN QS7ZBLyHXJ18jy/tVcqY4EVq3ZF+/xvDhfvdSf3L0787Jw3nVlxWWRKSP9xQlQ0QBkKt KqKmebuyRUVuibzOceZkq/qGEi7FifiUr4TTX6NLsmQORbxKx+cVbAGHn3N0/qv/b9qj X04hnaw2oppw1bg7reNhHAnAcG339f2twjFxOygipR0gBDpkqXMyBica+qxiZnFBMg4v Ng== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v8 06/11] i386/pc: factor out cxl range start to helper Date: Fri, 15 Jul 2022 18:16:23 +0100 Message-Id: <20220715171628.21437-7-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: Mz_3NnyeNYsFwTDlG2bTGjFd2lVvkpiW X-Proofpoint-ORIG-GUID: Mz_3NnyeNYsFwTDlG2bTGjFd2lVvkpiW Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905929352100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Factor out the calculation of the base address of the memory region. It will be used later on for the cxl range end counterpart calculation and as well in pc_memory_init() CXL memory region initialization, thus avoiding duplication. Cc: Jonathan Cameron Signed-off-by: Joao Martins Acked-by: Igor Mammedov --- hw/i386/pc.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1f42f194d7b7..3fdcab4bb4f3 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -825,6 +825,22 @@ static hwaddr pc_above_4g_end(PCMachineState *pcms) return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 +static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) +{ + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + MachineState *machine =3D MACHINE(pcms); + hwaddr cxl_base; + + if (pcmc->has_reserved_memory && machine->device_memory->base) { + cxl_base =3D machine->device_memory->base + + memory_region_size(&machine->device_memory->mr); + } else { + cxl_base =3D pc_above_4g_end(pcms); + } + + return cxl_base; +} + static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) { uint64_t start =3D 0; @@ -946,15 +962,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion *mr =3D &pcms->cxl_devices_state.host_mr; hwaddr cxl_size =3D MiB; =20 - if (pcmc->has_reserved_memory && machine->device_memory->base) { - cxl_base =3D machine->device_memory->base - + memory_region_size(&machine->device_memory->mr); - } else if (pcms->sgx_epc.size !=3D 0) { - cxl_base =3D sgx_epc_above_4g_end(&pcms->sgx_epc); - } else { - cxl_base =3D pc_above_4g_end(pcms); - } - + cxl_base =3D pc_get_cxl_range_start(pcms); e820_add_entry(cxl_base, cxl_size, E820_RESERVED); memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657906072; cv=none; d=zohomail.com; s=zohoarc; b=A8J9dkkzG/anXWhEUIgBrB2R9KWy4w1awyPEMJ/uBwtKtAHWH2lZ/z5p5gZD5nEZGbd+rbHxDTIoV1BlK0dCdV8hHnoalaDFT1LqmGxpSOSmMWjiA2/F+EhZlvh/iao0kVIkms9MNrvWrt/iSaBDMk+yvvoYcqGFGOQPm3qzXew= ARC-Message-Signature: i=1; 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Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v8 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_end() Date: Fri, 15 Jul 2022 18:16:24 +0100 Message-Id: <20220715171628.21437-8-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: nIazVngMdlciHBAoaWk_fUm40CBB4YJL X-Proofpoint-ORIG-GUID: nIazVngMdlciHBAoaWk_fUm40CBB4YJL Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657906074707100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove pc_get_cxl_range_end() dependency on the CXL memory region, and replace with one that does not require the CXL host_mr to determine the start of CXL start. This in preparation to allow pc_pci_hole64_start() to be called early in pc_memory_init(), handle CXL memory region end when its underlying memory region isn't yet initialized. Cc: Jonathan Cameron Signed-off-by: Joao Martins --- hw/i386/pc.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 3fdcab4bb4f3..c654be6cf0bd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -843,17 +843,15 @@ static uint64_t pc_get_cxl_range_start(PCMachineState= *pcms) =20 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) { - uint64_t start =3D 0; + uint64_t start =3D pc_get_cxl_range_start(pcms) + MiB; =20 - if (pcms->cxl_devices_state.host_mr.addr) { - start =3D pcms->cxl_devices_state.host_mr.addr + - memory_region_size(&pcms->cxl_devices_state.host_mr); - if (pcms->cxl_devices_state.fixed_windows) { - GList *it; - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { - CXLFixedWindow *fw =3D it->data; - start =3D fw->mr.addr + memory_region_size(&fw->mr); - } + if (pcms->cxl_devices_state.fixed_windows) { + GList *it; + + start =3D ROUND_UP(start, 256 * MiB); + for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D it->= next) { + CXLFixedWindow *fw =3D it->data; + start +=3D fw->size; } } =20 --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657905539; cv=none; d=zohomail.com; s=zohoarc; b=oHe03m/1RaTXM89UwnsKAXCAr7bAB+RNn4GQFPFPUkofMySRjt+eRUZr69KGGgyFAVRcKs6leVBG/x5nKyEG1HgIoEBISXfqhACvwMjRzMVzzk246oguKyGjKTabRbXWQYG57xyhZlBZ0sgs+UDDVfh4IFRGpQyQkglnF/tc3Ug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657905539; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=FIBpiDX4j9bmOfAGrzs/qcReNbLF1JTIooWk6DwGGY0=; b=Ee13Q8/rHl+6YJCJYHmricZO5648BRgiaqZH6JOsy/PO5Zau4dzCkucnALq7xHFXp3EYJvYGHf6hfPok7LSkGrsspMcbSJaZlLOD0ndtWbEbpuJq47PD8gcNocWFm3wSiyV9AMFMcDlEJhhvYexjq5Y40CMjqe5LQ+LICeVnKwk= ARC-Authentication-Results: i=1; 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Fri, 15 Jul 2022 17:17:17 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-181-254.vpn.oracle.com [10.175.181.254]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047tyn7-9; Fri, 15 Jul 2022 17:17:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=FIBpiDX4j9bmOfAGrzs/qcReNbLF1JTIooWk6DwGGY0=; b=QR9Tu2S7PqfX8cBUMywLlqnPseUTfE/zYBQsX6Gjm3/Ug1Z6Af2yP7KxuGyNKBHqzIK6 8sMR2qnZ7JJbQUMLdsG7QORsJW3eAuUTi0Z0w+o41aMnWH9NSoDm89wGLbXgeeXQRTup 1FKa4CT1X+Mi0VFCYyV3FwNhGqmOsu02AkTwxbRBZdbrdg8Y/cVrW/Lbqzt6D++SF7Fs 0T6/GvfDQu1vXDOSjgZb4Qg62aYzOrmhrpeqzoEMGCf4mcFLfz1bzttIvaq3QUvO/U2S VPU4C+Fxui46DbjKwJjTWILGiBQlf9amTpSwp8TVdjg0ypg4zDzb5RAyNpLGlaPttQ2m Vw== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v8 08/11] i386/pc: factor out device_memory base/size to helper Date: Fri, 15 Jul 2022 18:16:25 +0100 Message-Id: <20220715171628.21437-9-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: w_hWTw9prErpAD_2dgiteg6ORgsyKDeL X-Proofpoint-ORIG-GUID: w_hWTw9prErpAD_2dgiteg6ORgsyKDeL Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905541606100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move obtaining hole64_start from device_memory memory region base/size into an helper alongside correspondent getters in pc_memory_init() when the hotplug range is unitialized. While doing that remove the memory region based logic from this newly added helper. This is the final step that allows pc_pci_hole64_start() to be callable at the beginning of pc_memory_init() before any memory regions are initialized. Cc: Jonathan Cameron Signed-off-by: Joao Martins Acked-by: Igor Mammedov --- hw/i386/pc.c | 47 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c654be6cf0bd..cda435e3baeb 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -825,15 +825,37 @@ static hwaddr pc_above_4g_end(PCMachineState *pcms) return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 -static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) +static void pc_get_device_memory_range(PCMachineState *pcms, + hwaddr *base, + ram_addr_t *device_mem_size) { PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *machine =3D MACHINE(pcms); + ram_addr_t size; + hwaddr addr; + + size =3D machine->maxram_size - machine->ram_size; + addr =3D ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); + + if (pcmc->enforce_aligned_dimm) { + /* size device region assuming 1G page max alignment per slot */ + size +=3D (1 * GiB) * machine->ram_slots; + } + + *base =3D addr; + *device_mem_size =3D size; +} + + +static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) +{ + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); hwaddr cxl_base; + ram_addr_t size; =20 - if (pcmc->has_reserved_memory && machine->device_memory->base) { - cxl_base =3D machine->device_memory->base - + memory_region_size(&machine->device_memory->mr); + if (pcmc->has_reserved_memory) { + pc_get_device_memory_range(pcms, &cxl_base, &size); + cxl_base +=3D size; } else { cxl_base =3D pc_above_4g_end(pcms); } @@ -920,7 +942,7 @@ void pc_memory_init(PCMachineState *pcms, /* initialize device memory address space */ if (pcmc->has_reserved_memory && (machine->ram_size < machine->maxram_size)) { - ram_addr_t device_mem_size =3D machine->maxram_size - machine->ram= _size; + ram_addr_t device_mem_size; =20 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { error_report("unsupported amount of memory slots: %"PRIu64, @@ -935,13 +957,7 @@ void pc_memory_init(PCMachineState *pcms, exit(EXIT_FAILURE); } =20 - machine->device_memory->base =3D - ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); - - if (pcmc->enforce_aligned_dimm) { - /* size device region assuming 1G page max alignment per slot = */ - device_mem_size +=3D (1 * GiB) * machine->ram_slots; - } + pc_get_device_memory_range(pcms, &machine->device_memory->base, &d= evice_mem_size); =20 if ((machine->device_memory->base + device_mem_size) < device_mem_size) { @@ -1046,13 +1062,14 @@ uint64_t pc_pci_hole64_start(void) PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *ms =3D MACHINE(pcms); uint64_t hole64_start =3D 0; + ram_addr_t size =3D 0; =20 if (pcms->cxl_devices_state.is_enabled) { hole64_start =3D pc_get_cxl_range_end(pcms); - } else if (pcmc->has_reserved_memory && ms->device_memory->base) { - hole64_start =3D ms->device_memory->base; + } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_siz= e)) { + pc_get_device_memory_range(pcms, &hole64_start, &size); if (!pcmc->broken_reserved_end) { - hole64_start +=3D memory_region_size(&ms->device_memory->mr); + hole64_start +=3D size; } } else { hole64_start =3D pc_above_4g_end(pcms); --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657906178; cv=none; d=zohomail.com; s=zohoarc; b=lUrn5q/gH6qz2kbUWn5uKMUEQzjI2REQ5D9tLULDTWx3u21qhkDwM4qVQMWcAWzyeHKQ2YTN8M69l++kWjYt4Ef+b+16LM1AT4DYFxTrS7ioKgqcSjTopY9C1TffutYhBq2j34AWdM7aRQ9CZKOXUP/kA29vDZZFD1YvMg7M+BY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657906178; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=G7PalnraylVxk05nfgQP4/7g3uVpFvuN5n3r6hLTvnE=; b=UgrfMh12EzvsNiv21ha7WRjIjqQ95R9HFpV5Pbj/A6Ss+U6AQ9b5atPJj3EZSKqpV6RbNf3DNQixUNbADjQI2mgJKRdWcw0zVp9BvFkEX1mX2TwFYneleoMkwhnoNbeJO4wwVIGjpRn4CwxU0qmmUIPpBU53PMTM9RidmGi3cNc= ARC-Authentication-Results: i=1; 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Fri, 15 Jul 2022 17:17:21 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-181-254.vpn.oracle.com [10.175.181.254]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047tyn7-10; Fri, 15 Jul 2022 17:17:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=G7PalnraylVxk05nfgQP4/7g3uVpFvuN5n3r6hLTvnE=; b=FMJnzgfy2IuvTXLHBATQYZLEmr5bROMNtKq5DJr7rMuDq94jGt+iBK5gb3iPH/D9hBmT UIDWlLKAuZEyimkCeXVpe6xXVQUDnYxfo6X10qvOkhhVfXpcR6U2LtbodfzCbiDR6d1Q +jDz5spoW0J/Mz7fdHtO+fwC/CK6D5/lAsYAFEBTp6oxjSC+TbJumqQzK70yz503Vo9i GVHmuuZjirEMijgyjn5Cu4oqUPG3xdfVGuMmWqzD9pFZk77ZJIqFLB/JDLnN5xPOkNlC VmvMERtUs5XaQP85GjlBscGJST3ZGtrr3h4L6fSAdo4/1jq83eq7cwTrg8EqvL90RZXH Pw== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 09/11] i386/pc: bounds check phys-bits against max used GPA Date: Fri, 15 Jul 2022 18:16:26 +0100 Message-Id: <20220715171628.21437-10-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: nj3oVewdC7vCUmUnnFYV9hB-hk0il34Q X-Proofpoint-ORIG-GUID: nj3oVewdC7vCUmUnnFYV9hB-hk0il34Q Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657906179517100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Calculate max *used* GPA against the CPU maximum possible address and error out if the former surprasses the latter. This ensures max used GPA is reacheable by configured phys-bits. Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough for the CPU to address 1Tb (0xff ffff ffff) or 1010G (0xfc ffff ffff) in AMD hosts with IOMMU. This is preparation for AMD guests with >1010G, where it will want relocate ram-above-4g to be after 1Tb instead of 4G. Signed-off-by: Joao Martins Acked-by: Igor Mammedov --- hw/i386/pc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index cda435e3baeb..f30661b7f1a2 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -880,6 +880,18 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *p= cms) return start; } =20 +static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_si= ze) +{ + X86CPU *cpu =3D X86_CPU(first_cpu); + + /* 32-bit systems don't have hole64 thus return max CPU address */ + if (cpu->phys_bits <=3D 32) { + return ((hwaddr)1 << cpu->phys_bits) - 1; + } + + return pc_pci_hole64_start() + pci_hole64_size - 1; +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -894,13 +906,28 @@ void pc_memory_init(PCMachineState *pcms, MachineClass *mc =3D MACHINE_GET_CLASS(machine); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms =3D X86_MACHINE(pcms); + hwaddr maxphysaddr, maxusedaddr; hwaddr cxl_base, cxl_resv_end =3D 0; + X86CPU *cpu =3D X86_CPU(first_cpu); =20 assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); =20 linux_boot =3D (machine->kernel_filename !=3D NULL); =20 + /* + * phys-bits is required to be appropriately configured + * to make sure max used GPA is reachable. + */ + maxusedaddr =3D pc_max_used_gpa(pcms, pci_hole64_size); + maxphysaddr =3D ((hwaddr)1 << cpu->phys_bits) - 1; + if (maxphysaddr < maxusedaddr) { + error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 + " phys-bits too low (%u)", + maxphysaddr, maxusedaddr, cpu->phys_bits); + exit(EXIT_FAILURE); + } + /* * Split single memory region and use aliases to address portions of i= t, * done for backwards compatibility with older qemus. --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=KZd3TtRmVnCZDQgAiTP7VwFbVts8moEpOPpkPyQqsxY=; b=lIakTsfa7Kn9doSyYrqVjB4De0PFZ990kqZIE0toQ0t6BBo9o4zUAbhf5+WBu3Xeu0Le VGgMTaqHgYYG94bL5cYmWPnQQncF2987tcsaVmAz1tt18c1e+j81kkWYTStbDS+ezQw9 QS4/gVrJGBeZMTqn/WLWznSSHBw3O+WHuQIQrImtvdoS4lYTCarF8Kk6ll54S4t37PRl v04woenP3Lz0vlmOf34uzeDQUsouhOsfYaaAZm3DVpX1qQcvMm8giz2hUrSNTckjW+wS HpPlDWBGeBqj7X2QcwMX90VsZA2AVgleG3oEJCK7rqoWPNORIS+UzL2IA/M0zfD1PGdo 8g== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 10/11] i386/pc: relocate 4g start to 1T where applicable Date: Fri, 15 Jul 2022 18:16:27 +0100 Message-Id: <20220715171628.21437-11-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: 1_6NpB9wGG2QCX0D0UGzLJj2VnswlAS_ X-Proofpoint-GUID: 1_6NpB9wGG2QCX0D0UGzLJj2VnswlAS_ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905765979100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It is assumed that the whole GPA space is available to be DMA addressable, within a given address space limit, except for a tiny region before the 4G. Since Linux v5.4, VFIO validates whether the selected GPA is indeed valid i.e. not reserved by IOMMU on behalf of some specific devices or platform-defined restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with -EINVAL. AMD systems with an IOMMU are examples of such platforms and particularly may only have these ranges as allowed: 0000000000000000 - 00000000fedfffff (0 .. 3.982G) 00000000fef00000 - 000000fcffffffff (3.983G .. 1011.9G) 0000010000000000 - ffffffffffffffff (1Tb .. 16Pb[*]) We already account for the 4G hole, albeit if the guest is big enough we will fail to allocate a guest with >1010G due to the ~12G hole at the 1Tb boundary, reserved for HyperTransport (HT). [*] there is another reserved region unrelated to HT that exists in the 256T boundary in Fam 17h according to Errata #1286, documeted also in "Open-Source Register Reference for AMD Family 17h Processors (PUB)" When creating the region above 4G, take into account that on AMD platforms the HyperTransport range is reserved and hence it cannot be used either as GPAs. On those cases rather than establishing the start of ram-above-4g to be 4G, relocate instead to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", for more information on the underlying restriction of IOVAs. After accounting for the 1Tb hole on AMD hosts, mtree should look like: 0000000000000000-000000007fffffff (prio 0, i/o): alias ram-below-4g @pc.ram 0000000000000000-000000007fffffff 0000010000000000-000001ff7fffffff (prio 0, i/o): alias ram-above-4g @pc.ram 0000000080000000-000000ffffffffff If the relocation is done or the address space covers it, we also add the the reserved HT e820 range as reserved. Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough to address 1Tb (0xff ffff ffff). On AMD platforms, if a ram-above-4g relocation is attempted and the CPU wasn't configured with a big enough phys-bits, an error message will be printed due to the maxphysaddr vs maxusedaddr check previously added. Suggested-by: Igor Mammedov Signed-off-by: Joao Martins Acked-by: Igor Mammedov --- hw/i386/pc.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f30661b7f1a2..a71135930833 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -892,6 +892,40 @@ static hwaddr pc_max_used_gpa(PCMachineState *pcms, ui= nt64_t pci_hole64_size) return pc_pci_hole64_start() + pci_hole64_size - 1; } =20 +/* + * AMD systems with an IOMMU have an additional hole close to the + * 1Tb, which are special GPAs that cannot be DMA mapped. Depending + * on kernel version, VFIO may or may not let you DMA map those ranges. + * Starting Linux v5.4 we validate it, and can't create guests on AMD mach= ines + * with certain memory sizes. It's also wrong to use those IOVA ranges + * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. + * The ranges reserved for Hyper-Transport are: + * + * FD_0000_0000h - FF_FFFF_FFFFh + * + * The ranges represent the following: + * + * Base Address Top Address Use + * + * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space + * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl + * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK + * FD_F910_0000h FD_F91F_FFFFh System Management + * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables + * FD_FB00_0000h FD_FBFF_FFFFh Address Translation + * FD_FC00_0000h FD_FDFF_FFFFh I/O Space + * FD_FE00_0000h FD_FFFF_FFFFh Configuration + * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages + * FE_2000_0000h FF_FFFF_FFFFh Reserved + * + * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", + * Table 3: Special Address Controls (GPA) for more information. + */ +#define AMD_HT_START 0xfd00000000UL +#define AMD_HT_END 0xffffffffffUL +#define AMD_ABOVE_1TB_START (AMD_HT_END + 1) +#define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -915,6 +949,26 @@ void pc_memory_init(PCMachineState *pcms, =20 linux_boot =3D (machine->kernel_filename !=3D NULL); =20 + /* + * The HyperTransport range close to the 1T boundary is unique to AMD + * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation + * to above 1T to AMD vCPUs only. + */ + if (IS_AMD_CPU(&cpu->env)) { + /* Bail out if max possible address does not cross HT range */ + if (pc_max_used_gpa(pcms, pci_hole64_size) >=3D AMD_HT_START) { + x86ms->above_4g_mem_start =3D AMD_ABOVE_1TB_START; + } + + /* + * Advertise the HT region if address space covers the reserved + * region or if we relocate. + */ + if (cpu->phys_bits >=3D 40) { + e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); + } + } + /* * phys-bits is required to be appropriately configured * to make sure max used GPA is reachable. --=20 2.17.2 From nobody Mon Feb 9 18:49:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1657905866; cv=none; d=zohomail.com; s=zohoarc; b=OWt2QHx4XHsVB5eF6gwF9VXZvPQl7Wf79aNPmTAowwlKjz9uAUufMehnR8B7DQH+oXOjqEOZRhEm+nFHDBk8lHbnYsAL/yI0834klbD42Y/dGF4CAb9StldN/W+qymVWuX8+jlc9CzmtqPMtEtmlpsOx9VRvGZSS6i98qxQavjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657905866; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=dwvUSa46J54EW39atyo5uGxXRyq38HrdAj16TV/I7c8=; b=OCO0/swgsxUcXwuoc9koep+gdxpUGZo6qCVrPz7kVey/sM1Px7lB08bJBPiwtGNjgu6qAKQRbYIV/ipRWuAzg69xkw9luDhtzaI5DTXEn59cDQgO40vLbbJMVhz0uMTZwuY++O/T9XjCyamAWbrYqiZABxEB+VVg9TzJu1thz8A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657905866522307.83289763691073; Fri, 15 Jul 2022 10:24:26 -0700 (PDT) Received: from localhost ([::1]:55580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oCP3B-0006cf-EC for importer@patchew.org; Fri, 15 Jul 2022 13:24:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oCOwb-0001r2-TM for qemu-devel@nongnu.org; Fri, 15 Jul 2022 13:17:37 -0400 Received: from mx0b-00069f02.pphosted.com ([205.220.177.32]:14296) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oCOwa-0005h0-1s for qemu-devel@nongnu.org; Fri, 15 Jul 2022 13:17:37 -0400 Received: from pps.filterd (m0246632.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26FH7Pb5002078; Fri, 15 Jul 2022 17:17:30 GMT Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.appoci.oracle.com [138.1.114.2]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3h71xrrj43-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 15 Jul 2022 17:17:30 +0000 Received: from pps.filterd (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (8.16.1.2/8.16.1.2) with SMTP id 26FHBiEC039710; Fri, 15 Jul 2022 17:17:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047u0fj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 15 Jul 2022 17:17:29 +0000 Received: from phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 26FHGjMH013789; Fri, 15 Jul 2022 17:17:28 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-181-254.vpn.oracle.com [10.175.181.254]) by phxpaimrmta01.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3h7047tyn7-12; Fri, 15 Jul 2022 17:17:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2022-7-12; bh=dwvUSa46J54EW39atyo5uGxXRyq38HrdAj16TV/I7c8=; b=lzXrHdAl3SAboHfwOJ80ynqzfFbEJaYzDoQagHL8SO9fKufmZym/wSmKjCyJhuJzm6cH AEnd5DXJKJhP2vnJ2AbOZFmTqc0Xh8ahZjhek2/O9d0zjGJmh6zDdaIgM8lRsbHbjjLv 9rjbHGCzp+udTvKBaePOnaUkm+46t2ObmxHcyZwWSXrOQR4ICIMy1gMS5K1bcDTtUL63 zem5M/z98PhPCms3U/h4AZQO/DqsJTeo1DwYRCrBBuWUntifTFS1raJ32B7CLMHaO4LY nkI6Vyxr0RsIL0sSEQHjQ2L1ERHgntaKKuV9hwqbgFfh+0yiJ1Cs7HB3hHQhnTeDGe/9 DQ== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v8 11/11] i386/pc: restrict AMD only enforcing of 1Tb hole to new machine type Date: Fri, 15 Jul 2022 18:16:28 +0100 Message-Id: <20220715171628.21437-12-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220715171628.21437-1-joao.m.martins@oracle.com> References: <20220715171628.21437-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: hqk856pan0YxMMBv2l3kYCyQr-XKpxMI X-Proofpoint-ORIG-GUID: hqk856pan0YxMMBv2l3kYCyQr-XKpxMI Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657905868702100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The added enforcing is only relevant in the case of AMD where the range right before the 1TB is restricted and cannot be DMA mapped by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST or possibly other kinds of IOMMU events in the AMD IOMMU. Although, there's a case where it may make sense to disable the IOVA relocation/validation when migrating from a non-amd-1tb-aware qemu to one that supports it. Relocating RAM regions to after the 1Tb hole has consequences for guest ABI because we are changing the memory mapping, so make sure that only new machine enforce but not older ones. Signed-off-by: Joao Martins Acked-by: Dr. David Alan Gilbert Acked-by: Igor Mammedov --- hw/i386/pc.c | 6 ++++-- hw/i386/pc_piix.c | 2 ++ hw/i386/pc_q35.c | 2 ++ include/hw/i386/pc.h | 1 + 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index a71135930833..c8d878cb8059 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -952,9 +952,10 @@ void pc_memory_init(PCMachineState *pcms, /* * The HyperTransport range close to the 1T boundary is unique to AMD * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation - * to above 1T to AMD vCPUs only. + * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false = in + * older machine types (<=3D 7.0) for compatibility purposes. */ - if (IS_AMD_CPU(&cpu->env)) { + if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { /* Bail out if max possible address does not cross HT range */ if (pc_max_used_gpa(pcms, pci_hole64_size) >=3D AMD_HT_START) { x86ms->above_4g_mem_start =3D AMD_ABOVE_1TB_START; @@ -1903,6 +1904,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) pcmc->has_reserved_memory =3D true; pcmc->kvmclock_enabled =3D true; pcmc->enforce_aligned_dimm =3D true; + pcmc->enforce_amd_1tb_hole =3D true; /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K rep= orted * to be used at the moment, 32K should be enough for a while. */ pcmc->acpi_data_size =3D 0x20000 + 0x8000; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 2a483e8666b4..074571bc03a8 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -446,9 +446,11 @@ DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1", NULL, =20 static void pc_i440fx_7_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_7_1_machine_options(m); m->alias =3D NULL; m->is_default =3D false; + pcmc->enforce_amd_1tb_hole =3D false; compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 99ed75371c67..f3aa4694a299 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -383,8 +383,10 @@ DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, =20 static void pc_q35_7_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_7_1_machine_options(m); m->alias =3D NULL; + pcmc->enforce_amd_1tb_hole =3D false; compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 568c226d3034..9cc3f5d33805 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -118,6 +118,7 @@ struct PCMachineClass { bool has_reserved_memory; bool enforce_aligned_dimm; bool broken_reserved_end; + bool enforce_amd_1tb_hole; =20 /* generate legacy CPU hotplug AML */ bool legacy_cpu_hotplug; --=20 2.17.2