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Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v7 01/10] hw/i386: add 4g boundary start to X86MachineState Date: Thu, 14 Jul 2022 19:28:11 +0100 Message-Id: <20220714182820.30970-2-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220714182820.30970-1-joao.m.martins@oracle.com> References: <20220714182820.30970-1-joao.m.martins@oracle.com> X-Proofpoint-GUID: oXm1b7mXJPFVfnKMIJU8NoEn8sKbz3UH X-Proofpoint-ORIG-GUID: oXm1b7mXJPFVfnKMIJU8NoEn8sKbz3UH Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1657824409272100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than hardcoding the 4G boundary everywhere, introduce a X86MachineState field @above_4g_mem_start and use it accordingly. This is in preparation for relocating ram-above-4g to be dynamically start at 1T on AMD platforms. Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/acpi-build.c | 2 +- hw/i386/pc.c | 11 ++++++----- hw/i386/sgx.c | 2 +- hw/i386/x86.c | 1 + include/hw/i386/x86.h | 3 +++ 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index cad6f5ac41e9..0355bd3ddaad 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2024,7 +2024,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) build_srat_memory(table_data, mem_base, mem_len, i - 1, MEM_AFFINITY_ENABLED); } - mem_base =3D 1ULL << 32; + mem_base =3D x86ms->above_4g_mem_start; mem_len =3D next_base - x86ms->below_4g_mem_size; next_base =3D mem_base + mem_len; } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8d68295fdaff..1660684d12fd 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -850,9 +850,10 @@ void pc_memory_init(PCMachineState *pcms, machine->ram, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size); - memory_region_add_subregion(system_memory, 0x100000000ULL, + memory_region_add_subregion(system_memory, x86ms->above_4g_mem_sta= rt, ram_above_4g); - e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); + e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, + E820_RAM); } =20 if (pcms->sgx_epc.size !=3D 0) { @@ -893,7 +894,7 @@ void pc_memory_init(PCMachineState *pcms, machine->device_memory->base =3D sgx_epc_above_4g_end(&pcms->s= gx_epc); } else { machine->device_memory->base =3D - 0x100000000ULL + x86ms->above_4g_mem_size; + x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 machine->device_memory->base =3D @@ -927,7 +928,7 @@ void pc_memory_init(PCMachineState *pcms, } else if (pcms->sgx_epc.size !=3D 0) { cxl_base =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - cxl_base =3D 0x100000000ULL + x86ms->above_4g_mem_size; + cxl_base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; } =20 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); @@ -1035,7 +1036,7 @@ uint64_t pc_pci_hole64_start(void) } else if (pcms->sgx_epc.size !=3D 0) { hole64_start =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - hole64_start =3D 0x100000000ULL + x86ms->above_4g_mem_size; + hole64_start =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; } =20 return ROUND_UP(hole64_start, 1 * GiB); diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index a44d66ba2afc..09d9c7c73d9f 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) return; } =20 - sgx_epc->base =3D 0x100000000ULL + x86ms->above_4g_mem_size; + sgx_epc->base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; =20 memory_region_init(&sgx_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX); memory_region_add_subregion(get_system_memory(), sgx_epc->base, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 6003b4b2dfea..029264c54fe2 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -1373,6 +1373,7 @@ static void x86_machine_initfn(Object *obj) x86ms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); x86ms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); x86ms->bus_lock_ratelimit =3D 0; + x86ms->above_4g_mem_start =3D 4 * GiB; } =20 static void x86_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 9089bdd99c3a..df82c5fd4252 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -56,6 +56,9 @@ struct X86MachineState { /* RAM information (sizes, addresses, configuration): */ ram_addr_t below_4g_mem_size, above_4g_mem_size; =20 + /* Start address of the initial RAM above 4G */ + uint64_t above_4g_mem_start; + /* CPU and apic information: */ bool apic_xrupt_override; unsigned pci_irq_mask; --=20 2.17.2