From nobody Wed Apr 9 12:43:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814173587673.9670300331517; Thu, 14 Jul 2022 08:56:13 -0700 (PDT) Received: from localhost ([::1]:55038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1CG-0006aq-Gn for importer@patchew.org; Thu, 14 Jul 2022 11:56:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11n-0005GJ-6O; Thu, 14 Jul 2022 11:45:23 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:58539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11k-0000Y1-Mf; Thu, 14 Jul 2022 11:45:22 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjB0zS2z4xvN; Fri, 15 Jul 2022 01:45:18 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJj82WHDz4xdJ; Fri, 15 Jul 2022 01:45:16 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/19] aspeed: Refactor UART init for multi-SoC machines Date: Thu, 14 Jul 2022 17:44:43 +0200 Message-Id: <20220714154456.2565189-7-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814175768100001 From: Peter Delevoryas This change moves the code that connects the SoC UART's to serial_hd's to the machine. It makes each UART a proper child member of the SoC, and then allows the machine to selectively initialize the chardev for each UART with a serial_hd. This should preserve backwards compatibility, but also allow multi-SoC boards to completely change the wiring of serial devices from the command line to specific SoC UART's. This also removes the uart-default property from the SoC, since the SoC doesn't need to know what UART is the "default" on the machine anymore. I tested this using the images and commands from the previous refactoring, and another test image for the ast1030: wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/f= uji.mtd wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/w= edge100.mtd wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35= -cl-2022.13.01/Y35BCL.elf Fuji uses UART1: qemu-system-arm -machine fuji-bmc \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -nographic ast2600-evb uses uart-default=3DUART5: qemu-system-arm -machine ast2600-evb \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -serial null -serial mon:stdio -display none Wedge100 uses UART3: qemu-system-arm -machine palmetto-bmc \ -drive file=3Dwedge100.mtd,format=3Draw,if=3Dmtd \ -serial null -serial null -serial null \ -serial mon:stdio -display none AST1030 EVB uses UART5: qemu-system-arm -machine ast1030-evb \ -kernel Y35BCL.elf -nographic Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices") Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-4-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 7 ++++-- hw/arm/aspeed.c | 22 +++++++++++++--- hw/arm/aspeed_ast10x0.c | 8 +++++- hw/arm/aspeed_ast2600.c | 8 +++++- hw/arm/aspeed_soc.c | 50 +++++++++++++++++++++++++------------ 5 files changed, 71 insertions(+), 24 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index e65926a667ee..68e907cd64bb 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -36,12 +36,14 @@ #include "hw/misc/aspeed_lpc.h" #include "hw/misc/unimp.h" #include "hw/misc/aspeed_peci.h" +#include "hw/char/serial.h" =20 #define ASPEED_SPIS_NUM 2 #define ASPEED_EHCIS_NUM 2 #define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 4 +#define ASPEED_UARTS_NUM 13 =20 struct AspeedSoCState { /*< private >*/ @@ -79,7 +81,7 @@ struct AspeedSoCState { AspeedSDHCIState emmc; AspeedLPCState lpc; AspeedPECIState peci; - uint32_t uart_default; + SerialMM uart[ASPEED_UARTS_NUM]; Clock *sysclk; UnimplementedDeviceState iomem; UnimplementedDeviceState video; @@ -175,7 +177,8 @@ enum { }; =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); -void aspeed_soc_uart_init(AspeedSoCState *s); +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr a= ddr); void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 33401871322c..6b37c3369e91 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -26,6 +26,7 @@ #include "qemu/error-report.h" #include "qemu/units.h" #include "hw/qdev-clock.h" +#include "sysemu/sysemu.h" =20 static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ @@ -301,6 +302,21 @@ static void sdhci_attach_drive(SDHCIState *sdhci, Driv= eInfo *dinfo) &error_fatal); } =20 +static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) +{ + AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); + AspeedSoCState *s =3D &bmc->soc; + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0)); + for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { + if (uart =3D=3D amc->uart_default) { + continue; + } + aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); + } +} + static void aspeed_machine_init(MachineState *machine) { AspeedMachineState *bmc =3D ASPEED_MACHINE(machine); @@ -346,8 +362,7 @@ static void aspeed_machine_init(MachineState *machine) object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", ASPEED_SCU_PROT_KEY, &error_abort); } - qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", - amc->uart_default); + connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); =20 aspeed_board_init_flashes(&bmc->soc.fmc, @@ -1383,8 +1398,7 @@ static void aspeed_minibmc_machine_init(MachineState = *machine) =20 object_property_set_link(OBJECT(&bmc->soc), "memory", OBJECT(get_system_memory()), &error_abort); - qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", - amc->uart_default); + connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); =20 aspeed_board_init_flashes(&bmc->soc.fmc, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 677699e54c0a..4d0b9b115f0d 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -144,6 +144,10 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); } =20 + for (i =3D 0; i < sc->uarts_num; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); + } + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); =20 @@ -255,7 +259,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 /* UART */ - aspeed_soc_uart_init(s); + if (!aspeed_soc_uart_realize(s, errp)) { + return; + } =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 64eb5a7b2600..aa2cd90bec17 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -214,6 +214,10 @@ static void aspeed_soc_ast2600_init(Object *obj) object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII= ); } =20 + for (i =3D 0; i < sc->uarts_num; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); + } + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); object_initialize_child(obj, "xdma", &s->xdma, typename); =20 @@ -386,7 +390,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ - aspeed_soc_uart_init(s); + if (!aspeed_soc_uart_realize(s, errp)) { + return; + } =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 0bb6a2f092c9..b05b9dd41602 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -208,6 +208,10 @@ static void aspeed_soc_init(Object *obj) TYPE_FTGMAC100); } =20 + for (i =3D 0; i < sc->uarts_num; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); + } + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); object_initialize_child(obj, "xdma", &s->xdma, typename); =20 @@ -315,7 +319,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ - aspeed_soc_uart_init(s); + if (!aspeed_soc_uart_realize(s, errp)) { + return; + } =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), @@ -482,8 +488,6 @@ static Property aspeed_soc_properties[] =3D { MemoryRegion *), DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, - ASPEED_DEV_UART5), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -573,23 +577,37 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int de= v) return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); } =20 -void aspeed_soc_uart_init(AspeedSoCState *s) +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - int i, uart; - - /* Attach an 8250 to the IO space as our UART */ - serial_mm_init(s->memory, sc->memmap[s->uart_default], 2, - aspeed_soc_get_irq(s, s->uart_default), 38400, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - for (i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart+= +) { - if (uart =3D=3D s->uart_default) { - uart++; + SerialMM *smm; + + for (int i =3D 0, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { + smm =3D &s->uart[i]; + + /* Chardev property is set by the machine. */ + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIA= N); + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { + return false; } - serial_mm_init(s->memory, sc->memmap[uart], 2, - aspeed_soc_get_irq(s, uart), 38400, - serial_hd(i), DEVICE_LITTLE_ENDIAN); + + sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, u= art)); + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); } + + return true; +} + +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) +{ + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + int i =3D dev - ASPEED_DEV_UART1; + + g_assert(0 <=3D i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } =20 /* --=20 2.35.3