From nobody Wed Apr 9 12:56:34 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814093545103.07541652196426; Thu, 14 Jul 2022 08:54:53 -0700 (PDT) Received: from localhost ([::1]:52144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1Ay-0004PF-Dw for importer@patchew.org; Thu, 14 Jul 2022 11:54:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11k-0005Ft-Kb; Thu, 14 Jul 2022 11:45:21 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:52145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11i-0000Xe-Bx; Thu, 14 Jul 2022 11:45:20 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJj762Jsz4xht; Fri, 15 Jul 2022 01:45:15 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJj55lV8z4xdJ; Fri, 15 Jul 2022 01:45:13 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/19] aspeed: Create SRAM name from first CPU index Date: Thu, 14 Jul 2022 17:44:42 +0200 Message-Id: <20220714154456.2565189-6-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814095171100001 From: Peter Delevoryas To support multiple SoC's running simultaneously, we need a unique name for each RAM region. DRAM is created by the machine, but SRAM is created by the SoC, since in hardware it is part of the SoC's internals. We need a way to uniquely identify each SRAM region though, for VM migration. Since each of the SoC's CPU's has an index which identifies it uniquely from other CPU's in the machine, we can use the index of any of the CPU's in the SoC to uniquely identify differentiate the SRAM name from other SoC SRAM's. In this change, I just elected to use the index of the first CPU in each SoC. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-3-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 5 ++++- hw/arm/aspeed_ast2600.c | 5 +++-- hw/arm/aspeed_soc.c | 5 +++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 33ef33177199..677699e54c0a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -159,6 +159,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) DeviceState *armv7m; Error *err =3D NULL; int i; + g_autofree char *sram_name =3D NULL; =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); @@ -183,7 +184,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); =20 /* Internal SRAM */ - memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &= err); + sram_name =3D g_strdup_printf("aspeed.sram.%d", + CPU(s->armv7m.cpu)->cpu_index); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err !=3D NULL) { error_propagate(errp, err); return; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3f0611ac11cd..64eb5a7b2600 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -276,6 +276,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); Error *err =3D NULL; qemu_irq irq; + g_autofree char *sram_name =3D NULL; =20 /* IO space */ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", @@ -335,8 +336,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) } =20 /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", - sc->sram_size, &err); + sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_i= ndex); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err) { error_propagate(errp, err); return; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 0f675e7fcdf5..0bb6a2f092c9 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -239,6 +239,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); Error *err =3D NULL; + g_autofree char *sram_name =3D NULL; =20 /* IO space */ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", @@ -259,8 +260,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) } =20 /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", - sc->sram_size, &err); + sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_i= ndex); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err) { error_propagate(errp, err); return; --=20 2.35.3