From nobody Wed Apr 9 13:05:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657815222027142.28751806131606; Thu, 14 Jul 2022 09:13:42 -0700 (PDT) Received: from localhost ([::1]:58268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1TA-0003RX-J4 for importer@patchew.org; Thu, 14 Jul 2022 12:13:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12I-0005Rn-KK; Thu, 14 Jul 2022 11:45:56 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:57841 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12D-0000uK-BU; Thu, 14 Jul 2022 11:45:53 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjk1VHPz4yTJ; Fri, 15 Jul 2022 01:45:46 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjg74M7z4xRC; Fri, 15 Jul 2022 01:45:43 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/19] hw/gpio/aspeed: Don't let guests modify input pins Date: Thu, 14 Jul 2022 17:44:55 +0200 Message-Id: <20220714154456.2565189-19-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657815223754100001 From: Peter Delevoryas Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin values, and the QOM property setter should only be permitted to modify input pins. This change also updates the gpio input pin test to match this expectation. Andrew suggested this particularly refactoring here: https://lore.kernel.org/qemu-devel/23523aa1-ba81-412b-92cc-8174faba3612= @www.fastmail.com/ Suggested-by: Andrew Jeffery Signed-off-by: Peter Delevoryas Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and = AST2500") Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220712023219.41065-3-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_gpio.c | 15 ++++++++------- tests/qtest/aspeed_gpio-test.c | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index a62a673857c2..1e267dd48203 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -268,7 +268,7 @@ static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s= , GPIOSets *regs) } =20 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, - uint32_t value) + uint32_t value, uint32_t mode_mask) { uint32_t input_mask =3D regs->input_mask; uint32_t direction =3D regs->direction; @@ -277,7 +277,8 @@ static void aspeed_gpio_update(AspeedGPIOState *s, GPIO= Sets *regs, uint32_t diff; int gpio; =20 - diff =3D old ^ new; + diff =3D (old ^ new); + diff &=3D mode_mask; if (diff) { for (gpio =3D 0; gpio < ASPEED_GPIOS_PER_SET; gpio++) { uint32_t mask =3D 1 << gpio; @@ -339,7 +340,7 @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *= s, uint32_t set_idx, value &=3D ~pin_mask; } =20 - aspeed_gpio_update(s, &s->sets[set_idx], value); + aspeed_gpio_update(s, &s->sets[set_idx], value, ~s->sets[set_idx].dire= ction); } =20 /* @@ -653,7 +654,7 @@ static void aspeed_gpio_write_index_mode(void *opaque, = hwaddr offset, reg_value =3D update_value_control_source(set, set->data_value, reg_value); set->data_read =3D reg_value; - aspeed_gpio_update(s, set, reg_value); + aspeed_gpio_update(s, set, reg_value, set->direction); return; case gpio_reg_idx_direction: reg_value =3D set->direction; @@ -753,7 +754,7 @@ static void aspeed_gpio_write_index_mode(void *opaque, = hwaddr offset, __func__, offset, data, reg_idx_type); return; } - aspeed_gpio_update(s, set, set->data_value); + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); return; } =20 @@ -799,7 +800,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, data &=3D props->output; data =3D update_value_control_source(set, set->data_value, data); set->data_read =3D data; - aspeed_gpio_update(s, set, data); + aspeed_gpio_update(s, set, data, set->direction); return; case gpio_reg_direction: /* @@ -875,7 +876,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, PRIx64"\n", __func__, offset); return; } - aspeed_gpio_update(s, set, set->data_value); + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); return; } =20 diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c index 8f524540998d..d38f51d71908 100644 --- a/tests/qtest/aspeed_gpio-test.c +++ b/tests/qtest/aspeed_gpio-test.c @@ -69,7 +69,7 @@ static void test_set_input_pins(const void *data) =20 qtest_writel(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE, 0x00000000); value =3D qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); - g_assert_cmphex(value, =3D=3D, 0x00000000); + g_assert_cmphex(value, =3D=3D, 0xffffffff); } =20 int main(int argc, char **argv) --=20 2.35.3