From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165781387944038.87644469278325; Thu, 14 Jul 2022 08:51:19 -0700 (PDT) Received: from localhost ([::1]:42790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC17W-0005lx-FC for importer@patchew.org; Thu, 14 Jul 2022 11:51:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11c-0005Eq-Rc; Thu, 14 Jul 2022 11:45:13 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:38425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11a-0000VZ-9t; Thu, 14 Jul 2022 11:45:12 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJhx4V5hz4xvN; Fri, 15 Jul 2022 01:45:05 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJhv00Jrz4xhp; Fri, 15 Jul 2022 01:45:02 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Joel Stanley , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/19] aspeed: sbc: Allow per-machine settings Date: Thu, 14 Jul 2022 17:44:38 +0200 Message-Id: <20220714154456.2565189-2-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813879938100001 From: Joel Stanley In order to correctly report secure boot running firmware the values of certain registers must be set. We don't yet have documentation from ASPEED on what they mean. The meaning is inferred from u-boot's use of them. Introduce properties so the settings can be configured per-machine. Reviewed-by: Peter Delevoryas Tested-by: Peter Delevoryas Signed-off-by: Joel Stanley Message-Id: <20220628154740.1117349-4-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_sbc.h | 13 +++++++++++ hw/misc/aspeed_sbc.c | 42 ++++++++++++++++++++++++++++++++++-- 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h index 67e43b53ecc3..405e6782b97a 100644 --- a/include/hw/misc/aspeed_sbc.h +++ b/include/hw/misc/aspeed_sbc.h @@ -17,9 +17,22 @@ OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPE= ED_SBC) =20 #define ASPEED_SBC_NR_REGS (0x93c >> 2) =20 +#define QSR_AES BIT(27) +#define QSR_RSA1024 (0x0 << 12) +#define QSR_RSA2048 (0x1 << 12) +#define QSR_RSA3072 (0x2 << 12) +#define QSR_RSA4096 (0x3 << 12) +#define QSR_SHA224 (0x0 << 10) +#define QSR_SHA256 (0x1 << 10) +#define QSR_SHA384 (0x2 << 10) +#define QSR_SHA512 (0x3 << 10) + struct AspeedSBCState { SysBusDevice parent; =20 + bool emmc_abr; + uint32_t signing_settings; + MemoryRegion iomem; =20 uint32_t regs[ASPEED_SBC_NR_REGS]; diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index bfa8b81d01c7..c6f328e3be23 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "hw/qdev-properties.h" #include "hw/misc/aspeed_sbc.h" #include "qapi/error.h" #include "migration/vmstate.h" @@ -19,6 +20,27 @@ #define R_STATUS (0x014 / 4) #define R_QSR (0x040 / 4) =20 +/* R_STATUS */ +#define ABR_EN BIT(14) /* Mirrors SCU510[11] */ +#define ABR_IMAGE_SOURCE BIT(13) +#define SPI_ABR_IMAGE_SOURCE BIT(12) +#define SB_CRYPTO_KEY_EXP_DONE BIT(11) +#define SB_CRYPTO_BUSY BIT(10) +#define OTP_WP_EN BIT(9) +#define OTP_ADDR_WP_EN BIT(8) +#define LOW_SEC_KEY_EN BIT(7) +#define SECURE_BOOT_EN BIT(6) +#define UART_BOOT_EN BIT(5) +/* bit 4 reserved*/ +#define OTP_CHARGE_PUMP_READY BIT(3) +#define OTP_IDLE BIT(2) +#define OTP_MEM_IDLE BIT(1) +#define OTP_COMPARE_STATUS BIT(0) + +/* QSR */ +#define QSR_RSA_MASK (0x3 << 12) +#define QSR_HASH_MASK (0x3 << 10) + static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedSBCState *s =3D ASPEED_SBC(opaque); @@ -80,8 +102,17 @@ static void aspeed_sbc_reset(DeviceState *dev) memset(s->regs, 0, sizeof(s->regs)); =20 /* Set secure boot enabled with RSA4096_SHA256 and enable eMMC ABR */ - s->regs[R_STATUS] =3D 0x000044C6; - s->regs[R_QSR] =3D 0x07C07C89; + s->regs[R_STATUS] =3D OTP_IDLE | OTP_MEM_IDLE; + + if (s->emmc_abr) { + s->regs[R_STATUS] &=3D ABR_EN; + } + + if (s->signing_settings) { + s->regs[R_STATUS] &=3D SECURE_BOOT_EN; + } + + s->regs[R_QSR] =3D s->signing_settings; } =20 static void aspeed_sbc_realize(DeviceState *dev, Error **errp) @@ -105,6 +136,12 @@ static const VMStateDescription vmstate_aspeed_sbc =3D= { } }; =20 +static Property aspeed_sbc_properties[] =3D { + DEFINE_PROP_BOOL("emmc-abr", AspeedSBCState, emmc_abr, 0), + DEFINE_PROP_UINT32("signing-settings", AspeedSBCState, signing_setting= s, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void aspeed_sbc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -112,6 +149,7 @@ static void aspeed_sbc_class_init(ObjectClass *klass, v= oid *data) dc->realize =3D aspeed_sbc_realize; dc->reset =3D aspeed_sbc_reset; dc->vmsd =3D &vmstate_aspeed_sbc; + device_class_set_props(dc, aspeed_sbc_properties); } =20 static const TypeInfo aspeed_sbc_info =3D { --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657813893555968.8419215041822; Thu, 14 Jul 2022 08:51:33 -0700 (PDT) Received: from localhost ([::1]:43620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC17k-0006KV-H5 for importer@patchew.org; Thu, 14 Jul 2022 11:51:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11f-0005FD-NW; Thu, 14 Jul 2022 11:45:17 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:36341 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11d-0000Vt-HU; Thu, 14 Jul 2022 11:45:14 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJj01rrQz4ySg; Fri, 15 Jul 2022 01:45:08 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJhy0w0hz4xj5; Fri, 15 Jul 2022 01:45:05 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , Titus Rwantare , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/19] hw/i2c/pmbus: Add idle state to return 0xff's Date: Thu, 14 Jul 2022 17:44:39 +0200 Message-Id: <20220714154456.2565189-3-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813894006100001 From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: Titus Rwantare Message-Id: <20220701000626.77395-2-me@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/i2c/pmbus_device.h | 7 +++++++ hw/i2c/pmbus_device.c | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 0f4d6b3fada0..93f5d57c9dc6 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -155,6 +155,7 @@ enum pmbus_registers { PMBUS_MFR_MAX_TEMP_1 =3D 0xC0, /* R/W word */ PMBUS_MFR_MAX_TEMP_2 =3D 0xC1, /* R/W word */ PMBUS_MFR_MAX_TEMP_3 =3D 0xC2, /* R/W word */ + PMBUS_IDLE_STATE =3D 0xFF, }; =20 /* STATUS_WORD */ @@ -527,6 +528,12 @@ int pmbus_page_config(PMBusDevice *pmdev, uint8_t page= _index, uint64_t flags); */ void pmbus_check_limits(PMBusDevice *pmdev); =20 +/** + * Enter an idle state where only the PMBUS_ERR_BYTE will be returned + * indefinitely until a new command is issued. + */ +void pmbus_idle(PMBusDevice *pmdev); + extern const VMStateDescription vmstate_pmbus_device; =20 #define VMSTATE_PMBUS_DEVICE(_field, _state) { \ diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 749a33af827b..4071a88cfcd1 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -261,6 +261,11 @@ void pmbus_check_limits(PMBusDevice *pmdev) } } =20 +void pmbus_idle(PMBusDevice *pmdev) +{ + pmdev->code =3D PMBUS_IDLE_STATE; +} + /* assert the status_cml error upon receipt of malformed command */ static void pmbus_cml_error(PMBusDevice *pmdev) { @@ -980,6 +985,10 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; =20 + case PMBUS_IDLE_STATE: + pmbus_send8(pmdev, PMBUS_ERR_BYTE); + break; + case PMBUS_CLEAR_FAULTS: /* Send Byte */ case PMBUS_PAGE_PLUS_WRITE: /* Block Write-only */ case PMBUS_STORE_DEFAULT_ALL: /* Send Byte */ --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657813717707982.6490549807556; Thu, 14 Jul 2022 08:48:37 -0700 (PDT) Received: from localhost ([::1]:35342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC14t-0000cb-NH for importer@patchew.org; Thu, 14 Jul 2022 11:48:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11f-0005FC-N9; Thu, 14 Jul 2022 11:45:17 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:34941) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11d-0000WH-6k; Thu, 14 Jul 2022 11:45:14 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJj25W9fz4xj5; Fri, 15 Jul 2022 01:45:10 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJj05R6Gz4yTH; Fri, 15 Jul 2022 01:45:08 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , Titus Rwantare , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/19] hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators Date: Thu, 14 Jul 2022 17:44:40 +0200 Message-Id: <20220714154456.2565189-4-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813718182100001 From: Peter Delevoryas This commit adds a passthrough for PMBUS_IC_DEVICE_ID to allow Renesas voltage regulators to return the integrated circuit device ID if they would like to. The behavior is very device specific, so it hasn't been added to the general PMBUS model. Additionally, if the device ID hasn't been set, then the voltage regulator will respond with the error byte value. The guest error message will change slightly for IC_DEVICE_ID with this commit. Signed-off-by: Peter Delevoryas Reviewed-by: Titus Rwantare Message-Id: <20220701000626.77395-3-me@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/sensor/isl_pmbus_vr.h | 5 +++++ hw/sensor/isl_pmbus_vr.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/hw/sensor/isl_pmbus_vr.h b/include/hw/sensor/isl_pmbus= _vr.h index 3e47ff7e48d8..aa2c2767df90 100644 --- a/include/hw/sensor/isl_pmbus_vr.h +++ b/include/hw/sensor/isl_pmbus_vr.h @@ -12,12 +12,17 @@ #include "hw/i2c/pmbus_device.h" #include "qom/object.h" =20 +#define TYPE_ISL69259 "isl69259" #define TYPE_ISL69260 "isl69260" #define TYPE_RAA228000 "raa228000" #define TYPE_RAA229004 "raa229004" +#define ISL_MAX_IC_DEVICE_ID_LEN 16 =20 struct ISLState { PMBusDevice parent; + + uint8_t ic_device_id[ISL_MAX_IC_DEVICE_ID_LEN]; + uint8_t ic_device_id_len; }; =20 OBJECT_DECLARE_SIMPLE_TYPE(ISLState, ISL69260) diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c index e11e0288840d..799ea9d89edb 100644 --- a/hw/sensor/isl_pmbus_vr.c +++ b/hw/sensor/isl_pmbus_vr.c @@ -15,6 +15,18 @@ =20 static uint8_t isl_pmbus_vr_read_byte(PMBusDevice *pmdev) { + ISLState *s =3D ISL69260(pmdev); + + switch (pmdev->code) { + case PMBUS_IC_DEVICE_ID: + if (!s->ic_device_id_len) { + break; + } + pmbus_send(pmdev, s->ic_device_id, s->ic_device_id_len); + pmbus_idle(pmdev); + return 0; + } + qemu_log_mask(LOG_GUEST_ERROR, "%s: reading from unsupported register: 0x%02x\n", __func__, pmdev->code); --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16578137514092.9523428625582255; Thu, 14 Jul 2022 08:49:11 -0700 (PDT) Received: from localhost ([::1]:37230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC15S-0001vW-D4 for importer@patchew.org; Thu, 14 Jul 2022 11:49:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11k-0005Fu-Km; Thu, 14 Jul 2022 11:45:21 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:33127) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11i-0000X3-24; Thu, 14 Jul 2022 11:45:19 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJj528hhz4xRC; Fri, 15 Jul 2022 01:45:13 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJj31zZNz4xdJ; Fri, 15 Jul 2022 01:45:11 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , Titus Rwantare , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 04/19] hw/sensor: Add Renesas ISL69259 device model Date: Thu, 14 Jul 2022 17:44:41 +0200 Message-Id: <20220714154456.2565189-5-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813752196100001 From: Peter Delevoryas This adds the ISL69259, using all the same functionality as the existing ISL69260 but overriding the IC_DEVICE_ID. Signed-off-by: Peter Delevoryas Reviewed-by: Titus Rwantare Message-Id: <20220701000626.77395-4-me@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/sensor/isl_pmbus_vr.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c index 799ea9d89edb..eb344dd5a9d5 100644 --- a/hw/sensor/isl_pmbus_vr.c +++ b/hw/sensor/isl_pmbus_vr.c @@ -119,6 +119,18 @@ static void raa228000_exit_reset(Object *obj) pmdev->pages[0].read_temperature_3 =3D 0; } =20 +static void isl69259_exit_reset(Object *obj) +{ + ISLState *s =3D ISL69260(obj); + static const uint8_t ic_device_id[] =3D {0x04, 0x00, 0x81, 0xD2, 0x49,= 0x3c}; + g_assert(sizeof(ic_device_id) <=3D sizeof(s->ic_device_id)); + + isl_pmbus_vr_exit_reset(obj); + + s->ic_device_id_len =3D sizeof(ic_device_id); + memcpy(s->ic_device_id, ic_device_id, sizeof(ic_device_id)); +} + static void isl_pmbus_vr_add_props(Object *obj, uint64_t *flags, uint8_t p= ages) { PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); @@ -257,6 +269,21 @@ static void raa229004_class_init(ObjectClass *klass, v= oid *data) isl_pmbus_vr_class_init(klass, data, 2); } =20 +static void isl69259_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->desc =3D "Renesas ISL69259 Digital Multiphase Voltage Regulator"; + rc->phases.exit =3D isl69259_exit_reset; + isl_pmbus_vr_class_init(klass, data, 2); +} + +static const TypeInfo isl69259_info =3D { + .name =3D TYPE_ISL69259, + .parent =3D TYPE_ISL69260, + .class_init =3D isl69259_class_init, +}; + static const TypeInfo isl69260_info =3D { .name =3D TYPE_ISL69260, .parent =3D TYPE_PMBUS_DEVICE, @@ -283,6 +310,7 @@ static const TypeInfo raa228000_info =3D { =20 static void isl_pmbus_vr_register_types(void) { + type_register_static(&isl69259_info); type_register_static(&isl69260_info); type_register_static(&raa228000_info); type_register_static(&raa229004_info); --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814093545103.07541652196426; Thu, 14 Jul 2022 08:54:53 -0700 (PDT) Received: from localhost ([::1]:52144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1Ay-0004PF-Dw for importer@patchew.org; Thu, 14 Jul 2022 11:54:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11k-0005Ft-Kb; Thu, 14 Jul 2022 11:45:21 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:52145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11i-0000Xe-Bx; Thu, 14 Jul 2022 11:45:20 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJj762Jsz4xht; Fri, 15 Jul 2022 01:45:15 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJj55lV8z4xdJ; Fri, 15 Jul 2022 01:45:13 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 05/19] aspeed: Create SRAM name from first CPU index Date: Thu, 14 Jul 2022 17:44:42 +0200 Message-Id: <20220714154456.2565189-6-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814095171100001 From: Peter Delevoryas To support multiple SoC's running simultaneously, we need a unique name for each RAM region. DRAM is created by the machine, but SRAM is created by the SoC, since in hardware it is part of the SoC's internals. We need a way to uniquely identify each SRAM region though, for VM migration. Since each of the SoC's CPU's has an index which identifies it uniquely from other CPU's in the machine, we can use the index of any of the CPU's in the SoC to uniquely identify differentiate the SRAM name from other SoC SRAM's. In this change, I just elected to use the index of the first CPU in each SoC. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-3-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 5 ++++- hw/arm/aspeed_ast2600.c | 5 +++-- hw/arm/aspeed_soc.c | 5 +++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 33ef33177199..677699e54c0a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -159,6 +159,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) DeviceState *armv7m; Error *err =3D NULL; int i; + g_autofree char *sram_name =3D NULL; =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); @@ -183,7 +184,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); =20 /* Internal SRAM */ - memory_region_init_ram(&s->sram, NULL, "aspeed.sram", sc->sram_size, &= err); + sram_name =3D g_strdup_printf("aspeed.sram.%d", + CPU(s->armv7m.cpu)->cpu_index); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err !=3D NULL) { error_propagate(errp, err); return; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3f0611ac11cd..64eb5a7b2600 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -276,6 +276,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); Error *err =3D NULL; qemu_irq irq; + g_autofree char *sram_name =3D NULL; =20 /* IO space */ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", @@ -335,8 +336,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) } =20 /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", - sc->sram_size, &err); + sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_i= ndex); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err) { error_propagate(errp, err); return; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 0f675e7fcdf5..0bb6a2f092c9 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -239,6 +239,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); Error *err =3D NULL; + g_autofree char *sram_name =3D NULL; =20 /* IO space */ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io= ", @@ -259,8 +260,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) } =20 /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", - sc->sram_size, &err); + sram_name =3D g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_i= ndex); + memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err) { error_propagate(errp, err); return; --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814173587673.9670300331517; Thu, 14 Jul 2022 08:56:13 -0700 (PDT) Received: from localhost ([::1]:55038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1CG-0006aq-Gn for importer@patchew.org; Thu, 14 Jul 2022 11:56:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11n-0005GJ-6O; Thu, 14 Jul 2022 11:45:23 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:58539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11k-0000Y1-Mf; Thu, 14 Jul 2022 11:45:22 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjB0zS2z4xvN; Fri, 15 Jul 2022 01:45:18 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJj82WHDz4xdJ; Fri, 15 Jul 2022 01:45:16 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/19] aspeed: Refactor UART init for multi-SoC machines Date: Thu, 14 Jul 2022 17:44:43 +0200 Message-Id: <20220714154456.2565189-7-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814175768100001 From: Peter Delevoryas This change moves the code that connects the SoC UART's to serial_hd's to the machine. It makes each UART a proper child member of the SoC, and then allows the machine to selectively initialize the chardev for each UART with a serial_hd. This should preserve backwards compatibility, but also allow multi-SoC boards to completely change the wiring of serial devices from the command line to specific SoC UART's. This also removes the uart-default property from the SoC, since the SoC doesn't need to know what UART is the "default" on the machine anymore. I tested this using the images and commands from the previous refactoring, and another test image for the ast1030: wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/f= uji.mtd wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/w= edge100.mtd wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35= -cl-2022.13.01/Y35BCL.elf Fuji uses UART1: qemu-system-arm -machine fuji-bmc \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -nographic ast2600-evb uses uart-default=3DUART5: qemu-system-arm -machine ast2600-evb \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -serial null -serial mon:stdio -display none Wedge100 uses UART3: qemu-system-arm -machine palmetto-bmc \ -drive file=3Dwedge100.mtd,format=3Draw,if=3Dmtd \ -serial null -serial null -serial null \ -serial mon:stdio -display none AST1030 EVB uses UART5: qemu-system-arm -machine ast1030-evb \ -kernel Y35BCL.elf -nographic Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices") Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-4-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 7 ++++-- hw/arm/aspeed.c | 22 +++++++++++++--- hw/arm/aspeed_ast10x0.c | 8 +++++- hw/arm/aspeed_ast2600.c | 8 +++++- hw/arm/aspeed_soc.c | 50 +++++++++++++++++++++++++------------ 5 files changed, 71 insertions(+), 24 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index e65926a667ee..68e907cd64bb 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -36,12 +36,14 @@ #include "hw/misc/aspeed_lpc.h" #include "hw/misc/unimp.h" #include "hw/misc/aspeed_peci.h" +#include "hw/char/serial.h" =20 #define ASPEED_SPIS_NUM 2 #define ASPEED_EHCIS_NUM 2 #define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 4 +#define ASPEED_UARTS_NUM 13 =20 struct AspeedSoCState { /*< private >*/ @@ -79,7 +81,7 @@ struct AspeedSoCState { AspeedSDHCIState emmc; AspeedLPCState lpc; AspeedPECIState peci; - uint32_t uart_default; + SerialMM uart[ASPEED_UARTS_NUM]; Clock *sysclk; UnimplementedDeviceState iomem; UnimplementedDeviceState video; @@ -175,7 +177,8 @@ enum { }; =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); -void aspeed_soc_uart_init(AspeedSoCState *s); +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr a= ddr); void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 33401871322c..6b37c3369e91 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -26,6 +26,7 @@ #include "qemu/error-report.h" #include "qemu/units.h" #include "hw/qdev-clock.h" +#include "sysemu/sysemu.h" =20 static struct arm_boot_info aspeed_board_binfo =3D { .board_id =3D -1, /* device-tree-only board */ @@ -301,6 +302,21 @@ static void sdhci_attach_drive(SDHCIState *sdhci, Driv= eInfo *dinfo) &error_fatal); } =20 +static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) +{ + AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); + AspeedSoCState *s =3D &bmc->soc; + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0)); + for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { + if (uart =3D=3D amc->uart_default) { + continue; + } + aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); + } +} + static void aspeed_machine_init(MachineState *machine) { AspeedMachineState *bmc =3D ASPEED_MACHINE(machine); @@ -346,8 +362,7 @@ static void aspeed_machine_init(MachineState *machine) object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", ASPEED_SCU_PROT_KEY, &error_abort); } - qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", - amc->uart_default); + connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); =20 aspeed_board_init_flashes(&bmc->soc.fmc, @@ -1383,8 +1398,7 @@ static void aspeed_minibmc_machine_init(MachineState = *machine) =20 object_property_set_link(OBJECT(&bmc->soc), "memory", OBJECT(get_system_memory()), &error_abort); - qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", - amc->uart_default); + connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); =20 aspeed_board_init_flashes(&bmc->soc.fmc, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 677699e54c0a..4d0b9b115f0d 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -144,6 +144,10 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); } =20 + for (i =3D 0; i < sc->uarts_num; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); + } + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); =20 @@ -255,7 +259,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 /* UART */ - aspeed_soc_uart_init(s); + if (!aspeed_soc_uart_realize(s, errp)) { + return; + } =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 64eb5a7b2600..aa2cd90bec17 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -214,6 +214,10 @@ static void aspeed_soc_ast2600_init(Object *obj) object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII= ); } =20 + for (i =3D 0; i < sc->uarts_num; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); + } + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); object_initialize_child(obj, "xdma", &s->xdma, typename); =20 @@ -386,7 +390,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ - aspeed_soc_uart_init(s); + if (!aspeed_soc_uart_realize(s, errp)) { + return; + } =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 0bb6a2f092c9..b05b9dd41602 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -208,6 +208,10 @@ static void aspeed_soc_init(Object *obj) TYPE_FTGMAC100); } =20 + for (i =3D 0; i < sc->uarts_num; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); + } + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); object_initialize_child(obj, "xdma", &s->xdma, typename); =20 @@ -315,7 +319,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 /* UART */ - aspeed_soc_uart_init(s); + if (!aspeed_soc_uart_realize(s, errp)) { + return; + } =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), @@ -482,8 +488,6 @@ static Property aspeed_soc_properties[] =3D { MemoryRegion *), DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, - ASPEED_DEV_UART5), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -573,23 +577,37 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int de= v) return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); } =20 -void aspeed_soc_uart_init(AspeedSoCState *s) +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - int i, uart; - - /* Attach an 8250 to the IO space as our UART */ - serial_mm_init(s->memory, sc->memmap[s->uart_default], 2, - aspeed_soc_get_irq(s, s->uart_default), 38400, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - for (i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart+= +) { - if (uart =3D=3D s->uart_default) { - uart++; + SerialMM *smm; + + for (int i =3D 0, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { + smm =3D &s->uart[i]; + + /* Chardev property is set by the machine. */ + qdev_prop_set_uint8(DEVICE(smm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400); + qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIA= N); + if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) { + return false; } - serial_mm_init(s->memory, sc->memmap[uart], 2, - aspeed_soc_get_irq(s, uart), 38400, - serial_hd(i), DEVICE_LITTLE_ENDIAN); + + sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, u= art)); + aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); } + + return true; +} + +void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr) +{ + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + int i =3D dev - ASPEED_DEV_UART1; + + g_assert(0 <=3D i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } =20 /* --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814308101607.2278092952604; Thu, 14 Jul 2022 08:58:28 -0700 (PDT) Received: from localhost ([::1]:33656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1ER-0003Rn-0i for importer@patchew.org; Thu, 14 Jul 2022 11:58:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11o-0005Hf-Cf; Thu, 14 Jul 2022 11:45:34 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:53745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11m-0000YK-P7; Thu, 14 Jul 2022 11:45:24 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjD2tvxz4ySg; Fri, 15 Jul 2022 01:45:20 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjB4X9rz4xdJ; Fri, 15 Jul 2022 01:45:18 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/19] aspeed: Make aspeed_board_init_flashes public Date: Thu, 14 Jul 2022 17:44:44 +0200 Message-Id: <20220714154456.2565189-8-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814308840100001 From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-5-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 68e907cd64bb..8389200b2d01 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -184,5 +184,7 @@ void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *d= ev, int n, hwaddr addr); void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, const char *name, hwaddr addr, uint64_t size); +void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, + unsigned int count, int unit0); =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 6b37c3369e91..60bc2e4cf9b0 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -262,7 +262,7 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr add= r, size_t rom_size, rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); } =20 -static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flash= type, +void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, unsigned int count, int unit0) { int i; --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165781370777516.812473094305005; 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Fri, 15 Jul 2022 01:45:20 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/19] aspeed: Add fby35 skeleton Date: Thu, 14 Jul 2022 17:44:45 +0200 Message-Id: <20220714154456.2565189-9-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813710066100003 From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-6-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/fby35.c | 39 +++++++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + hw/arm/meson.build | 3 ++- 3 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 hw/arm/fby35.c diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c new file mode 100644 index 000000000000..03b458584c26 --- /dev/null +++ b/hw/arm/fby35.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com) + * + * This code is licensed under the GPL version 2 or later. See the COPYING + * file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/boards.h" + +#define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") +OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); + +struct Fby35State { + MachineState parent_obj; +}; + +static void fby35_init(MachineState *machine) +{ +} + +static void fby35_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Meta Platforms fby35"; + mc->init =3D fby35_init; +} + +static const TypeInfo fby35_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("fby35"), + .parent =3D TYPE_MACHINE, + .class_init =3D fby35_class_init, + .instance_size =3D sizeof(Fby35State), + }, +}; + +DEFINE_TYPES(fby35_types); diff --git a/MAINTAINERS b/MAINTAINERS index 450abd025271..fce6161ce506 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1065,6 +1065,7 @@ F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h F: docs/system/arm/aspeed.rst F: tests/qtest/*aspeed* +F: hw/arm/fby35.c =20 NRF51 M: Joel Stanley diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 2d8381339c07..92f9f6e000ea 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -51,7 +51,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_soc.c', 'aspeed.c', 'aspeed_ast2600.c', - 'aspeed_ast10x0.c')) + 'aspeed_ast10x0.c', + 'fby35.c')) arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657813925862171.18368442657777; Thu, 14 Jul 2022 08:52:05 -0700 (PDT) Received: from localhost ([::1]:45142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC18G-0007Uo-J9 for importer@patchew.org; Thu, 14 Jul 2022 11:52:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC121-0005N3-44; Thu, 14 Jul 2022 11:45:38 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:58539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11r-0000Y1-VA; Thu, 14 Jul 2022 11:45:35 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjJ6Y3lz4xRC; Fri, 15 Jul 2022 01:45:24 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjH19r7z4xdJ; Fri, 15 Jul 2022 01:45:22 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/19] aspeed: Add AST2600 (BMC) to fby35 Date: Thu, 14 Jul 2022 17:44:46 +0200 Message-Id: <20220714154456.2565189-10-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813926270100001 From: Peter Delevoryas You can test booting the BMC with both '-device loader' and '-drive file'. This is necessary because of how the fb-openbmc boot sequence works (jump to 0x20000000 after U-Boot SPL). wget https://github.com/facebook/openbmc/releases/download/openbmc-e229= 4ff5d31d/fby35.mtd qemu-system-arm -machine fby35 -nographic \ -device loader,file=3Dfby35.mtd,addr=3D0,cpu-num=3D0 -drive file=3D= fby35.mtd,format=3Draw,if=3Dmtd Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-7-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/fby35.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index 03b458584c26..5c5224d37471 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -6,17 +6,55 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" #include "hw/boards.h" +#include "hw/arm/aspeed_soc.h" =20 #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); =20 struct Fby35State { MachineState parent_obj; + + MemoryRegion bmc_memory; + MemoryRegion bmc_dram; + MemoryRegion bmc_boot_rom; + + AspeedSoCState bmc; }; =20 +#define FBY35_BMC_RAM_SIZE (2 * GiB) + +static void fby35_bmc_init(Fby35State *s) +{ + memory_region_init(&s->bmc_memory, OBJECT(s), "bmc-memory", UINT64_MAX= ); + memory_region_init_ram(&s->bmc_dram, OBJECT(s), "bmc-dram", + FBY35_BMC_RAM_SIZE, &error_abort); + + object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); + object_property_set_int(OBJECT(&s->bmc), "ram-size", FBY35_BMC_RAM_SIZ= E, + &error_abort); + object_property_set_link(OBJECT(&s->bmc), "memory", OBJECT(&s->bmc_mem= ory), + &error_abort); + object_property_set_link(OBJECT(&s->bmc), "dram", OBJECT(&s->bmc_dram), + &error_abort); + object_property_set_int(OBJECT(&s->bmc), "hw-strap1", 0x000000C0, + &error_abort); + object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003, + &error_abort); + aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0)); + qdev_realize(DEVICE(&s->bmc), NULL, &error_abort); + + aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0); +} + static void fby35_init(MachineState *machine) { + Fby35State *s =3D FBY35(machine); + + fby35_bmc_init(s); } =20 static void fby35_class_init(ObjectClass *oc, void *data) @@ -25,6 +63,9 @@ static void fby35_class_init(ObjectClass *oc, void *data) =20 mc->desc =3D "Meta Platforms fby35"; mc->init =3D fby35_init; + mc->no_floppy =3D 1; + mc->no_cdrom =3D 1; + mc->min_cpus =3D mc->max_cpus =3D mc->default_cpus =3D 2; } =20 static const TypeInfo fby35_types[] =3D { --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814709571874.6284076625102; Thu, 14 Jul 2022 09:05:09 -0700 (PDT) Received: from localhost ([::1]:41272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1Ku-0000Qd-EA for importer@patchew.org; Thu, 14 Jul 2022 12:05:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC121-0005Mm-2Y; Thu, 14 Jul 2022 11:45:38 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:37429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11y-0000bx-0g; Thu, 14 Jul 2022 11:45:36 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjM1H9gz4yTJ; Fri, 15 Jul 2022 01:45:27 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjK320wz4xdJ; Fri, 15 Jul 2022 01:45:25 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Delevoryas Subject: [PULL 10/19] aspeed: fby35: Add a bootrom for the BMC Date: Thu, 14 Jul 2022 17:44:47 +0200 Message-Id: <20220714154456.2565189-11-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814711567100001 The BMC boots from the first flash device by fetching instructions from the flash contents. Add an alias region on 0x0 for this purpose. There are currently performance issues with this method (TBs being flushed too often), so as a faster alternative, install the flash contents as a ROM in the BMC memory space. See commit 1a15311a12fa ("hw/arm/aspeed: add a 'execute-in-place' property to boot directly from CE0") Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Peter Delevoryas [ clg: blk_pread() fixes ] Message-Id: <20220705191400.41632-8-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/fby35.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index 5c5224d37471..e7405f6570b3 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -9,6 +9,7 @@ #include "qemu/units.h" #include "qapi/error.h" #include "sysemu/sysemu.h" +#include "sysemu/block-backend.h" #include "hw/boards.h" #include "hw/arm/aspeed_soc.h" =20 @@ -23,12 +24,49 @@ struct Fby35State { MemoryRegion bmc_boot_rom; =20 AspeedSoCState bmc; + + bool mmio_exec; }; =20 #define FBY35_BMC_RAM_SIZE (2 * GiB) +#define FBY35_BMC_FIRMWARE_ADDR 0x0 + +static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr, + hwaddr offset, size_t rom_size, + Error **errp) +{ + BlockBackend *blk =3D blk_by_legacy_dinfo(dinfo); + g_autofree void *storage =3D NULL; + int64_t size; + + /* + * The block backend size should have already been 'validated' by + * the creation of the m25p80 object. + */ + size =3D blk_getlength(blk); + if (size <=3D 0) { + error_setg(errp, "failed to get flash size"); + return; + } + + if (rom_size > size) { + rom_size =3D size; + } + + storage =3D g_malloc0(rom_size); + if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { + error_setg(errp, "failed to read the initial flash content"); + return; + } + + /* TODO: find a better way to install the ROM */ + memcpy(memory_region_get_ram_ptr(mr) + offset, storage, rom_size); +} =20 static void fby35_bmc_init(Fby35State *s) { + DriveInfo *drive0 =3D drive_get(IF_MTD, 0, 0); + memory_region_init(&s->bmc_memory, OBJECT(s), "bmc-memory", UINT64_MAX= ); memory_region_init_ram(&s->bmc_dram, OBJECT(s), "bmc-dram", FBY35_BMC_RAM_SIZE, &error_abort); @@ -48,6 +86,28 @@ static void fby35_bmc_init(Fby35State *s) qdev_realize(DEVICE(&s->bmc), NULL, &error_abort); =20 aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0); + + /* Install first FMC flash content as a boot rom. */ + if (drive0) { + AspeedSMCFlash *fl =3D &s->bmc.fmc.flashes[0]; + MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + uint64_t size =3D memory_region_size(&fl->mmio); + + if (s->mmio_exec) { + memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", + &fl->mmio, 0, size); + memory_region_add_subregion(&s->bmc_memory, FBY35_BMC_FIRMWARE= _ADDR, + boot_rom); + } else { + + memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", + size, &error_abort); + memory_region_add_subregion(&s->bmc_memory, FBY35_BMC_FIRMWARE= _ADDR, + boot_rom); + fby35_bmc_write_boot_rom(drive0, boot_rom, FBY35_BMC_FIRMWARE_= ADDR, + size, &error_abort); + } + } } =20 static void fby35_init(MachineState *machine) @@ -57,6 +117,22 @@ static void fby35_init(MachineState *machine) fby35_bmc_init(s); } =20 + +static bool fby35_get_mmio_exec(Object *obj, Error **errp) +{ + return FBY35(obj)->mmio_exec; +} + +static void fby35_set_mmio_exec(Object *obj, bool value, Error **errp) +{ + FBY35(obj)->mmio_exec =3D value; +} + +static void fby35_instance_init(Object *obj) +{ + FBY35(obj)->mmio_exec =3D false; +} + static void fby35_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -66,6 +142,12 @@ static void fby35_class_init(ObjectClass *oc, void *dat= a) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->min_cpus =3D mc->max_cpus =3D mc->default_cpus =3D 2; + + object_class_property_add_bool(oc, "execute-in-place", + fby35_get_mmio_exec, + fby35_set_mmio_exec); + object_class_property_set_description(oc, "execute-in-place", + "boot directly from CE0 flash device"); } =20 static const TypeInfo fby35_types[] =3D { @@ -74,6 +156,7 @@ static const TypeInfo fby35_types[] =3D { .parent =3D TYPE_MACHINE, .class_init =3D fby35_class_init, .instance_size =3D sizeof(Fby35State), + .instance_init =3D fby35_instance_init, }, }; =20 --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16578139627181003.0390869593365; Thu, 14 Jul 2022 08:52:42 -0700 (PDT) Received: from localhost ([::1]:46806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC18r-0000GZ-O0 for importer@patchew.org; Thu, 14 Jul 2022 11:52:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC121-0005Mk-2U; Thu, 14 Jul 2022 11:45:38 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:32919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11x-0000es-BZ; Thu, 14 Jul 2022 11:45:36 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjP39bRz4xht; Fri, 15 Jul 2022 01:45:29 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjM4vg5z4xdJ; Fri, 15 Jul 2022 01:45:27 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 11/19] aspeed: Add AST1030 (BIC) to fby35 Date: Thu, 14 Jul 2022 17:44:48 +0200 Message-Id: <20220714154456.2565189-12-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657813964425100001 From: Peter Delevoryas With the BIC, the easiest way to run everything is to create two pty's for each SoC and reserve stdin/stdout for the monitor: wget https://github.com/facebook/openbmc/releases/download/openbmc-e229= 4ff5d31d/fby35.mtd wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35= -cl-2022.13.01/Y35BCL.elf qemu-system-arm -machine fby35 \ -drive file=3Dfby35.mtd,format=3Draw,if=3Dmtd \ -device loader,file=3Dfby35.mtd,addr=3D0,cpu-num=3D0 \ -serial pty -serial pty -serial mon:stdio -display none -S screen /dev/ttys0 screen /dev/ttys1 (qemu) c This commit only adds the the first server board's Bridge IC, but in the future we'll try to include the other three server board Bridge IC's too. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220705191400.41632-9-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/fby35.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index e7405f6570b3..79605f306462 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -11,7 +11,9 @@ #include "sysemu/sysemu.h" #include "sysemu/block-backend.h" #include "hw/boards.h" +#include "hw/qdev-clock.h" #include "hw/arm/aspeed_soc.h" +#include "hw/arm/boot.h" =20 #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35") OBJECT_DECLARE_SIMPLE_TYPE(Fby35State, FBY35); @@ -22,8 +24,11 @@ struct Fby35State { MemoryRegion bmc_memory; MemoryRegion bmc_dram; MemoryRegion bmc_boot_rom; + MemoryRegion bic_memory; + Clock *bic_sysclk; =20 AspeedSoCState bmc; + AspeedSoCState bic; =20 bool mmio_exec; }; @@ -110,11 +115,31 @@ static void fby35_bmc_init(Fby35State *s) } } =20 +static void fby35_bic_init(Fby35State *s) +{ + s->bic_sysclk =3D clock_new(OBJECT(s), "SYSCLK"); + clock_set_hz(s->bic_sysclk, 200000000ULL); + + memory_region_init(&s->bic_memory, OBJECT(s), "bic-memory", UINT64_MAX= ); + + object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1"); + qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk); + object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_mem= ory), + &error_abort); + aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1)); + qdev_realize(DEVICE(&s->bic), NULL, &error_abort); + + aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2); + aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4); + aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6); +} + static void fby35_init(MachineState *machine) { Fby35State *s =3D FBY35(machine); =20 fby35_bmc_init(s); + fby35_bic_init(s); } =20 =20 @@ -141,7 +166,7 @@ static void fby35_class_init(ObjectClass *oc, void *dat= a) mc->init =3D fby35_init; mc->no_floppy =3D 1; mc->no_cdrom =3D 1; - mc->min_cpus =3D mc->max_cpus =3D mc->default_cpus =3D 2; + mc->min_cpus =3D mc->max_cpus =3D mc->default_cpus =3D 3; =20 object_class_property_add_bool(oc, "execute-in-place", fby35_get_mmio_exec, --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814971624105.20478195721603; Thu, 14 Jul 2022 09:09:31 -0700 (PDT) Received: from localhost ([::1]:48656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1P8-0005gI-EW for importer@patchew.org; Thu, 14 Jul 2022 12:09:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC122-0005NJ-LG; Thu, 14 Jul 2022 11:45:39 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:59425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC11z-0000lR-8H; Thu, 14 Jul 2022 11:45:38 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjR6qgFz4xvN; Fri, 15 Jul 2022 01:45:31 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjP6kxXz4xdJ; Fri, 15 Jul 2022 01:45:29 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 12/19] docs: aspeed: Add fby35 multi-SoC machine section Date: Thu, 14 Jul 2022 17:44:49 +0200 Message-Id: <20220714154456.2565189-13-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814972759100001 From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater [ clg: - fixed URL links - Moved Facebook Yosemite section at the end of the file ] Message-Id: <20220705191400.41632-10-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 48 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 5d0a7865d3a6..445095690c04 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -182,3 +182,51 @@ To boot a kernel directly from a Zephyr build tree: =20 $ qemu-system-arm -M ast1030-evb -nographic \ -kernel zephyr.elf + +Facebook Yosemite v3.5 Platform and CraterLake Server (``fby35``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Facebook has a series of multi-node compute server designs named +Yosemite. The most recent version released was +`Yosemite v3 `__. + +Yosemite v3.5 is an iteration on this design, and is very similar: there's= a +baseboard with a BMC, and 4 server slots. The new server board design term= ed +"CraterLake" includes a Bridge IC (BIC), with room for expansion boards to +include various compute accelerators (video, inferencing, etc). At the mom= ent, +only the first server slot's BIC is included. + +Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds +can be fit into a chassis. See `here `__ +for an example. + +In this generation, the BMC is an AST2600 and each BIC is an AST1030. The = BMC +runs `OpenBMC `__, and the BIC runs +`OpenBIC `__. + +Firmware images can be retrieved from the Github releases or built from the +source code, see the README's for instructions on that. This image uses the +"fby35" machine recipe from OpenBMC, and the "yv35-cl" target from OpenBIC. +Some reference images can also be found here: + +.. code-block:: bash + + $ wget https://github.com/facebook/openbmc/releases/download/openbmc-e= 2294ff5d31d/fby35.mtd + $ wget https://github.com/peterdelevoryas/OpenBIC/releases/download/ob= y35-cl-2022.13.01/Y35BCL.elf + +Since this machine has multiple SoC's, each with their own serial console,= the +recommended way to run it is to allocate a pseudoterminal for each serial +console and let the monitor use stdio. Also, starting in a paused state is +useful because it allows you to attach to the pseudoterminals before the b= oot +process starts. + +.. code-block:: bash + + $ qemu-system-arm -machine fby35 \ + -drive file=3Dfby35.mtd,format=3Draw,if=3Dmtd \ + -device loader,file=3DY35BCL.elf,addr=3D0,cpu-num=3D2 \ + -serial pty -serial pty -serial mon:stdio \ + -display none -S + $ screen /dev/tty0 # In a separate TMUX pane, terminal window, etc. + $ screen /dev/tty1 + $ (qemu) c # Start the boot process once screen is setup. --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657815402668751.7458620237458; Thu, 14 Jul 2022 09:16:42 -0700 (PDT) Received: from localhost ([::1]:35680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1W5-0006ue-C0 for importer@patchew.org; Thu, 14 Jul 2022 12:16:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12O-0005UF-2Q; Thu, 14 Jul 2022 11:46:01 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:44579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12L-0000ZB-HK; Thu, 14 Jul 2022 11:45:59 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjV3FSPz4ySg; Fri, 15 Jul 2022 01:45:34 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjS3F4vz4xdJ; Fri, 15 Jul 2022 01:45:32 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Delevoryas , Joel Stanley Subject: [PULL 13/19] docs: aspeed: Minor updates Date: Thu, 14 Jul 2022 17:44:50 +0200 Message-Id: <20220714154456.2565189-14-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657815404714100001 Some more controllers have been modeled recently. Reflect that in the list of supported devices. New machines were also added. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Peter Delevoryas Reviewed-by: Joel Stanley Message-Id: <20220706172131.809255-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 445095690c04..6c5b05128ea8 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -31,7 +31,10 @@ AST2600 SoC based machines : - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC - ``rainier-bmc`` IBM Rainier POWER10 BMC - ``fuji-bmc`` Facebook Fuji BMC +- ``bletchley-bmc`` Facebook Bletchley BMC - ``fby35-bmc`` Facebook fby35 BMC +- ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC +- ``qcom-firework-bmc`` Qualcomm Firework BMC =20 Supported devices ----------------- @@ -40,7 +43,7 @@ Supported devices * Interrupt Controller (VIC) * Timer Controller * RTC Controller - * I2C Controller + * I2C Controller, including the new register interface of the AST2600 * System Control Unit (SCU) * SRAM mapping * X-DMA Controller (basic interface) @@ -57,6 +60,10 @@ Supported devices * LPC Peripheral Controller (a subset of subdevices are supported) * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA * ADC + * Secure Boot Controller (AST2600) + * eMMC Boot Controller (dummy) + * PECI Controller (minimal) + * I3C Controller =20 =20 Missing devices @@ -68,12 +75,10 @@ Missing devices * Super I/O Controller * PCI-Express 1 Controller * Graphic Display Controller - * PECI Controller * MCTP Controller * Mailbox Controller * Virtual UART * eSPI Controller - * I3C Controller =20 Boot options ------------ @@ -154,6 +159,8 @@ Supported devices * LPC Peripheral Controller (a subset of subdevices are supported) * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA * ADC + * Secure Boot Controller + * PECI Controller (minimal) =20 =20 Missing devices @@ -161,7 +168,6 @@ Missing devices =20 * PWM and Fan Controller * Slave GPIO Controller - * PECI Controller * Mailbox Controller * Virtual UART * eSPI Controller --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814134333964.5295311920945; Thu, 14 Jul 2022 08:55:34 -0700 (PDT) Received: from localhost ([::1]:53862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1Bd-0005lC-47 for importer@patchew.org; Thu, 14 Jul 2022 11:55:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC126-0005Oo-Nt; Thu, 14 Jul 2022 11:45:45 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:41067 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC122-0000qX-VM; Thu, 14 Jul 2022 11:45:41 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjX3G2Zz4yTL; Fri, 15 Jul 2022 01:45:36 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjV6p2Dz4xdJ; Fri, 15 Jul 2022 01:45:34 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 14/19] test/avocado/machine_aspeed.py: Add SDK tests Date: Thu, 14 Jul 2022 17:44:51 +0200 Message-Id: <20220714154456.2565189-15-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814135941100001 The Aspeed SDK kernel usually includes support for the lastest HW features. This is interesting to exercise QEMU and discover the gaps in the models. Add extra I2C tests for the AST2600 EVB machine to check the new register interface. Message-Id: <20220707091239.1029561-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- tests/avocado/machine_aspeed.py | 68 +++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed= .py index 3b8f784a57b6..b4e35a3d0743 100644 --- a/tests/avocado/machine_aspeed.py +++ b/tests/avocado/machine_aspeed.py @@ -170,3 +170,71 @@ def test_arm_ast2600_evb_builroot(self): exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', ye= ar); =20 self.do_test_arm_aspeed_buidroot_poweroff() + + + def do_test_arm_aspeed_sdk_start(self, image, cpu_id): + self.vm.set_console() + self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format= =3Draw', + '-net', 'nic', '-net', 'user') + self.vm.launch() + + self.wait_for_console_pattern('U-Boot 2019.04') + self.wait_for_console_pattern('## Loading kernel from FIT Image') + self.wait_for_console_pattern('Starting kernel ...') + self.wait_for_console_pattern('Booting Linux on physical CPU ' + c= pu_id) + + def test_arm_ast2500_evb_sdk(self): + """ + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:ast2500-evb + """ + + image_url =3D ('https://github.com/AspeedTech-BMC/openbmc/releases= /' + 'download/v08.01/ast2500-default-obmc.tar.gz') + image_hash =3D ('5375f82b4c43a79427909342a1e18b4e48bd663e384668621= 45d27bb358796fd') + image_path =3D self.fetch_asset(image_url, asset_hash=3Dimage_hash, + algorithm=3D'sha256') + archive.extract(image_path, self.workdir) + + self.do_test_arm_aspeed_sdk_start( + self.workdir + '/ast2500-default/image-bmc', '0x0') + self.wait_for_console_pattern('ast2500-default login:') + + def test_arm_ast2600_evb_sdk(self): + """ + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:ast2600-evb + """ + + image_url =3D ('https://github.com/AspeedTech-BMC/openbmc/releases= /' + 'download/v08.01/ast2600-default-obmc.tar.gz') + image_hash =3D ('f12ef15e8c1f03a214df3b91c814515c5e2b2f56119021398= c1dbdd626817d15') + image_path =3D self.fetch_asset(image_url, asset_hash=3Dimage_hash, + algorithm=3D'sha256') + archive.extract(image_path, self.workdir) + + self.vm.add_args('-device', + 'tmp105,bus=3Daspeed.i2c.bus.5,address=3D0x4d,id= =3Dtmp-test'); + self.vm.add_args('-device', + 'ds1338,bus=3Daspeed.i2c.bus.5,address=3D0x32'); + self.do_test_arm_aspeed_sdk_start( + self.workdir + '/ast2600-default/image-bmc', '0xf00') + self.wait_for_console_pattern('ast2600-default login:') + exec_command_and_wait_for_pattern(self, 'root', 'Password:') + exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-d= efault:~#') + + exec_command_and_wait_for_pattern(self, + 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device', + 'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d'); + exec_command_and_wait_for_pattern(self, + 'cat /sys/class/hwmon/hwmon19/temp1_input', '= 0') + self.vm.command('qom-set', path=3D'/machine/peripheral/tmp-test', + property=3D'temperature', value=3D18000); + exec_command_and_wait_for_pattern(self, + 'cat /sys/class/hwmon/hwmon19/temp1_input', '= 18000') + + exec_command_and_wait_for_pattern(self, + 'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_devic= e', + 'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32'); + year =3D time.strftime("%Y") + exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', ye= ar); --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814928135762.6341749140138; Thu, 14 Jul 2022 09:08:48 -0700 (PDT) Received: from localhost ([::1]:47222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1OQ-0004hK-Cm for importer@patchew.org; Thu, 14 Jul 2022 12:08:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12Q-0005Vj-H4; Thu, 14 Jul 2022 11:46:03 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:59425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12O-0000lR-H3; Thu, 14 Jul 2022 11:46:02 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjZ6vXXz4xht; Fri, 15 Jul 2022 01:45:38 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjX6s9Vz4xRC; Fri, 15 Jul 2022 01:45:36 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Iris Chen , Francisco Iglesias , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 15/19] hw: m25p80: Add Block Protect and Top Bottom bits for write protect Date: Thu, 14 Jul 2022 17:44:52 +0200 Message-Id: <20220714154456.2565189-16-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814929395100001 From: Iris Chen Signed-off-by: Iris Chen Reviewed-by: Francisco Iglesias Message-Id: <20220708164552.3462620-1-irischenlj@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/block/m25p80.c | 102 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 90 insertions(+), 12 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 46dd9ee9bb06..a8d2519141f7 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -36,21 +36,19 @@ #include "trace.h" #include "qom/object.h" =20 -/* Fields for FlashPartInfo->flags */ - -/* erase capabilities */ -#define ER_4K 1 -#define ER_32K 2 -/* set to allow the page program command to write 0s back to 1. Useful for - * modelling EEPROM with SPI flash command set - */ -#define EEPROM 0x100 - /* 16 MiB max in 3 byte address mode */ #define MAX_3BYTES_SIZE 0x1000000 - #define SPI_NOR_MAX_ID_LEN 6 =20 +/* Fields for FlashPartInfo->flags */ +enum spi_flash_option_flags { + ER_4K =3D BIT(0), + ER_32K =3D BIT(1), + EEPROM =3D BIT(2), + HAS_SR_TB =3D BIT(3), + HAS_SR_BP3_BIT6 =3D BIT(4), +}; + typedef struct FlashPartInfo { const char *part_name; /* @@ -251,7 +249,8 @@ static const FlashPartInfo known_devices[] =3D { { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, - { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, + { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, + ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB) }, { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K= ) }, @@ -478,6 +477,11 @@ struct Flash { bool reset_enable; bool quad_enable; bool aai_enable; + bool block_protect0; + bool block_protect1; + bool block_protect2; + bool block_protect3; + bool top_bottom_bit; bool status_register_write_disabled; uint8_t ear; =20 @@ -623,12 +627,36 @@ void flash_write8(Flash *s, uint32_t addr, uint8_t da= ta) { uint32_t page =3D addr / s->pi->page_size; uint8_t prev =3D s->storage[s->cur_addr]; + uint32_t block_protect_value =3D (s->block_protect3 << 3) | + (s->block_protect2 << 2) | + (s->block_protect1 << 1) | + (s->block_protect0 << 0); =20 if (!s->write_enable) { qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\= n"); return; } =20 + if (block_protect_value > 0) { + uint32_t num_protected_sectors =3D 1 << (block_protect_value - 1); + uint32_t sector =3D addr / s->pi->sector_size; + + /* top_bottom_bit =3D=3D 0 means TOP */ + if (!s->top_bottom_bit) { + if (s->pi->n_sectors <=3D sector + num_protected_sectors) { + qemu_log_mask(LOG_GUEST_ERROR, + "M25P80: write with write protect!\n"); + return; + } + } else { + if (sector < num_protected_sectors) { + qemu_log_mask(LOG_GUEST_ERROR, + "M25P80: write with write protect!\n"); + return; + } + } + } + if ((prev ^ data) & data) { trace_m25p80_programming_zero_to_one(s, addr, prev, data); } @@ -726,6 +754,15 @@ static void complete_collecting_data(Flash *s) break; case WRSR: s->status_register_write_disabled =3D extract32(s->data[0], 7, 1); + s->block_protect0 =3D extract32(s->data[0], 2, 1); + s->block_protect1 =3D extract32(s->data[0], 3, 1); + s->block_protect2 =3D extract32(s->data[0], 4, 1); + if (s->pi->flags & HAS_SR_TB) { + s->top_bottom_bit =3D extract32(s->data[0], 5, 1); + } + if (s->pi->flags & HAS_SR_BP3_BIT6) { + s->block_protect3 =3D extract32(s->data[0], 6, 1); + } =20 switch (get_man(s)) { case MAN_SPANSION: @@ -1212,6 +1249,15 @@ static void decode_new_cmd(Flash *s, uint32_t value) case RDSR: s->data[0] =3D (!!s->write_enable) << 1; s->data[0] |=3D (!!s->status_register_write_disabled) << 7; + s->data[0] |=3D (!!s->block_protect0) << 2; + s->data[0] |=3D (!!s->block_protect1) << 3; + s->data[0] |=3D (!!s->block_protect2) << 4; + if (s->pi->flags & HAS_SR_TB) { + s->data[0] |=3D (!!s->top_bottom_bit) << 5; + } + if (s->pi->flags & HAS_SR_BP3_BIT6) { + s->data[0] |=3D (!!s->block_protect3) << 6; + } =20 if (get_man(s) =3D=3D MAN_MACRONIX || get_man(s) =3D=3D MAN_ISSI) { s->data[0] |=3D (!!s->quad_enable) << 6; @@ -1552,6 +1598,11 @@ static void m25p80_reset(DeviceState *d) =20 s->wp_level =3D true; s->status_register_write_disabled =3D false; + s->block_protect0 =3D false; + s->block_protect1 =3D false; + s->block_protect2 =3D false; + s->block_protect3 =3D false; + s->top_bottom_bit =3D false; =20 reset_memory(s); } @@ -1638,6 +1689,32 @@ static const VMStateDescription vmstate_m25p80_write= _protect =3D { } }; =20 +static bool m25p80_block_protect_needed(void *opaque) +{ + Flash *s =3D (Flash *)opaque; + + return s->block_protect0 || + s->block_protect1 || + s->block_protect2 || + s->block_protect3 || + s->top_bottom_bit; +} + +static const VMStateDescription vmstate_m25p80_block_protect =3D { + .name =3D "m25p80/block_protect", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D m25p80_block_protect_needed, + .fields =3D (VMStateField[]) { + VMSTATE_BOOL(block_protect0, Flash), + VMSTATE_BOOL(block_protect1, Flash), + VMSTATE_BOOL(block_protect2, Flash), + VMSTATE_BOOL(block_protect3, Flash), + VMSTATE_BOOL(top_bottom_bit, Flash), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m25p80 =3D { .name =3D "m25p80", .version_id =3D 0, @@ -1670,6 +1747,7 @@ static const VMStateDescription vmstate_m25p80 =3D { &vmstate_m25p80_data_read_loop, &vmstate_m25p80_aai_enable, &vmstate_m25p80_write_protect, + &vmstate_m25p80_block_protect, NULL } }; --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814578023580.3833103773374; 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Fri, 15 Jul 2022 01:45:39 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Iris Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 16/19] hw: m25p80: add tests for BP and TB bit write protect Date: Thu, 14 Jul 2022 17:44:53 +0200 Message-Id: <20220714154456.2565189-17-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814579973100001 From: Iris Chen Signed-off-by: Iris Chen Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220627185234.1911337-3-irischenlj@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed_smc-test.c | 111 ++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index 1258687eacd8..05ce941566e6 100644 --- a/tests/qtest/aspeed_smc-test.c +++ b/tests/qtest/aspeed_smc-test.c @@ -192,6 +192,24 @@ static void read_page_mem(uint32_t addr, uint32_t *pag= e) } } =20 +static void write_page_mem(uint32_t addr, uint32_t write_value) +{ + spi_ctrl_setmode(CTRL_WRITEMODE, PP); + + for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + writel(ASPEED_FLASH_BASE + addr + i * 4, write_value); + } +} + +static void assert_page_mem(uint32_t addr, uint32_t expected_value) +{ + uint32_t page[FLASH_PAGE_SIZE / 4]; + read_page_mem(addr, page); + for (int i =3D 0; i < FLASH_PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], =3D=3D, expected_value); + } +} + static void test_erase_sector(void) { uint32_t some_page_addr =3D 0x600 * FLASH_PAGE_SIZE; @@ -501,6 +519,95 @@ static void test_status_reg_write_protection(void) flash_reset(); } =20 +static void test_write_block_protect(void) +{ + uint32_t sector_size =3D 65536; + uint32_t n_sectors =3D 512; + + spi_ce_ctrl(1 << CRTL_EXTENDED0); + spi_conf(CONF_ENABLE_W0); + + uint32_t bp_bits =3D 0b0; + + for (int i =3D 0; i < 16; i++) { + bp_bits =3D ((i & 0b1000) << 3) | ((i & 0b0111) << 2); + + spi_ctrl_start_user(); + writeb(ASPEED_FLASH_BASE, WREN); + writeb(ASPEED_FLASH_BASE, BULK_ERASE); + writeb(ASPEED_FLASH_BASE, WREN); + writeb(ASPEED_FLASH_BASE, WRSR); + writeb(ASPEED_FLASH_BASE, bp_bits); + writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); + writeb(ASPEED_FLASH_BASE, WREN); + spi_ctrl_stop_user(); + + uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors= ) : 0; + uint32_t protection_start =3D n_sectors - num_protected_sectors; + uint32_t protection_end =3D n_sectors; + + for (int sector =3D 0; sector < n_sectors; sector++) { + uint32_t addr =3D sector * sector_size; + + assert_page_mem(addr, 0xffffffff); + write_page_mem(addr, make_be32(0xabcdef12)); + + uint32_t expected_value =3D protection_start <=3D sector + && sector < protection_end + ? 0xffffffff : 0xabcdef12; + + assert_page_mem(addr, expected_value); + } + } + + flash_reset(); +} + +static void test_write_block_protect_bottom_bit(void) +{ + uint32_t sector_size =3D 65536; + uint32_t n_sectors =3D 512; + + spi_ce_ctrl(1 << CRTL_EXTENDED0); + spi_conf(CONF_ENABLE_W0); + + /* top bottom bit is enabled */ + uint32_t bp_bits =3D 0b00100 << 3; + + for (int i =3D 0; i < 16; i++) { + bp_bits =3D (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2); + + spi_ctrl_start_user(); + writeb(ASPEED_FLASH_BASE, WREN); + writeb(ASPEED_FLASH_BASE, BULK_ERASE); + writeb(ASPEED_FLASH_BASE, WREN); + writeb(ASPEED_FLASH_BASE, WRSR); + writeb(ASPEED_FLASH_BASE, bp_bits); + writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); + writeb(ASPEED_FLASH_BASE, WREN); + spi_ctrl_stop_user(); + + uint32_t num_protected_sectors =3D i ? MIN(1 << (i - 1), n_sectors= ) : 0; + uint32_t protection_start =3D 0; + uint32_t protection_end =3D num_protected_sectors; + + for (int sector =3D 0; sector < n_sectors; sector++) { + uint32_t addr =3D sector * sector_size; + + assert_page_mem(addr, 0xffffffff); + write_page_mem(addr, make_be32(0xabcdef12)); + + uint32_t expected_value =3D protection_start <=3D sector + && sector < protection_end + ? 0xffffffff : 0xabcdef12; + + assert_page_mem(addr, expected_value); + } + } + + flash_reset(); +} + static char tmp_path[] =3D "/tmp/qtest.m25p80.XXXXXX"; =20 int main(int argc, char **argv) @@ -529,6 +636,10 @@ int main(int argc, char **argv) qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg); qtest_add_func("/ast2400/smc/status_reg_write_protection", test_status_reg_write_protection); + qtest_add_func("/ast2400/smc/write_block_protect", + test_write_block_protect); + qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit", + test_write_block_protect_bottom_bit); =20 flash_reset(); ret =3D g_test_run(); --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814198743273.78788468481855; Thu, 14 Jul 2022 08:56:38 -0700 (PDT) Received: from localhost ([::1]:56336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1Cf-0007hy-OP for importer@patchew.org; Thu, 14 Jul 2022 11:56:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12H-0005Rc-IV; Thu, 14 Jul 2022 11:45:56 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:59375 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12B-0000u8-LC; Thu, 14 Jul 2022 11:45:50 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjg3TbPz4xdJ; Fri, 15 Jul 2022 01:45:43 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjd5DNhz4xRC; Fri, 15 Jul 2022 01:45:41 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 17/19] qtest/aspeed_gpio: Add input pin modification test Date: Thu, 14 Jul 2022 17:44:54 +0200 Message-Id: <20220714154456.2565189-18-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814199912100003 From: Peter Delevoryas Verify the current behavior, which is that input pins can be modified by guest OS register writes. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220712023219.41065-2-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- tests/qtest/aspeed_gpio-test.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c index bac63e8742f4..8f524540998d 100644 --- a/tests/qtest/aspeed_gpio-test.c +++ b/tests/qtest/aspeed_gpio-test.c @@ -28,6 +28,11 @@ #include "qapi/qmp/qdict.h" #include "libqtest-single.h" =20 +#define AST2600_GPIO_BASE 0x1E780000 + +#define GPIO_ABCD_DATA_VALUE 0x000 +#define GPIO_ABCD_DIRECTION 0x004 + static void test_set_colocated_pins(const void *data) { QTestState *s =3D (QTestState *)data; @@ -46,6 +51,27 @@ static void test_set_colocated_pins(const void *data) g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); } =20 +static void test_set_input_pins(const void *data) +{ + QTestState *s =3D (QTestState *)data; + char name[16]; + uint32_t value; + + qtest_writel(s, AST2600_GPIO_BASE + GPIO_ABCD_DIRECTION, 0x00000000); + for (char c =3D 'A'; c <=3D 'D'; c++) { + for (int i =3D 0; i < 8; i++) { + sprintf(name, "gpio%c%d", c, i); + qtest_qom_set_bool(s, "/machine/soc/gpio", name, true); + } + } + value =3D qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); + g_assert_cmphex(value, =3D=3D, 0xffffffff); + + qtest_writel(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE, 0x00000000); + value =3D qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); + g_assert_cmphex(value, =3D=3D, 0x00000000); +} + int main(int argc, char **argv) { QTestState *s; @@ -56,6 +82,7 @@ int main(int argc, char **argv) s =3D qtest_init("-machine ast2600-evb"); qtest_add_data_func("/ast2600/gpio/set_colocated_pins", s, test_set_colocated_pins); + qtest_add_data_func("/ast2600/gpio/set_input_pins", s, test_set_input_= pins); r =3D g_test_run(); qtest_quit(s); =20 --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657815222027142.28751806131606; Thu, 14 Jul 2022 09:13:42 -0700 (PDT) Received: from localhost ([::1]:58268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1TA-0003RX-J4 for importer@patchew.org; Thu, 14 Jul 2022 12:13:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53982) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12I-0005Rn-KK; Thu, 14 Jul 2022 11:45:56 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:57841 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12D-0000uK-BU; Thu, 14 Jul 2022 11:45:53 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjk1VHPz4yTJ; Fri, 15 Jul 2022 01:45:46 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjg74M7z4xRC; Fri, 15 Jul 2022 01:45:43 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 18/19] hw/gpio/aspeed: Don't let guests modify input pins Date: Thu, 14 Jul 2022 17:44:55 +0200 Message-Id: <20220714154456.2565189-19-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657815223754100001 From: Peter Delevoryas Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin values, and the QOM property setter should only be permitted to modify input pins. This change also updates the gpio input pin test to match this expectation. Andrew suggested this particularly refactoring here: https://lore.kernel.org/qemu-devel/23523aa1-ba81-412b-92cc-8174faba3612= @www.fastmail.com/ Suggested-by: Andrew Jeffery Signed-off-by: Peter Delevoryas Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and = AST2500") Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220712023219.41065-3-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_gpio.c | 15 ++++++++------- tests/qtest/aspeed_gpio-test.c | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index a62a673857c2..1e267dd48203 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -268,7 +268,7 @@ static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s= , GPIOSets *regs) } =20 static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, - uint32_t value) + uint32_t value, uint32_t mode_mask) { uint32_t input_mask =3D regs->input_mask; uint32_t direction =3D regs->direction; @@ -277,7 +277,8 @@ static void aspeed_gpio_update(AspeedGPIOState *s, GPIO= Sets *regs, uint32_t diff; int gpio; =20 - diff =3D old ^ new; + diff =3D (old ^ new); + diff &=3D mode_mask; if (diff) { for (gpio =3D 0; gpio < ASPEED_GPIOS_PER_SET; gpio++) { uint32_t mask =3D 1 << gpio; @@ -339,7 +340,7 @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *= s, uint32_t set_idx, value &=3D ~pin_mask; } =20 - aspeed_gpio_update(s, &s->sets[set_idx], value); + aspeed_gpio_update(s, &s->sets[set_idx], value, ~s->sets[set_idx].dire= ction); } =20 /* @@ -653,7 +654,7 @@ static void aspeed_gpio_write_index_mode(void *opaque, = hwaddr offset, reg_value =3D update_value_control_source(set, set->data_value, reg_value); set->data_read =3D reg_value; - aspeed_gpio_update(s, set, reg_value); + aspeed_gpio_update(s, set, reg_value, set->direction); return; case gpio_reg_idx_direction: reg_value =3D set->direction; @@ -753,7 +754,7 @@ static void aspeed_gpio_write_index_mode(void *opaque, = hwaddr offset, __func__, offset, data, reg_idx_type); return; } - aspeed_gpio_update(s, set, set->data_value); + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); return; } =20 @@ -799,7 +800,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, data &=3D props->output; data =3D update_value_control_source(set, set->data_value, data); set->data_read =3D data; - aspeed_gpio_update(s, set, data); + aspeed_gpio_update(s, set, data, set->direction); return; case gpio_reg_direction: /* @@ -875,7 +876,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, PRIx64"\n", __func__, offset); return; } - aspeed_gpio_update(s, set, set->data_value); + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); return; } =20 diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c index 8f524540998d..d38f51d71908 100644 --- a/tests/qtest/aspeed_gpio-test.c +++ b/tests/qtest/aspeed_gpio-test.c @@ -69,7 +69,7 @@ static void test_set_input_pins(const void *data) =20 qtest_writel(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE, 0x00000000); value =3D qtest_readl(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE); - g_assert_cmphex(value, =3D=3D, 0x00000000); + g_assert_cmphex(value, =3D=3D, 0xffffffff); } =20 int main(int argc, char **argv) --=20 2.35.3 From nobody Thu Apr 10 10:43:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657814381807881.6324878168807; Thu, 14 Jul 2022 08:59:41 -0700 (PDT) Received: from localhost ([::1]:36366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC1Fc-0005Fw-Ip for importer@patchew.org; Thu, 14 Jul 2022 11:59:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12K-0005SC-DD; Thu, 14 Jul 2022 11:45:57 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:42061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC12I-0000uT-Kx; Thu, 14 Jul 2022 11:45:56 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LkJjm3Pk0z4yTL; Fri, 15 Jul 2022 01:45:48 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LkJjk54Qyz4xRC; Fri, 15 Jul 2022 01:45:46 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 19/19] aspeed: Add fby35-bmc slot GPIO's Date: Thu, 14 Jul 2022 17:44:56 +0200 Message-Id: <20220714154456.2565189-20-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220714154456.2565189-1-clg@kaod.org> References: <20220714154456.2565189-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=QWOl=XT=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657814383599100001 From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220712023219.41065-4-peter@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 60bc2e4cf9b0..4193a3d23d1d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1358,11 +1358,23 @@ static void fby35_reset(MachineState *state) =20 qemu_devices_reset(); =20 - /* Board ID */ + /* Board ID: 7 (Class-1, 4 slots) */ object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); + + /* Slot presence pins, inverse polarity. (False means present) */ + object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); + + /* Slot 12v power pins, normal polarity. (True means powered-on) */ + object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); } =20 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) --=20 2.35.3