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bh=hapmOFEwmUHGSMahVEGMQVUPE796CbuBCALsQKsJHd4=; b=SIrQglTgXcarfFJG9MYtNj8LzXWB4v3sVrVmNSblwUx4u4uzWrcu4lsn 8r7/BwArc6V89fMj27PPY4EgsjEpNQMt3b5bapnUe6FZ7W6qXTN8UzZCt A4gPD/r1qFIIkVREvNfHVPt22V88FKwOzcJ23Yv9bfHYyZN0tqwXOJK2Q 4=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 05/11] target/arm: Make stage_2_format for cache attributes optional Date: Thu, 14 Jul 2022 16:53:49 +0200 Message-ID: <20220714145355.7225-6-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:13 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657818235002100001 From: Tobias R=C3=B6hmel The Cortex-R52 has a 2 stage MPU translation process but doesn't have the F= EAT_S2FWB feature. This makes it neccessary to allow for the old cache attr= ibut combination. This is facilitated by changing the control path of combine_cacheattrs inst= ead of failing if the second cache attributes struct is not in that format. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/ptw.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4d97a24808..8b037c1f55 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2108,7 +2108,11 @@ static uint8_t combined_attrs_nofwb(CPUARMState *env, { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + if (s2.is_s2_format) { + s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + } else { + s2_mair_attrs =3D s2.attrs; + } =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2166,6 +2170,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) static uint8_t combined_attrs_fwb(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2) { + assert(s2.is_s2_format && !s1.is_s2_format); + switch (s2.attrs) { case 7: /* Use stage 1 attributes */ @@ -2215,7 +2221,6 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, ARMCacheAttrs ret; bool tagged =3D false; =20 - assert(s2.is_s2_format && !s1.is_s2_format); ret.is_s2_format =3D false; =20 if (s1.attrs =3D=3D 0xf0) { --=20 2.25.1