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bh=qWj0N60MwxAdxvJV2+cY4KbK5kqSKODWxUDkbwn8t3c=; b=ilMW+8/QLzLWGCWM3T98UV/3dOiTJaHjfrCM8m7waOuTecQFfWtXti+d LEqRccG15+rhX6UR8Qw+r1sXR16IP3vCm83A5UxIk9MhI0/9EjXIbWBNm S7ZUl4t3fgfj7bFgpFX0kHc7GHJl83HRxXw5ywvkDlI/byW0cOcQ9p3+6 E=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 04/11] target/arm: Make RVBAR available for non AARCH64 CPUs Date: Thu, 14 Jul 2022 16:53:48 +0200 Message-ID: <20220714145355.7225-5-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657811350630100001 From: Tobias R=C3=B6hmel The ARM Cortex-R52 is not AARCH64 but uses RVBAR. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..2c26a5387d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,6 +258,10 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR, CP11, 3); #endif + if (arm_feature(env, ARM_FEATURE_V8_R)) { + env->cp15.rvbar =3D cpu->rvbar_prop; + env->regs[15] =3D cpu->rvbar_prop; + } } =20 #if defined(CONFIG_USER_ONLY) @@ -1273,7 +1277,8 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_proper= ty); } =20 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + arm_feature(&cpu->env, ARM_FEATURE_V8_R)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); --=20 2.25.1