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bh=j6hZ0WNJZLcfk4eENbwZVIjSq1eQDNaDZEXP7hNxr2c=; b=iGqrFinsJNb7WtMFrMeSmcSvIiOHA81M7LKpfcwtvbZNh3E/9rXxjvbb BlW8uqrCu+wlv1Mh6pPLWLAv5ae3hpMlyJ1e8agBAaYo3Rde/p8TdHS8b pYF+p73Ui2V73IjrJW/KSk3D3I4gsG6aGJNfJOV3A4nwWol/zP7ctAYFs M=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 01/11] target/arm: Add ARM_FEATURE_V8_R Date: Thu, 14 Jul 2022 16:53:45 +0200 Message-ID: <20220714145355.7225-2-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657811000204100001 From: Tobias R=C3=B6hmel This flag is necessary to add features for the Cortex-R52. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df677b2d5d..86e06116a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2287,6 +2287,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + ARM_FEATURE_V8_R, }; =20 static inline int arm_feature(CPUARMState *env, int feature) --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657817522; cv=none; d=zohomail.com; s=zohoarc; b=nOml/+MeGMdMmPnr16W52tA8ydfL5w0g6t+q/b7mqA+YdjtTITT91/GobGUbqO1vEhDicMiF/pXa9COLR4h+kL8xM2pmcECdx/FdhPj79+orYYNKlCnglB58/i06Qgst1iNjRVxWmZdeZr0raZkkQvc0ONavhFM0LdegiofIbwQ= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:11 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657817523299100001 From: Tobias R=C3=B6hmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu_tcg.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b751a19c8a..49fb03c09a 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -843,6 +843,59 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 +static const ARMCPRegInfo cortexr52_cp_reginfo[] =3D { + /* Dummy the TCM region regs for the moment */ + { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, + .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, +}; + +static void cortex_r52_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_R); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + cpu->midr =3D 0x411fd133; /* r1p3 */ + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034023; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8144c004; + cpu->reset_sctlr =3D 0x30c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x10111001; + cpu->isar.id_dfr0 =3D 0x03010006; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00211040; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0xf0102211; + cpu->isar.id_mmfr4 =3D 0x00000010; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232142; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x00010001; + cpu->isar.dbgdidr =3D 0x77168000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + + cpu->pmsav7_dregion =3D 16; + + define_arm_cp_regs(cpu, cortexr52_cp_reginfo); +} + static void cortex_r5f_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1148,6 +1201,7 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, + { .name =3D "cortex-r52", .initfn =3D cortex_r52_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "ti925t", .initfn =3D ti925t_initfn }, { .name =3D "sa1100", .initfn =3D sa1100_initfn }, --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657817753; cv=none; d=zohomail.com; s=zohoarc; b=h3EI2xigsAHASyu1/2tnDoH1ihv6aeyU1hSRkhubRvTm8XLCN7oXbV0l0tx0d/uOVdyrHDowmaoET/WNwPRoOGcISX8GyAfcbG4bH3JG9naHDj9QSUCNpytDcQADZWdwhEkKJM7H/3dAJxA9FvVgzjbq3zR/eGyr/IIWnBP2h7s= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:12 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657817753885100001 From: Tobias R=C3=B6hmel This register is used by the ARM Cortex-R52. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/helper.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6457e6301c..bdf1df37d5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8201,6 +8201,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; + ARMCPRegInfo id_v8r_midr_cp_reginfo[] =3D { + { .name =3D "MIDR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .resetvalue =3D cpu->midr, + .writefn =3D arm_cp_write_ignore, .raw_writefn =3D raw_write, + .readfn =3D midr_read, + .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), + .type =3D ARM_CP_OVERRIDE }, + }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ { .name =3D "CTR", @@ -8264,7 +8273,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; } - if (arm_feature(env, ARM_FEATURE_V8)) { + if (arm_feature(env, ARM_FEATURE_V8_R)) { + define_arm_cp_regs(cpu, id_v8r_midr_cp_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657811349; cv=none; d=zohomail.com; s=zohoarc; b=bDwaH1oZeTqm8Jt9BNDERAyrRZfElVYKTHuiNLSc9hS3Zi4lvhzc1GSrtv7BCjOue84xyoUlO3kjJj/WCvrwgqineqxQxNNBzxELVnBGpfUOBkQ8Uyoh7nQipKiIjU+JzlT9AZjfMsLX3qWXbz4O0JgQ2DM8iR/V+9OL/zdGiSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Thu, 14 Jul 2022 07:54:18 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Jul 2022 07:54:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657810827; x=1689346827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qWj0N60MwxAdxvJV2+cY4KbK5kqSKODWxUDkbwn8t3c=; b=ilMW+8/QLzLWGCWM3T98UV/3dOiTJaHjfrCM8m7waOuTecQFfWtXti+d LEqRccG15+rhX6UR8Qw+r1sXR16IP3vCm83A5UxIk9MhI0/9EjXIbWBNm S7ZUl4t3fgfj7bFgpFX0kHc7GHJl83HRxXw5ywvkDlI/byW0cOcQ9p3+6 E=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 04/11] target/arm: Make RVBAR available for non AARCH64 CPUs Date: Thu, 14 Jul 2022 16:53:48 +0200 Message-ID: <20220714145355.7225-5-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657811350630100001 From: Tobias R=C3=B6hmel The ARM Cortex-R52 is not AARCH64 but uses RVBAR. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..2c26a5387d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,6 +258,10 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR, CP11, 3); #endif + if (arm_feature(env, ARM_FEATURE_V8_R)) { + env->cp15.rvbar =3D cpu->rvbar_prop; + env->regs[15] =3D cpu->rvbar_prop; + } } =20 #if defined(CONFIG_USER_ONLY) @@ -1273,7 +1277,8 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_proper= ty); } =20 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + arm_feature(&cpu->env, ARM_FEATURE_V8_R)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=hapmOFEwmUHGSMahVEGMQVUPE796CbuBCALsQKsJHd4=; b=SIrQglTgXcarfFJG9MYtNj8LzXWB4v3sVrVmNSblwUx4u4uzWrcu4lsn 8r7/BwArc6V89fMj27PPY4EgsjEpNQMt3b5bapnUe6FZ7W6qXTN8UzZCt A4gPD/r1qFIIkVREvNfHVPt22V88FKwOzcJ23Yv9bfHYyZN0tqwXOJK2Q 4=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 05/11] target/arm: Make stage_2_format for cache attributes optional Date: Thu, 14 Jul 2022 16:53:49 +0200 Message-ID: <20220714145355.7225-6-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:13 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657818235002100001 From: Tobias R=C3=B6hmel The Cortex-R52 has a 2 stage MPU translation process but doesn't have the F= EAT_S2FWB feature. This makes it neccessary to allow for the old cache attr= ibut combination. This is facilitated by changing the control path of combine_cacheattrs inst= ead of failing if the second cache attributes struct is not in that format. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/ptw.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4d97a24808..8b037c1f55 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2108,7 +2108,11 @@ static uint8_t combined_attrs_nofwb(CPUARMState *env, { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + if (s2.is_s2_format) { + s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + } else { + s2_mair_attrs =3D s2.attrs; + } =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2166,6 +2170,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) static uint8_t combined_attrs_fwb(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2) { + assert(s2.is_s2_format && !s1.is_s2_format); + switch (s2.attrs) { case 7: /* Use stage 1 attributes */ @@ -2215,7 +2221,6 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *= env, ARMCacheAttrs ret; bool tagged =3D false; =20 - assert(s2.is_s2_format && !s1.is_s2_format); ret.is_s2_format =3D false; =20 if (s1.attrs =3D=3D 0xf0) { --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657811173; cv=none; d=zohomail.com; s=zohoarc; b=OEaGDhP/IZmJ4iwgN3n+YRnGDtgbuSvKODePVr5T4pqg/0+qc60cPLundfNwOq8/SC0EXeWgahRU+QztEDKu6iBbzocoYzoz6PW1t00dLBnyL2t8dvGOiPez2dp+7zPYVUR5du7xl/ljlzpf5bvwGGh7dwfrbtA02bU4GBqK6yo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657811173; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657810830; x=1689346830; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w5IQxraxoSArUuftBd37e45My2CIyqHLGOT+dh/Y/3U=; b=NYu0ZH9Mo3hUcdvO3BMtut0tVzCjYWYkFQi26YUaSZFMcwFvlcrfpjwr FUDvNca5c/bSHYsgKcBZwhQdni1PNDLO1e/VZAuFuIKiF40XEwEVs6Jrf qSRvMJG2DckuED9xZVvb1Z4g5+x7QRRdVjE6xilyU3lvskvDqp8KZd+Hs g=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 06/11] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup Date: Thu, 14 Jul 2022 16:53:50 +0200 Message-ID: <20220714145355.7225-7-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657811174583100001 From: Tobias R=C3=B6hmel Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup to prepare for the = Cortex-R52 MPU which uses and combines cache attributes of different transl= ation levels. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/internals.h | 13 +++++++------ target/arm/m_helper.c | 3 ++- target/arm/ptw.c | 11 +++++++---- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6f94f3019d..b03049d920 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1109,12 +1109,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t = address, MMUAccessType access_type, ARMMMUIdx mmu_idx, V8M_SAttributes *sattrs); =20 -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); - /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { /* @@ -1126,6 +1120,13 @@ typedef struct ARMCacheAttrs { bool is_s2_format:1; } ARMCacheAttrs; =20 +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion, + ARMCacheAttrs *cacheattrs); + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index a740c3e160..44c80d733a 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2829,10 +2829,11 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t = addr, uint32_t op) * inspecting the other MPU state. */ if (arm_current_el(env) !=3D 0 || alt) { + ARMCacheAttrs cacheattrs =3D {0}; /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, &attrs, &prot, &is_subpage, - &fi, &mregion); + &fi, &mregion, &cacheattrs); if (mregion =3D=3D -1) { mrvalid =3D false; mregion =3D 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b037c1f55..c4f5721012 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1702,7 +1702,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) + ARMMMUFaultInfo *fi, uint32_t *mregion, + ARMCacheAttrs *cacheattrs) { /* * Perform a PMSAv8 MPU lookup (without also doing the SAU check @@ -1968,7 +1969,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cache= attrs) { uint32_t secure =3D regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs =3D {}; @@ -2036,7 +2037,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, } =20 ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); + txattrs, prot, &mpu_is_subpage, fi, + NULL, cacheattrs); *page_size =3D sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; return ret; } @@ -2416,7 +2418,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - phys_ptr, attrs, prot, page_size, f= i); + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 07/11] target/arm: Enable TTBCR_EAE for ARM_FEATURE_V8_R Date: Thu, 14 Jul 2022 16:53:51 +0200 Message-ID: <20220714145355.7225-8-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:13 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657817942513100001 From: Tobias R=C3=B6hmel Enable TTBCR_EAE during reset since it's always set to 1 for Cortex-R52. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2c26a5387d..121fc2a819 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -261,6 +261,9 @@ static void arm_cpu_reset(DeviceState *dev) if (arm_feature(env, ARM_FEATURE_V8_R)) { env->cp15.rvbar =3D cpu->rvbar_prop; env->regs[15] =3D cpu->rvbar_prop; + env->cp15.tcr_el[0].raw_tcr =3D TTBCR_EAE; + env->cp15.tcr_el[1].raw_tcr =3D TTBCR_EAE; + env->cp15.tcr_el[2].raw_tcr =3D TTBCR_EAE; } } =20 --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657817429; cv=none; d=zohomail.com; s=zohoarc; b=UxdtmDNRbiERLvcQQ3FuLVlerjxJwp3BbhsRLht54EDjIrk5kaxLeAAHxZhBLUfPXTIDKChsgzGJkaUDWNSUf4KcQcioiuqzYo6O3PFF0dL8Zku4BJGaXgoM336j75ybYao4kUVZxV37H6J1v/JuOsqtR5culSZ2o3UuA4PLOF8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=quic_trohmel@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:13 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657817430310100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel --- target/arm/cpu.h | 10 +++ target/arm/helper.c | 171 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 181 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 86e06116a9..632d0d13c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -726,8 +726,18 @@ typedef struct CPUArchState { */ uint32_t *rbar[M_REG_NUM_BANKS]; uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t prbarn[255]; + uint32_t prlarn[255]; + uint32_t hprbarn[255]; + uint32_t hprlarn[255]; uint32_t mair0[M_REG_NUM_BANKS]; uint32_t mair1[M_REG_NUM_BANKS]; + uint32_t prbar; + uint32_t prlar; + uint32_t prselr; + uint32_t hprbar; + uint32_t hprlar; + uint32_t hprselr; } pmsav8; =20 /* v8M SAU */ diff --git a/target/arm/helper.c b/target/arm/helper.c index bdf1df37d5..adbf282d00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7422,6 +7422,78 @@ static CPAccessResult access_joscr_jmcr(CPUARMState = *env, return CP_ACCESS_OK; } =20 +static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.prbarn[env->pmsav8.prselr] =3D value; +} + +static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.prlarn[env->pmsav8.prselr] =3D value; +} + +static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.prbarn[env->pmsav8.prselr]; +} + +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.prlarn[env->pmsav8.prselr]; +} + +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.hprbarn[env->pmsav8.hprselr] =3D value; +} + +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pmsav8.hprlarn[env->pmsav8.hprselr] =3D value; +} + +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t n; + ARMCPU *cpu =3D env_archcpu(env); + for (n =3D 0; n < (int)cpu->pmsav7_dregion; ++n) { + if (value & (1 << n)) { + env->pmsav8.hprlarn[n] |=3D 0x1; + } else { + env->pmsav8.hprlarn[n] &=3D (~0x1); + } + } +} + +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprbarn[env->pmsav8.hprselr]; +} + +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprlarn[env->pmsav8.hprselr]; +} + +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t n; + uint32_t result =3D 0x0; + ARMCPU *cpu =3D env_archcpu(env); + + for (n =3D 0; n < (int)cpu->pmsav7_dregion; ++n) { + if (env->pmsav8.hprlarn[n] & 0x1) { + result |=3D (0x1 << n); + } + } + return result; +} + static const ARMCPRegInfo jazelle_regs[] =3D { { .name =3D "JIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, @@ -8242,6 +8314,46 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; + /* PMSAv8-R registers*/ + ARMCPRegInfo id_pmsav8_r_reginfo[] =3D { + { .name =3D "HMPUIR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 4, .opc2 =3D 4, + .access =3D PL2_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav7_dregion}, + /* PMSAv8-R registers */ + { .name =3D "PRBAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .readfn =3D prbar_read, .writefn =3D prbar_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prbar)}, + { .name =3D "PRLAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .resetvalue =3D 0, + .readfn =3D prlar_read, .writefn =3D prlar_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prlar)}, + { .name =3D "PRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prselr)}, + { .name =3D "HPRBAR", .resetvalue =3D 0, + .readfn =3D hprbar_read, .writefn =3D hprbar_write, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprbar)}, + { .name =3D "HPRLAR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .readfn =3D hprlar_read, .writefn =3D hprlar_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprlar)}, + { .name =3D "HPRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprselr)}, + { .name =3D "HPRENR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .readfn =3D hprenr_read, .writefn =3D hprenr_write}, + }; static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, @@ -8283,6 +8395,65 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V8_R)) { + uint32_t i =3D 0; + char hprbar_string[] =3D "HPRBAR%u"; + char hprlar_string[] =3D "HPRLAR%u"; + + char prbar_string[] =3D "PRBAR%u"; + char prlar_string[] =3D "PRLAR%u"; + char tmp_string[50]; + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + define_arm_cp_regs(cpu, id_pmsav8_r_reginfo); + for (i =3D 0; i < cpu->pmsav7_dregion; ++i) { + uint8_t crm =3D 0b1000 | ((i & 0b1110) >> 1); + uint8_t opc2 =3D (i & 0x1) << 2; + + sprintf(tmp_string, hprbar_string, i); + ARMCPRegInfo tmp_hprbarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprbarn) + + i * sizeof(env->pmsav8.hprbarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); + + sprintf(tmp_string, prbar_string, i); + ARMCPRegInfo tmp_prbarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prbarn) + + i * sizeof(env->pmsav8.prbarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); + + opc2 =3D (i & 0x1) << 2 | 0x1; + sprintf(tmp_string, hprlar_string, i); + ARMCPRegInfo tmp_hprlarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprlarn) + + i * sizeof(env->pmsav8.hprlarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); + + sprintf(tmp_string, prlar_string, i); + ARMCPRegInfo tmp_prlarn_reginfo =3D { + .name =3D tmp_string, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D crm, .op= c2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.prlarn) + + i * sizeof(env->pmsav8.prlarn[0]) + }; + define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657811933; cv=none; d=zohomail.com; s=zohoarc; b=jQ/e9a58bXRpEj0fLp2C+Xi40FmN294xewGDugVuoRB4/wUFPzCoR9A7LVPGqHNc5tPb4+oLopB48Rja8o4V+JR3axUGpaugyY8jbcXHJQuvS7eA20112wYa2ayv1S6KCe8LosDELPAfiewF7U2a0EOHPtT2aftwJI5KeDzax3U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657811933; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657810832; x=1689346832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rDDYPyAsKAP+4QMNBSGjqis1xptYRxkRlQgJvjG+XY4=; b=xrcYQBNllWDb5mPD23NacbcXb7rlXfW2yZg1FzRmHwk7M2wei0CSkXpQ q/5Cu4oJjgt6Xkx9bPi+rA9+fKWJstqaXBeWHaDESRmLQ0atjAQ2L9MO1 hSIDW6Gwa5c6mJPezy431tkhrRIKZqfJcnZba6I+7gBvplq1C7qcB+F9t M=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 09/11] target/arm: Add PMSAv8r functionality Date: Thu, 14 Jul 2022 16:53:53 +0200 Message-ID: <20220714145355.7225-10-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657811935276100001 From: Tobias R=C3=B6hmel Add PMSAv8r translation that is used by the ARM Cortex-R52. Signed-off-by: Tobias R=C3=B6hmel --- target/arm/ptw.c | 171 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 150 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c4f5721012..c7e37c66d0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -140,6 +140,9 @@ static bool regime_translation_disabled(CPUARMState *en= v, ARMMMUIdx mmu_idx) */ return true; } + } else if (arm_feature(env, ARM_FEATURE_V8_R)) { + return !(regime_sctlr(env, mmu_idx) & SCTLR_M) || + (!(regime_el(env, mmu_idx) =3D=3D 2) && arm_hcr_el2_eff(env) & HCR= _TGE); } =20 hcr_el2 =3D arm_hcr_el2_eff(env); @@ -1504,6 +1507,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,= ARMMMUIdx mmu_idx, if (arm_feature(env, ARM_FEATURE_M)) { return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + } else if (arm_feature(env, ARM_FEATURE_V8_R)) { + return false; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } @@ -1698,6 +1703,77 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, return !(*prot & (1 << access_type)); } =20 +static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprbarn; + } else { + return env->pmsav8.prbarn; + } + } else { + return env->pmsav8.rbar[secure]; + } +} + +static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprlarn; + } else { + return env->pmsav8.prlarn; + } + } else { + return env->pmsav8.rlar[secure]; + } +} + +static inline void get_phys_addr_pmsav8_default(CPUARMState *env, + ARMMMUIdx mmu_idx, + uint32_t address, int *pro= t) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + *prot =3D PAGE_READ | PAGE_WRITE; + if (address <=3D 0x7FFFFFFF) { + *prot |=3D PAGE_EXEC; + } + if ((regime_el(env, mmu_idx) =3D=3D 2) + && (regime_sctlr(env, mmu_idx) & SCTLR_WXN) + && (regime_sctlr(env, mmu_idx) & SCTLR_M)) { + *prot &=3D ~PAGE_EXEC; + } + } else { + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } +} + +static bool pmsav8_fault(bool hit, CPUARMState *env, ARMMMUIdx mmu_idx) +{ + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + if (!hit && (mmu_idx !=3D ARMMMUIdx_E2)) { + return true; + } else if (!hit && (mmu_idx =3D=3D ARMMMUIdx_E2) + &&!(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + return true; + } + } else { + if (!hit && (mmu_idx !=3D ARMMMUIdx_Stage1_E1)) { + return true; + } else if (!hit && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1) + &&!(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { + return true; + } + } + return false; + } else { + return !hit; + } +} + bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, @@ -1730,6 +1806,12 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, *mregion =3D -1; } =20 + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + fi->stage2 =3D true; + } + } + /* * Unlike the ARM ARM pseudocode, we don't need to check whether this * was an exception vector read from the vector table (which is always @@ -1746,17 +1828,26 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, hit =3D true; } =20 + uint32_t bitmask; + if (arm_feature(env, ARM_FEATURE_V8_R)) { + bitmask =3D 0x3f; + } else { + bitmask =3D 0x1f; + } + + for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ /* - * Note that the base address is bits [31:5] from the register - * with bits [4:0] all zeroes, but the limit address is bits - * [31:5] from the register with bits [4:0] all ones. + * Note that the base address is bits [31:x] from the register + * with bits [x-1:0] all zeroes, but the limit address is bits + * [31:x] from the register with bits [x:0] all ones. Where x = is + * 5 for Cortex-M and 6 for Cortex-R */ - uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; + uint32_t base =3D regime_rbar(env, mmu_idx, secure)[n] & ~bitm= ask; + uint32_t limit =3D regime_rlar(env, mmu_idx, secure)[n] | bitm= ask; =20 - if (!(env->pmsav8.rlar[secure][n] & 0x1)) { + if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) { /* Region disabled */ continue; } @@ -1799,22 +1890,25 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, } } =20 - if (!hit) { - /* background fault */ - fi->type =3D ARMFault_Background; + if (pmsav8_fault(hit, env, mmu_idx)) { + fi->type =3D ARMFault_Permission; + fi->level =3D 0; return true; } =20 if (matchregion =3D=3D -1) { /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + get_phys_addr_pmsav8_default(env, mmu_idx, address, prot); } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + uint32_t ap =3D extract32(regime_rbar(env, + mmu_idx, secure)[matchregion], 1, 2); + uint32_t xn =3D extract32(regime_rbar(env, + mmu_idx, secure)[matchregion], 0, 1); bool pxn =3D false; =20 if (arm_feature(env, ARM_FEATURE_V8_1M)) { - pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + pxn =3D extract32(regime_rlar(env, + mmu_idx, secure)[matchregion], 4, 1); } =20 if (m_is_system_region(env, address)) { @@ -1822,14 +1916,42 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, xn =3D 1; } =20 - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (arm_feature(env, ARM_FEATURE_V8_R)) { + if (regime_el(env, mmu_idx) =3D=3D 2) { + *prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_E2); + } else { + *prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_Sta= ge1_E1); + } + + if (regime_sctlr(env, mmu_idx) & SCTLR_WXN + && (*prot & PAGE_WRITE)) { + xn =3D 0x1; + } + + if ((regime_el(env, mmu_idx) =3D=3D 1) && regime_sctlr(env, mm= u_idx) + & SCTLR_UWXN && (ap =3D=3D 0x1)) { + xn =3D 0x1; + } + + uint8_t attrindx =3D extract32(regime_rlar(env, + mmu_idx, secure)[matchregion], 1,= 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + uint8_t sh =3D extract32(regime_rlar(env, + mmu_idx, secure)[matchregion], 3, 2); + assert(attrindx <=3D 4); + cacheattrs->is_s2_format =3D false; + cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + cacheattrs->shareability =3D sh; + } else { + *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + } + if (*prot && !xn && !(pxn && !is_user)) { *prot |=3D PAGE_EXEC; } - /* - * We don't need to look the attribute up in the MAIR0/MAIR1 - * registers because that only tells us about cacheability. - */ + if (mregion) { *mregion =3D matchregion; } @@ -2342,9 +2464,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; =20 /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, - phys_ptr, attrs, &s2_prot, - page_size, fi, &cacheattrs2); + if (arm_feature(env, ARM_FEATURE_V8_R)) { + ret =3D get_phys_addr_pmsav8(env, ipa, access_type, s2_mmu= _idx, + phys_ptr, attrs, &s2_prot, page_siz= e, + fi, &cacheattrs2); + } else { + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_i= dx, + is_el0, phys_ptr, attrs, &s2_prot, + page_size, fi, &cacheattrs2); + } + fi->s2addr =3D ipa; /* Combine the S1 and S2 perms. */ *prot &=3D s2_prot; --=20 2.25.1 From nobody Tue Feb 10 03:16:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1657818357; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 14 Jul 2022 07:54:26 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Jul 2022 07:54:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657810467; x=1689346467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WhFipYl+TSpogS8hKIuOhUU01/WRbUB4Iq3S2ffW3BY=; b=C66G0vHAxwJNc3fcNKO98FYBOUIQEEJ5VMW0DizwlG2K4ptfoZQVFW/H JLTUAQY/+bOKDdQySh8N5dtu4JU396EBacSKHZyayYvlfueMZ1P/RyQH3 /w++4ApPAcEZitKteBggxWUWJCxM8mJQPVo/eI1XTw/YBZX51gT+temEu g=; X-QCInternal: smtphost From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 10/11] target/arm: Make SPSR_hyp accessible for Cortex-R52 Date: Thu, 14 Jul 2022 16:53:54 +0200 Message-ID: <20220714145355.7225-11-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:13 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657818357508100001 From: Tobias R=C3=B6hmel The Cortex-R52 can access SPSR_hyp from hypervisor mode as discussed here: https://github.com/zephyrproject-rtos/zephyr/issues/47330 Signed-off-by: Tobias R=C3=B6hmel --- target/arm/op_helper.c | 8 ++++++++ target/arm/translate.c | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c5bde1cfcc..aa019bc39d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -522,6 +522,11 @@ static void msr_mrs_banked_exc_checks(CPUARMState *env= , uint32_t tgtmode, return; } =20 + if (curmode =3D=3D ARM_CPU_MODE_HYP && tgtmode =3D=3D ARM_CPU_MODE_HYP + && arm_feature(env, ARM_FEATURE_V8_R)) { + return; + } + if (curmode =3D=3D tgtmode) { goto undef; } @@ -570,6 +575,9 @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t valu= e, uint32_t tgtmode, switch (regno) { case 16: /* SPSRs */ env->banked_spsr[bank_number(tgtmode)] =3D value; + if (arm_feature(env, ARM_FEATURE_V8_R)) { + env->spsr =3D value; + } break; case 17: /* ELR_Hyp */ env->elr_el[2] =3D value; diff --git a/target/arm/translate.c b/target/arm/translate.c index 6617de775f..c097f7e417 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2881,8 +2881,9 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, * can be accessed also from Hyp mode, so forbid accesses from * EL0 or EL1. */ - if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 || - (s->current_el < 3 && *regno !=3D 17)) { + if (!arm_dc_feature(s, ARM_FEATURE_V8_R) + && (!arm_dc_feature(s, ARM_FEATURE_EL2) + || s->current_el < 2 || (s->current_el < 3 && *regno !=3D 17))= ) { goto undef; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=quic_trohmel@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:13 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1657817656751100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel --- configs/devices/arm-softmmu/default.mak | 1 + hw/arm/Kconfig | 5 + hw/arm/meson.build | 1 + hw/arm/r52_machine.c | 133 +++++++++++++++ hw/arm/r52_virt.c | 217 ++++++++++++++++++++++++ include/hw/arm/r52_virt.h | 61 +++++++ 6 files changed, 418 insertions(+) create mode 100644 hw/arm/r52_machine.c create mode 100644 hw/arm/r52_virt.c create mode 100644 include/hw/arm/r52_virt.h diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 6985a25377..4df0844080 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -42,3 +42,4 @@ CONFIG_FSL_IMX6UL=3Dy CONFIG_SEMIHOSTING=3Dy CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy CONFIG_ALLWINNER_H3=3Dy +CONFIG_CORTEX_R52_VIRT=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 219262a8da..72ec0bb656 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -565,3 +565,8 @@ config ARMSSE select UNIMP select SSE_COUNTER select SSE_TIMER + +config CORTEX_R52_VIRT + bool + select ARM_GIC + select PL011 diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 2d8381339c..2a0cdb9c83 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -43,6 +43,7 @@ arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('= stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c',= 'xlnx-zcu102.c')) +arm_ss.add(when: 'CONFIG_CORTEX_R52_VIRT', if_true: files('r52_virt.c', 'r= 52_machine.c')) arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xl= nx-versal-virt.c')) arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_= pdk.c')) arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'= )) diff --git a/hw/arm/r52_machine.c b/hw/arm/r52_machine.c new file mode 100644 index 0000000000..33e9764793 --- /dev/null +++ b/hw/arm/r52_machine.c @@ -0,0 +1,133 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/r52_virt.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qom/object.h" + +struct r52MachineState { + MachineState parent_obj; + + ArmR52VirtState soc; + + bool secure; + bool virt; + + struct arm_boot_info binfo; +}; + +#define TYPE_R52_MACHINE MACHINE_TYPE_NAME("r52") +OBJECT_DECLARE_SIMPLE_TYPE(r52MachineState, R52_MACHINE) + + +static bool r52_get_secure(Object *obj, Error **errp) +{ + r52MachineState *s =3D R52_MACHINE(obj); + + return s->secure; +} + +static void r52_set_secure(Object *obj, bool value, Error **errp) +{ + r52MachineState *s =3D R52_MACHINE(obj); + + s->secure =3D value; +} + +static bool r52_get_virt(Object *obj, Error **errp) +{ + r52MachineState *s =3D R52_MACHINE(obj); + + return s->virt; +} + +static void r52_set_virt(Object *obj, bool value, Error **errp) +{ + r52MachineState *s =3D R52_MACHINE(obj); + + s->virt =3D value; +} + +static void r52_init(MachineState *machine) +{ + r52MachineState *s =3D R52_MACHINE(machine); + uint64_t ram_size =3D machine->ram_size; + + object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_ARMR52VI= RT); + + object_property_set_bool(OBJECT(&s->soc), "secure", s->secure, + &error_fatal); + object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, + &error_fatal); + + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); + + s->binfo.ram_size =3D ram_size; + s->binfo.loader_start =3D 0; + s->binfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); +} + +static void r52_machine_instance_init(Object *obj) +{ + r52MachineState *s =3D R52_MACHINE(obj); + + /* Default to secure mode being disabled */ + s->secure =3D false; + /* Default to virt (EL2) being enabled */ + s->virt =3D true; +} + +static void r52_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Cortex-R52 platform"; + mc->init =3D r52_init; + mc->block_default_type =3D IF_IDE; + mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; + mc->max_cpus =3D ARMR52_VIRT_NUM_APU_CPUS; + mc->default_cpus =3D ARMR52_VIRT_NUM_APU_CPUS; + + object_class_property_add_bool(oc, "secure", r52_get_secure, + r52_set_secure); + object_class_property_set_description(oc, "secure", + "Set on/off to enable/disable th= e ARM " + "Security Extensions (TrustZone)= "); + + object_class_property_add_bool(oc, "virtualization", r52_get_virt, + r52_set_virt); + object_class_property_set_description(oc, "virtualization", + "Set on/off to enable/disable em= ulating a " + "guest CPU which implements the = ARM " + "Virtualization Extensions"); +} + +static const TypeInfo r52_machine_init_typeinfo =3D { + .name =3D TYPE_R52_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D r52_machine_class_init, + .instance_init =3D r52_machine_instance_init, + .instance_size =3D sizeof(r52MachineState), +}; + +static void r52_machine_init_register_types(void) +{ + type_register_static(&r52_machine_init_typeinfo); +} + +type_init(r52_machine_init_register_types) diff --git a/hw/arm/r52_virt.c b/hw/arm/r52_virt.c new file mode 100644 index 0000000000..edf3dadb0e --- /dev/null +++ b/hw/arm/r52_virt.c @@ -0,0 +1,217 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/arm/r52_virt.h" +#include "hw/intc/arm_gic_common.h" +#include "hw/misc/unimp.h" +#include "hw/boards.h" +#include "sysemu/kvm.h" +#include "sysemu/sysemu.h" +#include "kvm_arm.h" + +#define GIC_NUM_SPI_INTR 160 + +#define ARM_PHYS_TIMER_PPI 30 +#define ARM_VIRT_TIMER_PPI 27 +#define ARM_HYP_TIMER_PPI 26 +#define ARM_SEC_TIMER_PPI 29 +#define GIC_MAINTENANCE_PPI 25 + +#define GIC_BASE_ADDR 0xaf000000 +#define GIC_REDIST_ADDR 0xaf100000 + +static const uint64_t uart_addr[ARMR52_VIRT_NUM_UARTS] =3D { + 0x9c090000, +}; + +static const int uart_intr[ARMR52_VIRT_NUM_UARTS] =3D { + 5, +}; + +static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) +{ + return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; +} + +static void armr52_virt_init(Object *obj) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + ArmR52VirtState *s =3D ARMR52VIRT(obj); + int i; + int num_apus =3D MIN(ms->smp.cpus, ARMR52_VIRT_NUM_APU_CPUS); + + object_initialize_child(obj, "apu-cluster", &s->apu_cluster, + TYPE_CPU_CLUSTER); + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + + for (i =3D 0; i < num_apus; i++) { + object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", + &s->apu_cpu[i], + ARM_CPU_TYPE_NAME("cortex-r52")); + } + + object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); + + + for (i =3D 0; i < ARMR52_VIRT_NUM_UARTS; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], + TYPE_PL011); + } +} + +static void armr52_virt_realize(DeviceState *dev, Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + ArmR52VirtState *s =3D ARMR52VIRT(dev); + uint8_t i; + int num_apus =3D MIN(ms->smp.cpus, ARMR52_VIRT_NUM_APU_CPUS); + const char *boot_cpu =3D s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; + qemu_irq gic_spi[GIC_NUM_SPI_INTR]; + Error *err =3D NULL; + + memory_region_init_ram(&s->ddr_ram, NULL, "armr52virt.dram", 0x0400000= 0, + &error_fatal); + memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram); + + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", NUM_IRQS + 32); + qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 3); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); + qdev_prop_set_uint32(DEVICE(&s->gic), "len-redist-region-count", 1); + qdev_prop_set_uint32(DEVICE(&s->gic), "redist-region-count[0]", num_ap= us); + + qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); + + for (i =3D 0; i < num_apus; i++) { + const char *name; + + name =3D object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]= )); + if (strcmp(name, boot_cpu)) { + /* + * Secondary CPUs start in powered-down state. + */ + object_property_set_bool(OBJECT(&s->apu_cpu[i]), + "start-powered-off", true, &error_abo= rt); + } else { + s->boot_cpu_ptr =3D &s->apu_cpu[i]; + } + + object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->sec= ure, + NULL); + object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->vir= t, + NULL); + object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", + num_apus, &error_abort); + if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { + return; + } + } + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, GIC_BASE_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_REDIST_ADDR); + + for (i =3D 0; i < num_apus; i++) { + + int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs we use for the virt board. + */ + const int timer_irq[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), irq, + qdev_get_gpio_in(DEVICE(&s->gic), + ppibase + timer_irq[irq= ])); + } + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_VFIQ)); + } + + if (err) { + error_propagate(errp, err); + return; + } + + if (!s->boot_cpu_ptr) { + error_setg(errp, "Boot cpu %s not found", boot_cpu); + return; + } + + for (i =3D 0; i < GIC_NUM_SPI_INTR; i++) { + gic_spi[i] =3D qdev_get_gpio_in(DEVICE(&s->gic), i); + } + + for (i =3D 0; i < ARMR52_VIRT_NUM_UARTS; i++) { + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + gic_spi[uart_intr[i]]); + } + +} + +static Property armr52_virt_props[] =3D { + DEFINE_PROP_STRING("boot-cpu", ArmR52VirtState, boot_cpu), + DEFINE_PROP_BOOL("secure", ArmR52VirtState, secure, false), + DEFINE_PROP_BOOL("virtualization", ArmR52VirtState, virt, false), +}; + +static void armr52_virt_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + device_class_set_props(dc, armr52_virt_props); + dc->realize =3D armr52_virt_realize; +} + +static const TypeInfo armr52_virt_type_info =3D { + .name =3D TYPE_ARMR52VIRT, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(ArmR52VirtState), + .instance_init =3D armr52_virt_init, + .class_init =3D armr52_virt_class_init, +}; + +static void armr52_virt_register_types(void) +{ + type_register_static(&armr52_virt_type_info); +} + +type_init(armr52_virt_register_types) diff --git a/include/hw/arm/r52_virt.h b/include/hw/arm/r52_virt.h new file mode 100644 index 0000000000..0f26745535 --- /dev/null +++ b/include/hw/arm/r52_virt.h @@ -0,0 +1,61 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef ARMR52VIRT_H +#define ARMR52VIRT_H + +#include "hw/arm/boot.h" +#include "hw/intc/arm_gic.h" +#include "hw/char/pl011.h" +#include "include/exec/address-spaces.h" +#include "hw/cpu/cluster.h" +#include "target/arm/cpu.h" +#include "qom/object.h" +#include "hw/intc/arm_gicv3_common.h" + +#define TYPE_ARMR52VIRT "armr52virt" +OBJECT_DECLARE_SIMPLE_TYPE(ArmR52VirtState, ARMR52VIRT) + +#define ARMR52_VIRT_NUM_APU_CPUS 4 +#define ARMR52_VIRT_NUM_UARTS 1 +#define ARMR52_VIRT_GIC_REGIONS 6 + +#define ARCH_TIMER_VIRT_IRQ 11 +#define ARCH_TIMER_S_EL1_IRQ 13 +#define ARCH_TIMER_NS_EL1_IRQ 14 +#define ARCH_TIMER_NS_EL2_IRQ 10 +#define NUM_IRQS 256 + +struct ArmR52VirtState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CPUClusterState apu_cluster; + ARMCPU apu_cpu[ARMR52_VIRT_NUM_APU_CPUS]; + GICv3State gic; + + MemoryRegion ddr_ram; + + PL011State uart[ARMR52_VIRT_NUM_UARTS]; + + char *boot_cpu; + ARMCPU *boot_cpu_ptr; + + /* Has the ARM Security extensions? */ + bool secure; + /* Has the ARM Virtualization extensions? */ + bool virt; + +}; + +#endif --=20 2.25.1