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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id d194-20020a621dcb000000b00525302fe9c4sm7677047pfd.190.2022.07.12.21.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 21:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H0h1mijfb/JBmMIsG1ho4eH5ZlC4TyS0gLWzNfX6jB0=; b=Um2W1PLjch0aH+/d4eDtNA/Xw2OpL6Z6fnYnDEPLyYkGENxcYExIubl6SknSvYwo+Q jZpDWmDw2iZe5/gIbCO2J3eQBXG5hPWqeWC8UZjWIAJ/U5rX7i6xPxrJJA+uWogdwzkH S2fo8Zu1trTE5UVzSGM46Ax8EWi5BsyLtJ9Vkwk/pYslkP6VuMEo8kxniNvYreOIBrsg JINfuxoMahU+jTeKMFUOnSOMfk4A9EmwAoADRS4rm0cCfzpGTr1QRyoGnSDbT0v9hqYq nReQ6TEaE9CnogdI9/fuir68MtEylw7/tMdhvZ5vaygrtkpQv/1tgyjlvV9l7B73R66w F4Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H0h1mijfb/JBmMIsG1ho4eH5ZlC4TyS0gLWzNfX6jB0=; b=n4fCpDXitdryae4ncawfyKvEpIvX7hl+pn3sCg0YNPoYOhxq8sxyJ81Fm85UmUyNbB 99a1uV+N7EKisOgm/RQ7BnMdD5ZJjsos3VTIYiKReeI8KFOxcDHmCTpZQYx2hVk3Yuo2 xZV4BRcK6Z9akwyTtH425TaQa7s3LkuSWbnXCuEUnC1/VKYM7DuA0Jc1Lt5siuqt5Mc7 BGgluzl+TlRRvQPGV6Gb5PVdgAGesF6rpjItKZE10JtLncYsjx8FFWydMkj51CGGJ+Mk SOqZgvLiy3gop7UmZ5E01wmuW8wIM4wlJ0gn+SlkwsBR78C31XzofXyi7/nZuUEcWev7 57jg== X-Gm-Message-State: AJIora8XYduMDxbXYAdKGE55MceMrhgj/0UDu0xsrixZ8F/stttXyehm LUEugFbIh0qbvAMtZci21i2L++NaPdlO5vt+ X-Google-Smtp-Source: AGRyM1t6ZrNmAn/sNVKwxDbG7Eu4hquj24h1tlChErKXa5ufJjvwl6MhkRIKZ7xCe5oEWC3h8ctLCA== X-Received: by 2002:a17:903:26c1:b0:16b:df40:e566 with SMTP id jg1-20020a17090326c100b0016bdf40e566mr1435578plb.121.1657688340781; Tue, 12 Jul 2022 21:59:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: broonie@kernel.org, qemu-arm@nongnu.org Subject: [PATCH 2/2] target/arm: Fix aarch64_sve_change_el for SME Date: Wed, 13 Jul 2022 10:28:48 +0530 Message-Id: <20220713045848.217364-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220713045848.217364-1-richard.henderson@linaro.org> References: <20220713045848.217364-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657688742102100001 Content-Type: text/plain; charset="utf-8" We were only checking for SVE disabled and not taking into account PSTATE.SM to check SME disabled, which resulted in vectors being incorrectly truncated. Signed-off-by: Richard Henderson --- target/arm/helper.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6fff7fc64f..24c45a9bf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11228,6 +11228,21 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsig= ned vq) } } =20 +static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) +{ + int exc_el; + + if (sm) { + exc_el =3D sme_exception_el(env, el); + } else { + exc_el =3D sve_exception_el(env, el); + } + if (exc_el) { + return 0; /* disabled */ + } + return sve_vqm1_for_el_sm(env, el, sm); +} + /* * Notice a change in SVE vector size when changing EL. */ @@ -11236,7 +11251,7 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, { ARMCPU *cpu =3D env_archcpu(env); int old_len, new_len; - bool old_a64, new_a64; + bool old_a64, new_a64, sm; =20 /* Nothing to do if no SVE. */ if (!cpu_isar_feature(aa64_sve, cpu)) { @@ -11256,7 +11271,8 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, * invoke ResetSVEState when taking an exception from, or * returning to, AArch32 state when PSTATE.SM is enabled. */ - if (old_a64 !=3D new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + sm =3D FIELD_EX64(env->svcr, SVCR, SM); + if (old_a64 !=3D new_a64 && sm) { arm_reset_sve_state(env); return; } @@ -11273,10 +11289,13 @@ void aarch64_sve_change_el(CPUARMState *env, int = old_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_vqm1_for_el(env, old_el) : 0); - new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_vqm1_for_el(env, new_el) : 0); + old_len =3D new_len =3D 0; + if (old_a64) { + old_len =3D sve_vqm1_for_el_sm_ena(env, old_el, sm); + } + if (new_a64) { + new_len =3D sve_vqm1_for_el_sm_ena(env, new_el, sm); + } =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { --=20 2.34.1