From nobody Fri May 9 06:43:46 2025
Delivered-To: importer@patchew.org
Authentication-Results: mx.zohomail.com;
dkim=pass;
spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as
permitted sender)
smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org;
dmarc=pass(p=none dis=none) header.from=linaro.org
ARC-Seal: i=1; a=rsa-sha256; t=1657551740; cv=none;
d=zohomail.com; s=zohoarc;
b=MY0wm2R4xFVTlxHcve+7t7YjFza7IcRCNmfHUAHBjkZZXn3VPVzliTCGuYVbIbH1PJSIgPjoY5VWdPtZaLwdid1elZNT/Vv2zHaaN9csu96ept51DEXO+uZ4HZscAyt3vPwbHvuMBP49T6UTY9DglpIMGbQrfffwxDjoq5ykgf4=
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com;
s=zohoarc;
t=1657551740;
h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To;
bh=pCPJDwjnczLHYV5M/KTJGoCxy94q+B5Z63OSCHqyluc=;
b=OQMtA+CMT+AqqJRIEdoortvxHD4Djob22TsSbtRc6FPrMU9tO9ZXhjp4Y+xfKjQx6ZeYrdSPbiL+aFJ0Hk+Ee4mb/OD5Ywy2ZbcM8ZCwMa7GP1PRaibUX/znYXcZAfbW5833jiw3Px6H3BKNKeFWX6N9WcIfCYfuWUnP3VZr7+8=
ARC-Authentication-Results: i=1; mx.zohomail.com;
dkim=pass;
spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as
permitted sender)
smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org;
dmarc=pass header.from=<peter.maydell@linaro.org> (p=none dis=none)
Return-Path: <qemu-devel-bounces+importer=patchew.org@nongnu.org>
Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by
mx.zohomail.com
with SMTPS id 1657551739907422.61660081662694;
Mon, 11 Jul 2022 08:02:19 -0700 (PDT)
Received: from localhost ([::1]:52438 helo=lists1p.gnu.org)
by lists.gnu.org with esmtp (Exim 4.90_1)
(envelope-from <qemu-devel-bounces+importer=patchew.org@nongnu.org>)
id 1oAuvS-0003GC-Kn
for importer@patchew.org; Mon, 11 Jul 2022 11:02:18 -0400
Received: from eggs.gnu.org ([2001:470:142:3::10]:43322)
by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)
(Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)
id 1oAtvs-0006vl-0V
for qemu-devel@nongnu.org; Mon, 11 Jul 2022 09:58:40 -0400
Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:34392)
by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)
(Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)
id 1oAtvg-0002vP-2M
for qemu-devel@nongnu.org; Mon, 11 Jul 2022 09:58:39 -0400
Received: by mail-wm1-x332.google.com with SMTP id
l22-20020a05600c4f1600b003a2e10c8cdeso1715209wmq.1
for <qemu-devel@nongnu.org>; Mon, 11 Jul 2022 06:58:26 -0700 (PDT)
Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2])
by smtp.gmail.com with ESMTPSA id
q123-20020a1c4381000000b00397402ae674sm7595596wma.11.2022.07.11.06.58.24
for <qemu-devel@nongnu.org>
(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
Mon, 11 Jul 2022 06:58:25 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;
h=from:to:subject:date:message-id:in-reply-to:references:mime-version
:content-transfer-encoding;
bh=pCPJDwjnczLHYV5M/KTJGoCxy94q+B5Z63OSCHqyluc=;
b=oG0DMK5vz3naWPKI2RVRz7/n8e3UXVXO/t663HaNAFhG+zpRBpKUI/OGkEEiTrZxQ7
GGysOjQ5YkD05t0B59Zp3UxTf9rFvao90tJhKfLGemkhs7AzfpA2DjtzhJyvk5v01U3B
Ck2tKxlrD9b3Ye8U8HLjeZ2TrdL4ZMWp+jI+PB+xRQ+lUepSK165asXF9OjJ/vR8pC5T
Rwtmk8pytUKGtWniqembBrIkazHDX9jqIt2iRkMI2GPCfGg6DyPNH4T2AlaUI3TPQOlr
WUThhLF1pKjYFAWkOw1nMrE7X52uEC0anIgJGXf+dIQ+1285fYNdZA2gFHf2vyddcFGU
iXkg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20210112;
h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to
:references:mime-version:content-transfer-encoding;
bh=pCPJDwjnczLHYV5M/KTJGoCxy94q+B5Z63OSCHqyluc=;
b=q7JjZkfo5aKLBEw0SLxRwR7FAKMHX6mKqgfAYjgDOv+gc04mji3vXDy29N53uoSxVi
25uJ0yqOkQdIFo99BfcoVBBvY/hWPAeYSKa8kyDdBXzrE2XC8sJZHsWU0veMbAPro5rl
saQiuOcnUmlBeeAQ7KLldBBmf+OQtdVpL1vDHuZLxCWPthboJJfeM5PR8B0lMdE5IN6O
RpTT/T9NV1GLlPcyjlm5DQa9BbqT/p3AxI8JD8VrWQxqcLWldzbO+xk6/mxMQwo6lVzQ
Cpjmh/wXcG0SrQzbucM//QeoNkLZZmsaKtEFQU4Xtk0g1ESqyolv9WFgESFOgTI7BPLE
XhlQ==
X-Gm-Message-State: AJIora8E1zhnX3QW3bvDGqwPQPl5YX5N7L56ysvT+vZ8S8RRLNycycHo
6HY0ddweiuLAuMcgPKVW9J8Blxn6Llperg==
X-Google-Smtp-Source:
AGRyM1sULstjDUc6T+mgVFype+1FcuSTCs4/6lbz9eulTbTeM/Fr2TYYQ1f3m9KQScPvKpHrfOUXGw==
X-Received: by 2002:a05:600c:3491:b0:3a0:4d4a:2e2d with SMTP id
a17-20020a05600c349100b003a04d4a2e2dmr16581497wmq.4.1657547905500;
Mon, 11 Jul 2022 06:58:25 -0700 (PDT)
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 40/45] linux-user/aarch64: Implement SME signal handling
Date: Mon, 11 Jul 2022 14:57:45 +0100
Message-Id: <20220711135750.765803-41-peter.maydell@linaro.org>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220711135750.765803-1-peter.maydell@linaro.org>
References: <20220711135750.765803-1-peter.maydell@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17
as permitted sender) client-ip=209.51.188.17;
envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org;
helo=lists.gnu.org;
Received-SPF: pass client-ip=2a00:1450:4864:20::332;
envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,
T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+importer=patchew.org@nongnu.org>
X-ZohoMail-DKIM: pass (identity @linaro.org)
X-ZM-MESSAGEID: 1657551741381100001
Content-Type: text/plain; charset="utf-8"
From: Richard Henderson <richard.henderson@linaro.org>
Set the SM bit in the SVE record on signal delivery, create the ZA record.
Restore SM and ZA state according to the records present on return.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/signal.c | 167 +++++++++++++++++++++++++++++++++---
1 file changed, 154 insertions(+), 13 deletions(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 22d0b8b4ece..6a2c6e06d28 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -104,6 +104,22 @@ struct target_sve_context {
=20
#define TARGET_SVE_SIG_FLAG_SM 1
=20
+#define TARGET_ZA_MAGIC 0x54366345
+
+struct target_za_context {
+ struct target_aarch64_ctx head;
+ uint16_t vl;
+ uint16_t reserved[3];
+ /* The actual ZA data immediately follows. */
+};
+
+#define TARGET_ZA_SIG_REGS_OFFSET \
+ QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
+#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
+ (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
+#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
+ TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
+
struct target_rt_sigframe {
struct target_siginfo info;
struct target_ucontext uc;
@@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch=
64_ctx *end)
}
=20
static void target_setup_sve_record(struct target_sve_context *sve,
- CPUARMState *env, int vq, int size)
+ CPUARMState *env, int size)
{
- int i, j;
+ int i, j, vq =3D sve_vq(env);
=20
memset(sve, 0, sizeof(*sve));
__put_user(TARGET_SVE_MAGIC, &sve->head.magic);
@@ -207,6 +223,35 @@ static void target_setup_sve_record(struct target_sve_=
context *sve,
}
}
=20
+static void target_setup_za_record(struct target_za_context *za,
+ CPUARMState *env, int size)
+{
+ int vq =3D sme_vq(env);
+ int vl =3D vq * TARGET_SVE_VQ_BYTES;
+ int i, j;
+
+ memset(za, 0, sizeof(*za));
+ __put_user(TARGET_ZA_MAGIC, &za->head.magic);
+ __put_user(size, &za->head.size);
+ __put_user(vl, &za->vl);
+
+ if (size =3D=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
+ return;
+ }
+ assert(size =3D=3D TARGET_ZA_SIG_CONTEXT_SIZE(vq));
+
+ /*
+ * Note that ZA vectors are stored as a byte stream,
+ * with each byte element at a subsequent address.
+ */
+ for (i =3D 0; i < vl; ++i) {
+ uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
+ for (j =3D 0; j < vq * 2; ++j) {
+ __put_user_e(env->zarray[i].d[j], z + j, le);
+ }
+ }
+}
+
static void target_restore_general_frame(CPUARMState *env,
struct target_rt_sigframe *sf)
{
@@ -252,16 +297,28 @@ static void target_restore_fpsimd_record(CPUARMState =
*env,
=20
static bool target_restore_sve_record(CPUARMState *env,
struct target_sve_context *sve,
- int size)
+ int size, int *svcr)
{
- int i, j, vl, vq;
+ int i, j, vl, vq, flags;
+ bool sm;
=20
- if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
+ __get_user(vl, &sve->vl);
+ __get_user(flags, &sve->flags);
+
+ sm =3D flags & TARGET_SVE_SIG_FLAG_SM;
+
+ /* The cpu must support Streaming or Non-streaming SVE. */
+ if (sm
+ ? !cpu_isar_feature(aa64_sme, env_archcpu(env))
+ : !cpu_isar_feature(aa64_sve, env_archcpu(env))) {
return false;
}
=20
- __get_user(vl, &sve->vl);
- vq =3D sve_vq(env);
+ /*
+ * Note that we cannot use sve_vq() because that depends on the
+ * current setting of PSTATE.SM, not the state to be restored.
+ */
+ vq =3D sve_vqm1_for_el_sm(env, 0, sm) + 1;
=20
/* Reject mismatched VL. */
if (vl !=3D vq * TARGET_SVE_VQ_BYTES) {
@@ -278,6 +335,8 @@ static bool target_restore_sve_record(CPUARMState *env,
return false;
}
=20
+ *svcr =3D FIELD_DP64(*svcr, SVCR, SM, sm);
+
/*
* Note that SVE regs are stored as a byte stream, with each byte elem=
ent
* at a subsequent address. This corresponds to a little-endian load
@@ -304,15 +363,57 @@ static bool target_restore_sve_record(CPUARMState *en=
v,
return true;
}
=20
+static bool target_restore_za_record(CPUARMState *env,
+ struct target_za_context *za,
+ int size, int *svcr)
+{
+ int i, j, vl, vq;
+
+ if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ return false;
+ }
+
+ __get_user(vl, &za->vl);
+ vq =3D sme_vq(env);
+
+ /* Reject mismatched VL. */
+ if (vl !=3D vq * TARGET_SVE_VQ_BYTES) {
+ return false;
+ }
+
+ /* Accept empty record -- used to clear PSTATE.ZA. */
+ if (size <=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
+ return true;
+ }
+
+ /* Reject non-empty but incomplete record. */
+ if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
+ return false;
+ }
+
+ *svcr =3D FIELD_DP64(*svcr, SVCR, ZA, 1);
+
+ for (i =3D 0; i < vl; ++i) {
+ uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
+ for (j =3D 0; j < vq * 2; ++j) {
+ __get_user_e(env->zarray[i].d[j], z + j, le);
+ }
+ }
+ return true;
+}
+
static int target_restore_sigframe(CPUARMState *env,
struct target_rt_sigframe *sf)
{
struct target_aarch64_ctx *ctx, *extra =3D NULL;
struct target_fpsimd_context *fpsimd =3D NULL;
struct target_sve_context *sve =3D NULL;
+ struct target_za_context *za =3D NULL;
uint64_t extra_datap =3D 0;
bool used_extra =3D false;
int sve_size =3D 0;
+ int za_size =3D 0;
+ int svcr =3D 0;
=20
target_restore_general_frame(env, sf);
=20
@@ -350,6 +451,14 @@ static int target_restore_sigframe(CPUARMState *env,
sve_size =3D size;
break;
=20
+ case TARGET_ZA_MAGIC:
+ if (za || size < sizeof(struct target_za_context)) {
+ goto err;
+ }
+ za =3D (struct target_za_context *)ctx;
+ za_size =3D size;
+ break;
+
case TARGET_EXTRA_MAGIC:
if (extra || size !=3D sizeof(struct target_extra_context)) {
goto err;
@@ -381,9 +490,16 @@ static int target_restore_sigframe(CPUARMState *env,
}
=20
/* SVE data, if present, overwrites FPSIMD data. */
- if (sve && !target_restore_sve_record(env, sve, sve_size)) {
+ if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
goto err;
}
+ if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
+ goto err;
+ }
+ if (env->svcr !=3D svcr) {
+ env->svcr =3D svcr;
+ arm_rebuild_hflags(env);
+ }
unlock_user(extra, extra_datap, 0);
return 0;
=20
@@ -451,7 +567,8 @@ static void target_setup_frame(int usig, struct target_=
sigaction *ka,
.total_size =3D offsetof(struct target_rt_sigframe,
uc.tuc_mcontext.__reserved),
};
- int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, vq =3D 0, sve_size =3D 0;
+ int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0;
+ int sve_size =3D 0, za_size =3D 0;
struct target_rt_sigframe *frame;
struct target_rt_frame_record *fr;
abi_ulong frame_addr, return_addr;
@@ -461,11 +578,20 @@ static void target_setup_frame(int usig, struct targe=
t_sigaction *ka,
&layout);
=20
/* SVE state needs saving only if it exists. */
- if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
- vq =3D sve_vq(env);
- sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
+ cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)=
), 16);
sve_ofs =3D alloc_sigframe_space(sve_size, &layout);
}
+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+ /* ZA state needs saving only if it is enabled. */
+ if (FIELD_EX64(env->svcr, SVCR, ZA)) {
+ za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
+ } else {
+ za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(0);
+ }
+ za_ofs =3D alloc_sigframe_space(za_size, &layout);
+ }
=20
if (layout.extra_ofs) {
/* Reserve space for the extra end marker. The standard end marker
@@ -512,7 +638,10 @@ static void target_setup_frame(int usig, struct target=
_sigaction *ka,
target_setup_end_record((void *)frame + layout.extra_end_ofs);
}
if (sve_ofs) {
- target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size=
);
+ target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
+ }
+ if (za_ofs) {
+ target_setup_za_record((void *)frame + za_ofs, env, za_size);
}
=20
/* Set up the stack frame for unwinding. */
@@ -536,6 +665,18 @@ static void target_setup_frame(int usig, struct target=
_sigaction *ka,
env->btype =3D 2;
}
=20
+ /*
+ * Invoke the signal handler with both SM and ZA disabled.
+ * When clearing SM, ResetSVEState, per SMSTOP.
+ */
+ if (FIELD_EX64(env->svcr, SVCR, SM)) {
+ arm_reset_sve_state(env);
+ }
+ if (env->svcr) {
+ env->svcr =3D 0;
+ arm_rebuild_hflags(env);
+ }
+
if (info) {
tswap_siginfo(&frame->info, info);
env->xregs[1] =3D frame_addr + offsetof(struct target_rt_sigframe,=
info);
--=20
2.25.1