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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/45] target/arm: Implement SCLAMP, UCLAMP
Date: Mon, 11 Jul 2022 14:57:35 +0100
Message-Id: <20220711135750.765803-31-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 18 +++++++
target/arm/sve.decode | 5 ++
target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++
target/arm/vec_helper.c | 24 +++++++++
4 files changed, 149 insertions(+)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 3a8ce42ab01..92f36d9dbb7 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
=20
+DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#include "helper-sve.h"
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a9e48f07b44..14b3a69c364 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0=
.... \
@psel esz=3D2 imm=3D%psel_imm_s
PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \
@psel esz=3D3 imm=3D%psel_imm_d
+
+### SVE clamp
+
+SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm
+UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9ed3b267fdb..41f8b12259e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7478,3 +7478,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
tcg_temp_free_ptr(ptr);
return true;
}
+
+static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+ tcg_gen_smax_i32(d, a, n);
+ tcg_gen_smin_i32(d, d, m);
+}
+
+static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+ tcg_gen_smax_i64(d, a, n);
+ tcg_gen_smin_i64(d, d, m);
+}
+
+static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec a)
+{
+ tcg_gen_smax_vec(vece, d, a, n);
+ tcg_gen_smin_vec(vece, d, d, m);
+}
+
+static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop[] =3D {
+ INDEX_op_smin_vec, INDEX_op_smax_vec, 0
+ };
+ static const GVecGen4 ops[4] =3D {
+ { .fniv =3D gen_sclamp_vec,
+ .fno =3D gen_helper_gvec_sclamp_b,
+ .opt_opc =3D vecop,
+ .vece =3D MO_8 },
+ { .fniv =3D gen_sclamp_vec,
+ .fno =3D gen_helper_gvec_sclamp_h,
+ .opt_opc =3D vecop,
+ .vece =3D MO_16 },
+ { .fni4 =3D gen_sclamp_i32,
+ .fniv =3D gen_sclamp_vec,
+ .fno =3D gen_helper_gvec_sclamp_s,
+ .opt_opc =3D vecop,
+ .vece =3D MO_32 },
+ { .fni8 =3D gen_sclamp_i64,
+ .fniv =3D gen_sclamp_vec,
+ .fno =3D gen_helper_gvec_sclamp_d,
+ .opt_opc =3D vecop,
+ .vece =3D MO_64,
+ .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 }
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a)
+
+static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+ tcg_gen_umax_i32(d, a, n);
+ tcg_gen_umin_i32(d, d, m);
+}
+
+static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+ tcg_gen_umax_i64(d, a, n);
+ tcg_gen_umin_i64(d, d, m);
+}
+
+static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec a)
+{
+ tcg_gen_umax_vec(vece, d, a, n);
+ tcg_gen_umin_vec(vece, d, d, m);
+}
+
+static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const TCGOpcode vecop[] =3D {
+ INDEX_op_umin_vec, INDEX_op_umax_vec, 0
+ };
+ static const GVecGen4 ops[4] =3D {
+ { .fniv =3D gen_uclamp_vec,
+ .fno =3D gen_helper_gvec_uclamp_b,
+ .opt_opc =3D vecop,
+ .vece =3D MO_8 },
+ { .fniv =3D gen_uclamp_vec,
+ .fno =3D gen_helper_gvec_uclamp_h,
+ .opt_opc =3D vecop,
+ .vece =3D MO_16 },
+ { .fni4 =3D gen_uclamp_i32,
+ .fniv =3D gen_uclamp_vec,
+ .fno =3D gen_helper_gvec_uclamp_s,
+ .opt_opc =3D vecop,
+ .vece =3D MO_32 },
+ { .fni8 =3D gen_uclamp_i64,
+ .fniv =3D gen_uclamp_vec,
+ .fno =3D gen_helper_gvec_uclamp_d,
+ .opt_opc =3D vecop,
+ .vece =3D MO_64,
+ .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 }
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a)
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 9a9c034e36f..f59d3b26eac 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, voi=
d *vm,
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+#define DO_CLAMP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz =3D simd_oprsz(desc); \
+ for (i =3D 0; i < opr_sz; i +=3D sizeof(TYPE)) { =
\
+ TYPE aa =3D *(TYPE *)(a + i); \
+ TYPE nn =3D *(TYPE *)(n + i); \
+ TYPE mm =3D *(TYPE *)(m + i); \
+ TYPE dd =3D MIN(MAX(aa, nn), mm); \
+ *(TYPE *)(d + i) =3D dd; \
+ } \
+ clear_tail(d, opr_sz, simd_maxsz(desc)); \
+}
+
+DO_CLAMP(gvec_sclamp_b, int8_t)
+DO_CLAMP(gvec_sclamp_h, int16_t)
+DO_CLAMP(gvec_sclamp_s, int32_t)
+DO_CLAMP(gvec_sclamp_d, int64_t)
+
+DO_CLAMP(gvec_uclamp_b, uint8_t)
+DO_CLAMP(gvec_uclamp_h, uint16_t)
+DO_CLAMP(gvec_uclamp_s, uint32_t)
+DO_CLAMP(gvec_uclamp_d, uint64_t)
--=20
2.25.1